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Oxford Cambridge and RSA
Level 3 Cambridge Technical in Engineering05822/05823/05824/05825/05873
Unit 4: Principles of electrical and electronic engineeringTuesday 23 May 2017 – MorningTime allowed: 1 hour 30 minutes
You must have:• the formula booklet for Level 3 Cambridge
Technicals in Engineering (inserted)• a ruler (cm/mm) • a scientific calculator
First Name Last Name
CentreNumber
CandidateNumber
Date of Birth D D M M Y Y Y Y
INSTRUCTIONS• Use black ink. You may use an HB pencil for graphs and diagrams.• Complete the boxes above with your name, centre number, candidate number and date of birth.• Answer all the questions.• Write your answer to each question in the space provided. If additional space is required, you
should use the lined page(s) at the end of this booklet. The question number(s) must beclearly shown.
INFORMATION• The total mark for this paper is 60.• The marks for each question are shown in brackets [ ].• Where appropriate, your answers should be supported with working.• Marks may be given for a correct method even if the answer is incorrect.• An answer may receive no marks unless you show sufficient detail of the
working to indicate that a correct method is being used.• Final answers should be given to a degree of accuracy appropriate to the
context.• This document consists of 12 pages.
© OCR 2017 [601/4593/6, 601/4594/8, 601/4600/X, 601/4599/7]
C304/1706/3 OCR is an exempt Charity Turn over
FOR EXAMINER USE ONLY
Question No Mark
1 /122 /123 /64 /125 /66 /12
Total /60
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Answer all the questions.
1 Fig.1 shows a fi ve resistor network.
R total
15 kΩ
2.2 kΩ
4.7 kΩ
3.3 kΩ
10 kΩ
Fig.1
(a) Calculate the total resistance R total.
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(b) Fig. 2 shows a circuit with two fixed resistors.12V
+
1mA
R2R1
Fig. 2
Calculate V2, the voltage drop across R2, when R1 = 4.7 kΩ.
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(c) A DC supply has an internal resistance of 3 Ω and an open circuit voltage of 24 V.
(i) State the value of the load that will enable maximum power transfer.
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(ii) Calculate the power dissipated in the load.
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2 Fig. 3 shows an AC circuit with a 70 Ω resistor, 33 μF capacitor and 0.5H inductor connected in series with a 240V, 50Hz supply.
V+
240 V
70 Ω 33 µF 0.5 H
I50 Hz
Fig. 3
(a) (i) Calculate the phase angle ø.
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(ii) Calculate I.
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(iii) Draw a phasor diagram to represent the circuit shown in Fig. 3.
Show the values of V, I and the phase angle ø clearly on this diagram.
[3]
(b) The instantaneous value of a voltage waveform is represented by v =25sin628.3t.
(i) Calculate the frequency of the waveform.
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(ii) Calculate the periodic time.
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3 Fig. 4 shows the circuit diagram for a shunt wound DC motor.
Field Winding Armature
Fig. 4
(a) Explain with the aid of circuit diagrams two methods of controlling the speed of a shunt wound DC motor.
Method 1
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Method 2
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4 A star connected three phase four wire network is widely used as a system of three phase electricity supply in the UK.
(a) Draw a circuit diagram that shows how this network is connected.
Indicate the phase voltages and the line voltages on the diagram.
[4]
(b) Sketch the waveforms which show one voltage cycle of a three phase supply.
Label phase 1, phase 2 and phase 3 on the sketch.
EMF(V)
30 60 90 120 150 180 210 240 270 300 330 360Phase (˚)
[4]
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(c) State the typical voltage of a three phase supply in the UK.
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(d) Explain with the aid of a circuit diagram how half wave rectification of an AC waveform can be achieved by using a single diode.
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5 A summing amplifier is required for use in an audio mixer circuit.
(a) Draw a circuit diagram of a three input summing amplifier.
[3]
(b) State the formula for Vout in a three input summing amplifier.
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(c) The input resistors in a three input summing amplifier each have a value of 10 k Ω. The feedback resistor is 50K Ω.
Calculate the value of Vout if the input voltages are 0.2 V, 0.5 V and 0.25 V.
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© OCR 2017
6 (a) Complete the table below by drawing the correct logic gate symbol for each Boolean expression.
Boolean Expression Logic Gate Symbol
= .A B
= A B+
= A B+
= A
[4]
(b) A digital system will only operate if three switches X, Y and Z are correctly set. An output signal, Q=1, will occur if switches X and Y are both in the ON position or if X is in the OFF position and Z is in the ON positon. Assume ON=1, OFF =0.
(i) Complete the truth table for the above system.
X Y Z Q0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
[4]
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(ii) Draw a circuit diagram of the combinational logic that will be required in the digital system.
[4]
END OF QUESTION PAPER
Oxford Cambridge and RSA
Copyright Information:OCR is committed to seeking permission to reproduce all third-party content that it uses in its assessment materials. OCR has attempted to identify and contact all copyright holders whose work is used in this paper. To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced in the OCR Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download from our public website (www.ocr.org.uk) after the live examination series.If OCR has unwittingly failed to correctly acknowledge or clear any third-party content in this assessment material OCR will be happy to correct its mistake at the earliest possible opportunity.For queries or further information please contact the Copyright Team, First Floor, 9 Hills Road, Cambridge CB2 1GE.OCR is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of University of Cambridge Local Examinations Syndicate (UCLES), which is itself a department of the University of Cambridge.
© OCR 2017
C304/1706
12
ADDITIONAL ANSWER SPACE
If additional answer space is required, you should use the following lined pages. The question number(s) must be clearly shown – for example 1(d) or 6(b).
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