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User's GuideSLWU029D–October 2006–Revised August 2007
TSW3003 Demonstration Kit
Contents1 Demonstration Kit Configuration Options................................................................................. 32 Block Diagrams .............................................................................................................. 43 Key Texas Instruments Components ..................................................................................... 54 Software Installation ......................................................................................................... 55 Software Operation .......................................................................................................... 56 Board Setup................................................................................................................. 127 Demo Kit Test Configuration.............................................................................................. 138 Basic Test Procedure ...................................................................................................... 239 Optional Configurations.................................................................................................... 2710 Filter Specifications ........................................................................................................ 2911 Bill of Materials and Schematics ......................................................................................... 30
List of Figures
1 System Block Diagram ...................................................................................................... 42 Demo Kit Block Diagram.................................................................................................... 43 TSW3003 Startup Screen .................................................................................................. 64 Default CDCM7005 SPI GUI ............................................................................................... 75 TRF3761 GUI - Main Menu ................................................................................................ 86 TRF3761 GUI - Advanced Menu .......................................................................................... 87 DAC5687 GUI ................................................................................................................ 98 Test System Block Diagram .............................................................................................. 139 Single-Carrier Test Mode 1 WCDMA, Typical Performance With IF=30.72 MHz, LO=2.14 GHz ............... 1510 Missing Middle-Carrier Test Mode 1 WCDMA, Typical Performance With IF=30.72 MHz, LO=2.14 GHz ..... 1611 Four-Carrier Test Mode 1 WCDMA, Typical Performance With IF=153.6 MHz, LO=2.14 GHz ................. 1712 ACPR Versus Output Power for 1Carrier WCDMA .................................................................... 1813 ACPR Versus Output Power for 2 Carriers WCDMA.................................................................. 1814 ACPR Versus Output Power for 3 Carriers WCDMA.................................................................. 1915 ACPR Versus Output Power for 4 Carriers WCDMA.................................................................. 1916 Optimum ACPR for 1 Carrier WCDMA, -7-dB Pad .................................................................... 2017 Optimum ACPR for 2 Carrier WCDMA, -7-dB Pad .................................................................... 2118 Optimum ACPR for 3 Carrier WCDMA, -7-dB Pad .................................................................... 2219 Optimum ACPR for 4 Carrier WCDMA, -7-dB Pad .................................................................... 2320 Default DAC GUI With fDAC/8 Tone From NCO ........................................................................ 2521 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments ................................... 2522 DAC GUI With Typical Settings To Minimize LO and Sideband ..................................................... 2623 Sideband and LO Compensated Using QMC Settings................................................................ 2724 Board Modifications for External LO ..................................................................................... 2825 Jumper Settings to Disable TRF3761 ................................................................................... 2826 Jumper Changes for External VCXO .................................................................................... 29
List of Tables
1 Frequency Bands ............................................................................................................ 32 CDCM7005 Register Values ............................................................................................... 7
Windows is a trademark of Microsoft Corporation.
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3 Jumper List.................................................................................................................. 124 Input/Output Connections ................................................................................................. 125 Demo Kit Typical Specifications.......................................................................................... 146 Frequency Designations................................................................................................... 247 Bill of Materials ............................................................................................................. 30
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1 Demonstration Kit Configuration Options
1.1 DAC Component
1.2 VComm Configuration
1.3 VCXO
1.4 LO Generation
Demonstration Kit Configuration Options
The TSW3003 Demonstration (Demo) Kit can be configured in different ways to evaluate differentcomponents in different frequency bands. This section outlines the various component configurations.Based on the configuration, testing and board setup must be altered to accommodate the givencomponents and features.
The TSW3003 Demo Kit is built for the DAC5687, although this Demo Kit can also support the DAC5686because the two devices are pin compatible. The procedures outlined in this document are primarily suitedfor the DAC5687, but can be modified easily for the DAC5686 if desired.
The analog quadrature modulator requires a common-mode dc voltage of approximately 3.3 V. In order touse the dc-offset adjustment capabilities of the DAC5687 for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maintained with a passive resistor network that is designed to provide the proper operationpoint for the DAC5687 and the TRF3703 modulator. By design, in order to preserve the proper dc levels,the DAC coarse gain should be kept at the maximum (15), though deviation by a few steps is generallyacceptable with no degradation in performance.
The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at referencedesignator U1. The frequency of the VCXO can be changed to operate the Demo Kit with differentclocking schemes for different modulation standards or for specific customer requirements. Denote whichVCXO frequency is on the board so that the CDCM7005 part can be set up properly. The followingconventions are typically used:
• WCDMA: Derivatives of 61.44 MHz (i.e., 122.88 MHz, 245.76 MHz, 491.52 MHz)• GSM: Derivatives of 52 MHz (i.e., 104 MHz, 208 MHz)• CDMA2K: Derivatives of 78.6432 (i.e., 157.2864 MHz, 314.5728 MHz)
The integrated VCO of the TRF3761 outputs the RF signal used for the LO drive on the analog quadraturemodulator. The RF output frequency is contingent on the LO frequency value. The default TRF3761-Htypically has a tuning range from 2028 to 2175 MHz. Other frequency bands will require the existingTRF3761 to be changed to another pin-compatible part in a different frequency band. Using the TRF3761internal divider or another TRF3761 part to generate frequencies outside this range requires the outputterminations to be changed. Contact TI for support in this situation.
The RF frequency band of the VCO must be noted in order to know how to program the TRF3761 and atwhat frequency to measure the output RF signal from the modulator. The typical bands of operation areshown in Table 1.
Table 1. Frequency Bands
UMTS PCS GSM900 DCS1800
FREQUENCY 2110-2170 MHz 1930-1990 MHz 935-960 MHz 1805-1880 MHz
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2 Block Diagrams
2.1 System Block Diagram
DAC
I/QModulator90°
0°
LPA TX
Diplexer
ANT
RX
LNA
A/DI/Q
Demod
2.2 Demo Kit Block Diagram
16
DAC5687
16
CLK1
TRF3703I/Q
Modulator
RF Out
TRF3750VCXO
TRF3761PLL
LO Generator
Ref Osc
CDCM7005Clock Gen
CLK2
Block Diagrams
The basic radio system block diagram in Figure 1 demonstrates where the TSW3003 Demo Kit fits in theoverall transceiver. The dash-line box illustrates the components found on the TSW3003 Demo Kit board.
Figure 1. System Block Diagram
The basic Demo Kit block diagram is shown in Figure 2. The shaded boxes illustrate the key TexasInstruments components found on the TSW3003 Demo Kit board.
Figure 2. Demo Kit Block Diagram
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3 Key Texas Instruments Components
3.1 CDCM7005
3.2 DAC5687
3.3 TRF3703
3.4 TRF3761
4 Software Installation
5 Software Operation
Key Texas Instruments Components
The CDCM7005 clock distribution chip is used to generate and synchronize the clock outputs to thesystem. The device has five outputs which can be either LVPECL or LVCMOS and can be divided downby 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a 90 degreephase shift.
The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates adigital modulator, independent differential offset control, and I/Q amplitude control. The device is typicallyused in baseband mode or in low IF mode with an analog quadrature modulator.
The TRF3703 is a direct upconversion IQ modulator. This device accepts a differential input voltagequadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the LOdrive frequency.
The TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized forwireless infrastructure applications. The TRF3761 includes an integrated VCO and integer-N PLL.Different members of the TRF3761 family can be chosen for application specific VCO frequency ranges.
This section summarizes the installation procedures for the software required to operate the Demo Kit.Once all of the software is loaded, it is recommended to reboot the computer. This software has beenverified to be functional on Win2K and WinXP.
• Execute setup.exe• Reboot computer as required by the Windows™ operating system.• Power up the TSW3003EVM, and plug in the USB cable.• Allow the Windows™ operating system to automatically find and install the TSW3003 USB drivers.• Start the TSW3003 USB Vx.x software.
The following describes the use of the software required to set the TSW3003 Demo Kit in the baselineconfiguration for the CDCM7005, TRF3761, and DAC5687. The software should be configured in theorder presented below. The first step requires starting the TSW3003 software. This opens a window asshown in Figure 3. The tabs on the left side of the window allow selection of different GUI controllers forthe DAC5687, TRF3761, and CDCM7005. The lower left portion of the screen contains links to this user'sguide as well as the data sheets for the DAC5687, TRF3761, and the CDCM7005.
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5.1 CDCM7005 Software
Software Operation
Figure 3. TSW3003 Startup Screen
By using the provided CDCM7005 serial peripheral interface (SPI) software, the user can load settings tothe CDCM7005 internal registers. This must be performed every time the TSW3003 Demo Kit is poweredup, because the CDCM7005 has default settings that are loaded at power up and the settings may beslightly different than the ones required to operate the Demo Kit. Executing the program brings up theinterface seen in Figure 4. The default settings are correct for a VCXO of 491.52 MHz and a 10 MHzreference as on the TSW3003. The CDCM7005 GUI allows register settings to be saved and can beloaded back in afterwards. This can be accomplished with the Save and Load Settings buttons near theright side of the GUI.
It is recommended that any unused output clocks be tri-stated. In this case the TSW3003 only usesOUT_MUX_1 to drive the DAC5687. OUT_MUX_0, OUT_MUX_2, OUT_MUX_3, OUT_MUX_4 should betri-stated unless there is a need to use the other output clocks.
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Software Operation
Figure 4. Default CDCM7005 SPI GUI
The divider parameters, M and N, are determined according to the following equation based on theinternal reference frequency and internal VCXO frequency.
FREF = (FVCXO × M)/(N × P)
The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N countervalues need to be adjusted depending on the board configuration. The M and N counter registers aredetermined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios forthe individual output clocks. The OUTSEL determines whether the output clocks will be used assingle-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settingsare shown in Table 2 for a variety of common VCXO frequencies. A calculator is included in theCDCM7005 GUI software to calculate the M and N values based on Ref and VCXO frequencies.
Table 2. CDCM7005 Register Values
VCXO Freq. (MHz) 491.52 245.76 122.88 61.44
Divider M 125 125 125 125
Divider N 768 768 768 768
FB_MUX 8 4 2 1
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5.2 TRF3761 Software
Software Operation
The TRF3761 software is used to program the internal PLL chip to lock the integrated VCO onto a desiredfrequency output. The main menu of the program is shown in Figure 5.
Figure 5. TRF3761 GUI - Main Menu
The options in the front panel allow the user to program the desired frequency of the VCO, the desiredfrequency of the PFD, the reference frequency, and the prescaler selection. The software then displaysthe actual VCO frequency, PFD frequency and the R, N, A, and B counter values to be programmed intothe TRF3761. Hitting the Send button writes these values to the TRF3761. In default mode on a defaultboard, only the desired VCO frequency (2028 MHz to 2175 MHz) needs to be changed. For other VCOranges, a different member of the TRF3761 family needs to be selected and other parameters may needto be changed. The Advanced Operation button will bring up another user interface as shown in Figure 6.
Figure 6. TRF3761 GUI - Advanced Menu
This menu allows control of more register settings. For details on these settings, see the TRF3761 data
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5.3 DAC5687 Software
5.4 DAC5687 GUI Register Descriptions
5.4.1 Register Controls
Software Operation
sheet (SLWS181). The register of interest in this menu is the MUXOUT CONTROL which can be used todetermine the function of LED D4. This mode defaults to Digital PLL Lock Detect and causes the LED D4to light up when the PLL successfully locks. Normally, these menu settings do not need to be changed. Ifthe divider ratios are changed, the TRF3761 output termination needs to be modified to accommodate thenew output frequency. Otherwise, the performance may be degraded. Contact TI in this situation.
By using the provided software, the user can write and read control register information to the DAC5687.Once the Demo Kit is powered on and connected properly, then the GUI shown in Figure 7 is displayedwith the default settings read from the device. If there is a problem with the communication, such as theDemo Kit is not powered on or the USB cable is not connected, an error message will be displayedinstructing the user to correct the problem. Once corrected, hit the Read All button to read the defaultsettings of the device.
Figure 7. DAC5687 GUI
For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.
• Load Regs – Loads register values from a saved file to the DAC5687 and updates the GUI.• Save Regs – Saves current GUI registers settings to a text file for future use.• Read All – Reads the current registers of the DAC5687. This is used to verify settings on the front
panel.• Send All – Sends the current front panel registers to the device. This is generally only used when the
Demo Kit power has recycled or the device has been reset and the user wants to load the displayedsettings to the device.
• Load Factory Optimization – Load default LO and sideband optimized values for the default boardcondition.
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5.4.2 Configuration Controls
Software Operation
• Full Bypass – When set, all filtering, QMC, and NCO functions are bypassed.• FIR Bypass – Bypass all interpolation filters. QMC INCO functional. Limited to FDAC = 250 MHz• FIFO Bypass – When set to bypass, the internal four sample FIFO is disabled. When cleared, the
FIFO is enabled.• FIR A – A side first FIR filter in high-pass mode when set, low-pass mode when cleared.• FIR B – B side first FIR filter in high-pass mode when set, low-pass mode when cleared.• Dual Clk – Only used when the PLL is disabled. When set, two differential clocks are used to input the
data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is usedas the DAC sample clock.
• Interleave – When set, interleaved input data mode is enabled; both A and B data streams are input atthe DA(15:0) input pins.
• Inverse Sinc – Enables inverse sinc filter.• Half Rate Input – Enables half rate input mode. Input data for the DAC A data path is input to the chip
at half speed using both the DA(15:0) and DB(15:0) input pins.• Sif – Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. The
DAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makesreading registers impossible with the GUI.
• Inv. PLL Lock – Only used when PLL is disabled and dual clock mode is disabled. When cleared,input data is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data islatched into the chip on falling edges of the PLLLOCK output pin.
• PLL Freq – Sets PLL VCO center frequency to low or high center frequency.• PLL Kv – Sets PLL VCO gain to either high or low gain.• Qflag – Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when
interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timingrelationship.
• 2's Comp – When set, input data is interpreted as 2's complement. When cleared, input data isinterpreted as offset binary.
• Rev A Bus – When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.
• Rev B Bus – When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
• USB – When set, the data to DACB is inverted to generate upper side band output.• Inv. Clk I(Q) – Inverts the DAC core sample clock when set, normal when cleared.• Sync_Phstr – When set, the internal clock divider logic is initialized with a PHSTR pin low to high
transition.• Sync_cm – When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.• Sync_NCO – When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.• Phstr Clk Div Select – Selects the clock used to latch the PHSTR input when restarting the internal
clock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided downinput clock signal latches PHSTR.
• DAC Serial Data – When set, both DAC A and DAC B input data is replaced with fixed data loadedinto the 16-bit serial interface DAC Static Data.
– Counter Mode – Controls the internal counter that can be used as the DAC data source: off; all16b; 7b LSBs; 5b MIDs; 5b MSBs.
– DAC Static Data – When DAC Serial Data is set, both DAC A and DAC B input data is replacedwith fixed data loaded with this value. Range = 0 - 65535.
• Alt. PLLLOCK Output – Can be used to determine alternate outputs on the PLLLOCK pin when usingthe internal PLL mode. The EXTLO pin must be open when using this mode.
• NCO – When set, enables NCO.
– NCO Gain – Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for Fs/2and Fs/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs.Consider using QMC gain for lower gains.
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5.4.3 DAC A(B) Gain
5.4.4 NCO
5.4.5 Additional Control/Monitor Registers
Software Operation
• QMC – When set, enables the QMC.
– QMCA Gain – Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.– QMC B Gain – Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.– QMC Phase – Sets QMC phase to a range = -512 to 511. See the data sheet for more information.
Used to adjust for I/Q phase imbalance.• Mode – Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.• PLL Divider – Sets VCO divider to div by 1, 2, 4, or 8.• Interpolation – Sets FIR Interpolation factor: X2, X4, X4L, X8. X4 uses lower power than 4xL, but
Fdac = 320 MHz max when NCO or QMC are used.• Phstr Init. Phase – Adjusts the initial phase of the FS/2 and FS/4 CMIP block at PHSTR.• Sync FIFO – Sync source selection mode for the FIFO. When a low to high transition is detected on
the selected sync source, the FIFO input and output pointers are initialized. See the DAC5687 datasheet for source description.
• DAC Coarse Gain – Sets coarse gain of DAC A(B) full-scale current. Range is 0 to 15. See theDAC5687 data sheet for full-scale gain equation.
• DAC Fine Gain – Sets fine gain of DAC A(B) full scale current. Range is -128 to127. See theDAC5687 data sheet for full-scale gain equation. Used to adjust for I/Q amplitude imbalance.
• DAC DCOffset – Sets DAC A(B) dc-offset register. Range is -4096 to 4095. Used to adjust for carriersuppression.
• Sleep – DAC A(B) sleeps when set, operational when cleared.
• NCO DDS – Sets NCO DDS registers. See the DAC5687 data sheet for formula.• NCO Phase – Sets initial NCO phase registers. See the DAC5687 data sheet for more information.• FDAC (MHz), NCO IF (MHz) – Used to calculate the required NCO DDS value.
• Version – Displays the version of the silicon. If a version of 0 is read then the communication is notfunctioning and an error message will be displayed.
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6 Board Setup
6.1 Jumper Settings
6.2 Input/Output Connectors
Board Setup
The TSW3003 Demo Kit has onboard jumpers that allow the user to selectively disengage devices asdesired. The unit is shipped with jumpers in place that activate all of the devices on board. Table 3explains the functionality of the jumpers on the board.
Table 3. Jumper List
Jumper Label Function Condition Default
JP1 VCXOB Choose internal VCXO or external VCXO INB Internal VCXO Pin 1, 2
JP2 VCXO Choose internal VCXO or external VCXO INA Internal VCXO Pin 1, 2
SJP3 SJP3 Choose 1.8 or 2.1 VDD 1.8 VDD Pin 1, 2
JP6 REF CLK Choose internal 10-MHz ref or external ref 10 MHz Pin 2, 3
JP8 DEFAULT 3.3VA Choose 3.3V or 1.8V for IOVDD 3.3 VDD Pin 1, 2
J31-2 PLL_VDD PLLVDD GND (OFF) or 3.3V (ON) GND Pin 1, 2
J31-5 SLEEP SLEEP GND (ACTIVE) or 3.3V (SLEEP) GND Pin 4, 5
J31-8 EXTLO Internal (GND) or external (3.3V) voltage reference GND Pin 7, 8
J31-11 TX_ENABLE High enable data for DAC 3.3 V Pin 11, 12
J31-14 TESTMODE GND GND Pin 22, 23
J31-17 No Connect
J31-20 CDC_PD Low active power down of CDCM7005 3.3 V Pin 20, 21
J31-23 PD_OUTBUF Power down output buffer of TRF3761 GND Pin 22, 23
J31-26 CHIP_EN Enable TRF3761 chip 3.3 V Pin 26, 27
J31-29 RESET Low active reset of DAC5687 3.3 V Pin 29, 30
J31-32 PLLLCK_EN Low active PLLLOCK output buffer GND Pin 31, 32
J31-35 (1) No Connect
(1) VCXO does not have Output Enable control.
The input and output connections are shown in Table 4.
Table 4. Input/Output Connections
Reference Designator Connector Type Description
J1 Power Connector 6 VDC from wall adapter
J4 34-pin header External VCXO connection
J7 SMA Optional input clock from CDCM7005
J8 SMA Optional input clock from CDCM7005
J9 SMA Optional input clock from CDCM7005
J27 SMA PLLLLCK output from DAC5687, used to indicate lock or to drive externaldata source
J29 34-pin header DA input to the DAC5687
J30 34-pin header DB input to the DAC5687
J32 SMA RF output from modulator
J34 USB USB connector for GUI software
J35 SMA External Ref clock input
J37 Banana Plug +6-VDC connector for external DC supply
J38 Banana Plug GND connection for external DC supply
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6.3 USB Port
6.4 DC Power Requirements
7 Demo Kit Test Configuration
7.1 Test Setup Block Diagram
TSW3003EVM DUT
J27Clock
PowerSupply GND
+6 V
16
USB
J32PatternGenerator
16
J38 J37
PC Controller
J30
J29
J34
SpectrumAnalyzer
7.2 Test Equipment
Demo Kit Test Configuration
The TSW3003 Demo Kit contains a 4-pin USB port connector (J34) to interface to a standard computerUSB port. Programming of the CDCM7005, DAC5687, and TRF3761 are accomplished through this port.
The Demo Kit requires a single dc-voltage supply that is nominally 6 V. From that supply, the 5 V, 3.3 V,and 1.8 V required for the devices on the board are generated internally through linear voltage regulators.It is possible to use a higher input voltage; however, care should be taken not to over dissipate theonboard voltage regulators.
The test set up for general testing of the TSW3003 Demo Kit is shown in Figure 8.
Figure 8. Test System Block Diagram
The following is a list of the test equipment required for testing the TSW3003 Demo Kit. Equivalent modelsmay be used for certain applications, but may produce different results due to limitations within theinstrument.
• Dual Power Supply: Any with current readout capability or use the supplied 6VDC 4A wall supply• Spectrum Analyzer: Rhode & Schwartz FSU, Agilent PSA, or equivalent
This particular piece can measure >70-dBc ACPR with the noise cancellation option active. Thisamount of dynamic range is required to accurately measure the ACPR of the Demo Kit. Anotherspectrum analyzer can be substituted if it achieves as good or better dynamic range.
• Pattern Generator: Agilent 16720A• Oscilloscope: Tektronix 650 or equivalent
Used to probe clock output signals and for debugging.• Digital Voltmeter: Agilent 34401A or equivalent
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7.3 Calibration
7.4 Test Specifications
Demo Kit Test Configuration
In order to record proper output power the insertion loss of the output cable must calibrated. Measure theinsertion loss of the cable from J32 to the spectrum analyzer; set the analyzer's reference level offset tothat value.
The test specifications are outlined in Table 5.
Table 5. Demo Kit Typical Specifications
MIN MAX UNITS
CURRENT
+6 V 1.5 A
CW TESTS
Carrier suppression 30 dBc
Sideband rejection 25 dBc
Spurious Output
2nd harmonic 45 dBc
Aliased LSB (pos) 40 dBc
Output clock 40 dBc
Aliased USB 15 dBc
Aliased USB (neg) 8 dBc
WCDMA ACPR
Channel power -14 dBm
ACPR -Low 76 dBc
ACPR -High 76 dBc
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A
Ref -17.5 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB*
1 RM
NOR
*
Center 2.17072 GHz Span 25.5 MHz2.55 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz Power -11.85 dBm
Adjacent Channel
Bandwidth 3.84 MHzLower -76.67 dB
Spacing 5 MHz Upper -76.59 dB
Alternate Channel
Bandwidth 3.84 MHzLower -77.96 dB
Spacing 10 MHz Upper -77.75 dB
POS -17.512 dBm
Demo Kit Test Configuration
Figure 9. Single-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=30.72 MHz, LO=2.14 GHz
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A
Ref -20.1 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB*
1 RM
NOR
*
Center 2.17072 GHz Span 35.6 MHz3.56 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -16.46 dBm(Ref)
Ch2 -88.87 dBm
Ch3 -16.56 dBm
Total -13.50 dBm
Adjacent Channel
Lower -72.90 dB
Upper -72.69 dB
Alternate Channel
Lower -72.51 dB
Upper -72.55 dB
POS -20.129 dBm
Demo Kit Test Configuration
Figure 10. Missing Middle-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=30.72 MHz, LO=2.14 GHz
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A
Ref -25.8 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB*
1 RM
NOR
*
Center 2.2936 GHz Span 40.6 MHz4.06 MHz/
EXT
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -22.39 dBm(Ref)
Ch2 -22.48 dBm
Ch3 -22.63 dBm
Ch4 -22.72 dBm
Total -16.53 dBm
Adjacent Channel
Lower -64.03 dB
Upper -64.65 dB
Alternate Channel
Lower -65.48 dB
Upper -64.78 dB
POS -25.811 dBm
7.5 WCDMA Output Power Versus ACPR Performance
Demo Kit Test Configuration
Figure 11. Four-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=153.6 MHz, LO=2.14 GHz
The ACPR has some dependency on the output power of the TSW3003. The RF output spectrum showssome IMD effects as the output power of the DAC is increased. The optimum ACPR performance occurswhen there is approximately a -6dB attenuation pad between the DAC output and the TRF3703 input. Asthe power is increased the IMD3 effects start to affect the ACPR. As the power is decreased, the ACPRbecomes linear as a function of the signal power and the noise floor.
The ACPR results have been tabulated in Figure 12 through Figure 15 for 1, 2, 3, and 4 WCDMA carrierswith the TM1 signal.
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1 Carrier ACPR vs Pout, Baseband 2.14 GHz
-20 -15 -10 -5 0
Pout dBm/Channel
dB
1 ACPR
1 Alt ACPR
85
80
75
70
65
60
55
50
11 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB
11 ACPR
11 Alt ACPR
80
75
65
55
70
60
Demo Kit Test Configuration
Figure 12. ACPR Versus Output Power for 1Carrier WCDMA
Figure 13. ACPR Versus Output Power for 2 Carriers WCDMA
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111 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB 111 ACPR
111 Alt ACPR
75
73
71
69
67
65
63
61
59
57
55
1111 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB
1111 ACPR
1111 Alt ACPR
75
73
71
69
67
65
63
61
59
57
55
Demo Kit Test Configuration
Figure 14. ACPR Versus Output Power for 3 Carriers WCDMA
Figure 15. ACPR Versus Output Power for 4 Carriers WCDMA
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A
Ref -16.9 dBm
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 3 s
*
Att 5 dB*
1 RM
NOR
*
Center 2.14 GHz Span 25.5 MHz2.55 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz Power -12.05 dBm
Adjacent Channel
Bandwidth 3.84 MHzLower -75.95 dB
Spacing 5 MHz Upper -75.70 dB
Alternate Channel
Bandwidth 3.84 MHzLower -78.95 dB
Spacing 10 MHz Upper -79.24 dB
Demo Kit Test Configuration
Typical ACPR results are shown in Figure 16 through Figure 19 for the four cases.
Figure 16. Optimum ACPR for 1 Carrier WCDMA, -7-dB Pad
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Ref -21.6 dBm Att 5 dB*
*
*
*1 RM
CLRWR
A
NOR
RBW 30 kHz
VBW 300 kHz
SWT 3 s*
Center 2.14 GHz Span 30.5 MHz3.05 MHz/
EXT
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -17.55 dBm(Ref)
Ch2 -17.58 dBm
Total -14.56 dBm
Adjacent Channel
Lower -71.99 dB
Upper -72.00 dB
Alternate Channel
Lower -74.53 dB
Upper -73.88 dB
Demo Kit Test Configuration
Figure 17. Optimum ACPR for 2 Carrier WCDMA, -7-dB Pad
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A
Ref -22.6 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 3 sAtt 5 dB*
1 RM
NOR
*
Center 2.14 GHz Span 35.6 MHz3.56 MHz/
EXT
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -19.42 dBm(Ref)
Ch2 -19.49 dBm
Ch3 -19.50 dBm
Total -14.70 dBm
Adjacent Channel
Lower -69.45 dB
Upper -69.36 dB
Alternate Channel
Lower -71.60 dB
Upper -71.69 dB
Demo Kit Test Configuration
Figure 18. Optimum ACPR for 3 Carrier WCDMA, -7-dB Pad
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A
Ref -25.2 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 3 sAtt 5 dB*
1 RM
NOR
*
Center 2.14 GHz Span 40.6 MHz4.06 MHz/
EXT
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -21.75 dBm(Ref)
Ch2 -21.78 dBm
Ch3 -21.83 dBm
Ch4 -21.75 dBm
Total -15.76 dBm
Adjacent Channel
Lower -68.38 dB
Upper -68.65 dB
Alternate Channel
Lower -69.27 dB
Upper -69.26 dB
8 Basic Test Procedure
8.1 Initial Inspection
8.2 Engage Power Supplies
Basic Test Procedure
Figure 19. Optimum ACPR for 4 Carrier WCDMA, -7-dB Pad
This section outlines the basic test procedure to get the Demo Kit operational. Disconnect the cables atJ29 and J30 that connect to the pattern generator. Connect the power supply cable and the RF output tothe spectrum analyzer.
Inspect the board to determine which devices were used.
• Note the VCXO frequency (U1) that is on the board
Engage 6-V power supply
• Verify the current reading is between 0.8 A to 1.3 A when configured with the DAC5687, if applicable.When using the wall adapter, this may be difficult. In this case, just note that the D12 and D13 are on.
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8.3 Program the CDCM7005
8.4 Program the TRF3761
8.5 DAC5687 Program
8.6 Carrier Suppression
Basic Test Procedure
Use the Default Settings on the CDCM7005 GUI (See Section 5.1). This generates a 491.52-MHz clock.
• Hit the GUI Send button• Verify that LEDs D12, D13, and D14 are illuminated
Use the Default Settings in the TRF3761 GUI (See Section 5.2). This places a carrier at 2.14 GHz
• Hit the GUI send button.• Verify the LED D15 is illuminated. This indicates that a locked LO is present.• Monitor RF output from the spectrum analyzer• Verify a single frequency tone at the default 2.14 GHz.
There may be side tones created by the default complex output of the DAC5687.
Table 6. Frequency Designations
VCO BAND UMTS GSM900 PCS DCS1800
Midband (MHz) 2140 950 1960 1850
Low (MHz) 2110 935 1930 1805
High (MHz) 2170 960 1990 1880
• The DAC PLL mode is disabled as per the default jumper settings on J31. See section 6.• Verify DACA and DACB Coarse Gain is set to 15• Ensure DAC Offsets and DAC fine gain for both A and B are set to 0• Set the spectrum analyzer as follows:
– Center Freq: 2.14 GHz– RBW: 30 kHz, VBW: 300 kHz– Span: 491.52 MHz– Attn: 5 dB– Ref Level: 10 dBm
The carrier suppression can be tuned for better performance by adjusting the dc-offset controls on theDAC5687. The default DAC GUI is shown below with the NCO mixer turned on to output a 61.44-MHztone. The output spectrum is illustrated in Figure 21.
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Basic Test Procedure
Figure 20. Default DAC GUI With fDAC/8 Tone From NCO
Figure 21. Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments
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8.7 Sideband Rejection
Basic Test Procedure
An iterative process is used to achieve the best performance.
• Place a normal marker at the peak upper sideband, place a delta marker at the carrier signal, and notethe initial delta value.
• Set initial DACA offset to 0 and DACB offset to 0.• Change DACA offset by 1000 steps and monitor the output performance change.• If performance gets better, then repeat the process with an additional 1000 steps. If the performance
gets worse or doesn't change, then change the offset in the other direction by 1000 steps.• Once the best performance remains basically unchanged, repeat the process on DACB offset with
1000 step changes.• Once optimized, go back to the A side and repeat the tuning process with a step size of 100.• Continue tuning. After each complete cycle, reduce the step size down (i.e., to 10, then to 1 if desired).• A performance greater that 70 dBc should be achievable.
Sideband rejection is determined by the two quadrature signals to the modulator being exactly 180degrees out of phase and exactly the same amplitude. Amplitude and phase imbalance between the twopaths yield an unwanted lower sideband. The amplitude variation between the two paths can becompensated for by adjusting the DAC fine gain controls or by adjusting the QMC gain controls if thedevice is operating with the QMC on. The phase can be compensated by using the QMC phaseadjustment. Note this is only possible when the coarse mixer is not used in the fDAC/4 mode. Coarsemixing in the fDAC/4 mode causes the relative phase information between I and Q paths to be mixed. In thefDAC/2 mode there are no cross terms (terms are 0) and the relative phase information is maintainedbetween I and Q paths.
• Place marker delta on the lower sideband• Turn on the QMC. Set the Gain of the QMC to 1024 for gain of 0 dB for I and Q paths. Other initial
settings may be needed depending on the state of the NCO gain and signal amplitude.• Change the phase of the QMC by small increments until the sideband is minimized.• Change the QMC A or B gains in increments of 1 until the sideband is minimized.• The overall performance should be greater than 60 dBc from the other sideband with amplitude and
phase corrections.• Re-optimized the dc-offset values as required to maintain carrier suppression performance as
specified.
Figure 22. DAC GUI With Typical Settings To Minimize LO and Sideband
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9 Optional Configurations
9.1 External LO
Optional Configurations
Sideband and LO are reduced significantly. Other spurs can be easily filtered out using an RF filter.
Figure 23. Sideband and LO Compensated Using QMC Settings
To configure the board for external LO implement the following modifications:
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Optional Configurations
• Remove C154, C155; disconnect the TRF3761 from LO path• Install C390, C391, R114 to connect the external LO to modulator, external LO J39• Disable the TRF3761 output by setting J31-23, 24 PD_OUTBUF, J31-25, 26 CHIP_EN
Figure 24. Board Modifications for External LO
Figure 25. Jumper Settings to Disable TRF3761
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9.2 External Reference
10 Filter Specifications
10.1 Baseband Filter
Filter Specifications
To configure the board for external reference, implement the following modifications:
• Change JP1-2,3 and JP2-2,3. Connect external VXCO to J4.
Figure 26. Jumper Changes for External VCXO
The TSW3003 Demo Kit layout provides the opportunity to place components to realize up to a 5th orderLC filter. The Demo Kit is by default populated with a resistive network to provide some attenuation and atwo-inductor network to compensate for the droop caused by the parasitic board capacitance. Thisprovides about 0.5 dB of ripple up to ±200 MHz of bandwidth, followed by a slow, low-pass rolloff.
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10.1.1 RF Filter/Output Match
11 Bill of Materials and Schematics
11.1 Bill of Materials
Bill of Materials and Schematics
The TSW3003 Demo Kit layout also provides the opportunity to place a small 3rd order LC filter on theoutput of the modulator for either filtering or impedance matching purposes. This filter has been disabledby removing the shunt elements.
This section contains the bill of materials and schematics for the TSW3003 Demo Kit.
Table 7 lists the parts used in constructing the TSW3003 Demo Kit.
Table 7. Bill of MaterialsQty Ref Des Value PCB Footprint MFR Name MFR Part Number Note
8 C1 C18 C21 C26 C34 47μF tant_b Kemet T494B476M010ASC39 C41 C46
62 C3 C20 C28 C36 C38 0.1μF 0402 Panasonic ECJ-0EB1C104KC43 C48-C54 C56-C66C70-C72 C74 C75 C78C85-C94 C97-C100C103 C106 C111 C112C115 C118 C120 C121C123 C124 C144 C145C162 C165 C344-C347
2 C4 C109 1μF 0603 Panasonic ECJ-1V41E105M
6 C5 C77 C80-C82 C96 0.01μF 0402 Panasonic ECJ-0EB1E103K
12 C19 C24 C25 C27 C35 10μF 1206 Panasonic ECJ-3YB1C106KC37 C40 C42 C44 C45C47 C348
13 C55 C67-C69 C76 C79 10μF tant_a Kermet T494A106M016ASC83 C84 C101 C116C122 C148 C150
6 C95 C104 C117 C127 0.001μF 0402 Panasonic ECJ-0EB1E102KC163 C164
1 C102 560pF 0402 Panasonic ECJ-0EB1H561K
1 C108 0.47μF 0603 Murata GRM188R71C474KA88D
1 C110 22μF tant_a Kemet T494A226M010AS
2 C119 C343 100pF 0402 Panasonic ECJ.-0EB1E101K
1 C126 680pF 0603 Murata GRM1885C2A681JA01D
1 C128 330pF 0603 Murata GRM1885C2A331JA01D
1 C136 0.033μF 0402 AVX 0402ZC333KAT2A
1 C137 330pF 0402 Panasonic ECJ-0EB1E331K
1 C138 10,000pF 0603 Murata GRM188R71H103KA01D
7 C147 C149 C151 C154 10pF 0402 Murata GRM1555C1H100JZ01DC155 C377 C387
2 C152 C153 22pF 0402 Panasonic ECJ-0EC1H220J
0 C156-C158 C171 2.2pF 0603 AVX 06035A2R2CAT2A_DNI DNI
3 C160 C161 C169 4.7μF tant_a AVX TAJA475K020R
0 C167 C168 DNI 0402 Panasonic ECJ-0EB1E103K_DNI DNI
0 C224-C226 C340 4.7pF 0603 Panasonic ECJ-1VC1H047C_DNI DNI
2 C381 C386 3.3pF 0402 Murata GRM1555C1H3R3CZ01D
2 C383 C384 47pF 0603 Panasonic ECJ-1VC1H470J
1 C385 10nF 0603 Panasonic ECJ-1VB1C103K
0 C390 C391 22pF 0402 Panasonic ECJ-0EC1H220J_DNI DNI
5 D12-D16 LED green LED_0805 Panasonic LNJ306G5UUX
16 FB1-FB16 68Ω at 100MHz 1206 Panasonic EXC-ML32A680U
1 J1 CONN JACK PWR CON_RAPC722_JACK_THVT_3 Switchcraft RAPC722
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Bill of Materials and Schematics
Table 7. Bill of Materials (continued)Qty Ref Des Value PCB Footprint MFR Name MFR Part Number Note
8 J4 J7-J9 J27 J32 J35 SMA_END_RND SMA_SMEL_218x247 Johnson 142-0761-821J39 Components
2 J29 J30 TSM-117-01-S-DV- SAMTEC_TSM_117_01_S_DV_L SAMTEC TSM-117-01-S-DV-LCLC C
1 J31 HTSW-120-07-L-T HDR_THVT_3x12_100_M SAMTEC HMTSW-120-07-G-T
1 J34 USB_B_S_F_B_T CON_THRT_USB_B_F SAMTEC USB-B-S-F-B-THH
1 J37 BANANA_JACK_R JACK_THVT_BANANA_250dia Alectron ST-351A REDED Connectors
1 J38 BANANA_JACK_B JACK_THVT_BANANA_250dia Alectron ST-351B BLKLK Connectors
4 JP1 JP2 JP6 JP8 Jumper_1x3_100_ HDR_THVT_1x3_100_M SAMTEC HMTSW-103-07-G-S-.230430L
10 L19 L21 L22 L25 R179 0 0603 Panasonic ERJ-3GEY0R00VR230 R235-R237 R262
4 L20 L23 L24 L26 33nH 0603 Coilcraft 0603CS-33NX_L
2 L27 L28 8.2nH 0402 Coilcraft or 0402CS-3N3XJL orJohanson L-07C3N3SV6S
3 R13 R18 R21 100K 0603 Panasonic ERJ-3EKF1003V
3 R23 R24 R105 1K 0402 Panasonic ERJ-2RKF1001X
0 R25 R37 R97 R98 130 0402 Panasonic ERJ-2RKF1300X_DNI DNI
14 R26 R31 R45 R46 R67 22.1 0402 Panasonic ERJ-2RKF22R1XR68 R71 R72 R75 R76R90 R91 R101 R108
1 R27 15.8K 0603 Panasonic ERJ-3EKF1582V
1 R28 30.1K 0603 Panasonic ERJ-6ENF3012V
1 R29 10 0402 Panasonic ERJ-2RKF10R0X
11 R32 R33 R82 R86 R88 100 0402 Panasonic ERJ-2RKF1000XR89 R92 R93 R96 R99R125
3 R34-R36 750 0402 Panasonic ERJ-2RKF7500X
8 R39-R44 R47 R49 130 0402 Panasonic ERJ-2RKF1300X
3 R48 R52 R83 150 0402 Panasonic ERJ-2RKF1500X
3 R50 R63 R69 0 0402 Panasonic ERJ-2GE0R00X
8 R53-R56 R58 R59 R70 82.5 0402 Panasonic ERJ-2RKF82R5XR78
8 R61 R65 R77 R79 R81 10K 0402 Panasonic ERJ-2RKF1002XR84 R94 R95
0 R64 1K 0402 Panasonic ERJ-2RKF1001X_DNI DNI
0 R66 22.1 0402 Panasonic ERJ-2GE0R00X_DNI DNI
1 R73 162 0402 Panasonic ERJ-2RKF1620X
3 R74 R106 R107 4.75K 0402 Panasonic ERJ-2RKF4751X
2 R102 R109 300 0603 Panasonic ERJ-3EKF3000V
0 R103 100 0402 Panasonic ERJ-2RKF1000X_DNI DNI
1 R104 7.5k 0603 ROHM MCR03EZPFX7501
1 R110 649 0603 Yageo RC0603FR-07649RL
0 R114 49.9 0402 Panasonic ERJ-2RKF49R9X_DNI DNI
4 R118 R119 R133 R134 634 0603 Yageo RC0603FR-07634RL
4 R120 R171 R180 R184 60.4 0603 Yageo RC0603FR-0760R4L
4 R172 R177 R280 R281 115 0603 Yageo RC0603FR-07115RL
1 R261 93.1 0402 Panasonic ERJ-2RKF93R1X
0 R284 110 0603 Panasonic ERJ-3EKF1100V_DNI DNI
0 R285 221 0603 Panasonic ERJ-3EKF2210V_DNI DNI
1 R287 23.2K 0603 Panasonic ERJ-3EKF2322V
1 R288 6.34K 0603 Panasonic ERJ-3EKF6341V
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11.2 Schematics
Bill of Materials and Schematics
Table 7. Bill of Materials (continued)Qty Ref Des Value PCB Footprint MFR Name MFR Part Number Note
2 R289 R290 90.9 0603 Panasonic ERJ-3EKF90R9V
4 RN1-RN4 4816P-001-220 RNET_16_225x445_50 Bourns 4816P-001-220
1 SJP3 Jumper_1x3_SMT SJP3_JUMPER
1 SW2 SW RESET switch_reset C&K KT11P3JM
2 TP1 TP4 Testloop_Red TP_THVT_060_RND Keystone 5000Electronics Corp
1 U1 2115-491.52MHZ VCXO_6 Toyocom TCO-2111-491.52
1 U6 TPS76733QPWP HTSSOP_20_260x177_26_pwrpa Texas TPS76733QPWPd Instruments
1 U8 HTSSOP_20_260x177_26_pwrpa Texas TPS76701QPWPTPS76701QPWP d Instruments
1 U9 HTSSOP_20_260x177_26_pwrpa Texas TPS76750QPWPTPS76701QPWP d Instruments
1 U10 HTQFP100 Texas DAC5687DAC5687 Instruments
1 U12 CDCM7005 QFN48 Texas CDCM7005RGZTInstruments
1 U16 OSC-VECTRON OSC_4_SM_460x386 VECTRON VTD3-J0BC-10M000
1 U17 TRF3761 PQFP_40_242x242_0p5mm Texas TRF3761Instruments
1 U18 TRF3703-33 QFN24 Texas TRF3703Instruments
1 U47 SN74AHC541PW tssop_20_260x177_26 Texas SN74AHC541PWInstruments
1 U48 SN74HC241PW tssop_20_260x177_26 Texas SN74HC241PWInstruments
3 U49 U51 U52 SN74LVC1G125D SOT_5_120x69_57 Texas SN74LVC1G125DBVRBVR Instruments
1 U50 FT245RL ssop_28_413x220_26 FTDI Chip FT245RL
0 U53 OSC-VECTRON XTAL_4_SM_203x132 Vectron VTC4_DNI DNIInternational
4 SCREW1-SCREW4 SCREW PANHEAD 4-40 x 3/8 Building PMS 440 0038 PHFasteners
4 STANDOFF1- STANDOFF ALUM Keystone 2203STANDOFF4 HEX 4-40 × 0.500
The schematic for the TSW3003 Demo Kit appears on the following page.
32 TSW3003 Demonstration Kit SLWU029D–October 2006–Revised August 2007Submit Documentation Feedback
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DB15DB14DB13
DB12DB11DB10DB9DB8
DB7DB6DB5
DA15DA14DA13
DA12DA11DA10DA9DA8
DA7DA6DA5
DA4DA3DA2DA1DA0
DB4DB3DB2DB1DB0
+3.3VA
+1.8VD
+3.3VA +3.3VA
+1.8VD +3.3VA
+3.3VCLK
IOVDD IOVDD
IOVDD
IOVDD
+1.8VD
+3.3VA
+3.3VA
+3.3VA
+1.8VD
DB[0..15] SH2
IOUTA2 SH3IOUTA1 SH3
IOUTB1 SH3IOUTB2 SH3
DA[0..15]SH2
CLK2CB SH4CLK2B SH4
CLK1CB SH4CLK1B SH4
/RESET SH2,4
TX_ENABLESH2
PLL_VDD SH2
/PLLCK_ENSH2
PHSTR SH2
EXT_LOSH2
SLEEP SH2
QFLAG SH2SDENBSH5SCLKSH5SDIOSH5
Title
Size Document Number Rev
Date: Sheet of
DAC D
TSW3003_EVMB
1 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
DAC D
TSW3003_EVMB
1 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
DAC D
TSW3003_EVMB
1 7Wednesday, March 07, 2007
NOTE: DNI = DO NOT INSTALL
P. LARSON
Engineer:
Drawn By:
J. SETON
FILE:
JP8 - JUMPER PINS 1 & 2
C66.1uFC66.1uF
R98130DNI
R98130DNI
C53.1uFC53.1uF
+ C7610uF10V
+ C7610uF10V
C71.1uFC71.1uF
C51.1uFC51.1uF
JP8DEFAULT +3.3VA
JP8DEFAULT +3.3VA
1
32
C82 .01uFC82 .01uF+ C6710uF10V
+ C6710uF10V
R31
22.1
R31
22.1
C78.1uFC78.1uF
R25130DNI
R25130DNI
C62.1uFC62.1uF
R29
10
R29
10
R33100R33100
R284110DNI
R284110DNI
C70.1uFC70.1uF
C136 .033uFC136 .033uF
C61.1uFC61.1uF
R2622.1R2622.1
+ C7910uF10V
+ C7910uF10V
+ C5510uF10V
+ C5510uF10V C77 .01uFC77 .01uF
M SA
D EN
J27PLL_LOCK
M SA
D EN
J27PLL_LOCK
1
5234
C56.1uFC56.1uF
C58.1uFC58.1uF
C59.1uFC59.1uF
U10DAC5687
U10DAC5687
DA
253
DA
352
DA
451
DGND45
DA550 DA649 DA748
AV
DD
3
IOGND47
DB
172
DB
0(LS
B)
71
DGND38
DGND 81IODVDD 80
AG
ND
17A
VD
D18
AV
DD
23A
VD
D24
DA1041
AG
ND
25
DVDD26 IOU
TB2
6
DGND27SDENB28SCLK29
PLL
LOC
K70
DA1435
RESETB 95SLEEP 96
DGND 88
IOVDD46
IOU
TB1
5
AG
ND
9A
VD
D8
PLL
VD
D67
DA1239
DA1336DVDD37
DA15(MSB)34
AG
ND
4
LPF
66P
LLG
ND
65
CLK
262
CLK
VD
D61
CLK
1C60
DG
ND
69
DB
273
AV
DD
10EX
TIO
11
DB11 86
AV
DD
14E
XTL
O15
DB13 90
AV
DD
16
TXENABLE33
SDIO30
CLK
159
CLK
GN
D58
DB
374
DB
475
DB5 76DB6 77DB7 78IOGND 79
DVDD 82DB8 83DB9 84DB10 85
CLK
2C63
CLK
GN
D64
DV
DD
68
DA
154
DA
0(LS
B)
55D
VD
D56
DG
ND
57
SDO31DVDD32
DA1140
DA942DA843DVDD44
AG
ND
12B
IAS
J13
AG
ND
7
AG
ND
1A
VD
D2
AG
ND
19IO
UTA
220
IOU
TA1
21A
GN
D22
DB12 87
DVDD 89
DB14 91DB15(MSB) 92DGND 93PHSTR 94
TESTMODE 97QFLAG 98DGND 99DVDD 100
+ C11610uF10V
+ C11610uF10V
R241KR241K
C60.1uFC60.1uF
C72.1uFC72.1uF
C80 .01uFC80 .01uF
R2370
R2370
R261
93.1
R261
93.1
C115.1uFC115.1uF
C137 330pFC137 330pF
C52.1uFC52.1uF
C50.1uFC50.1uF
U49
SN74LVC1G125DBVR
U49
SN74LVC1G125DBVR
OE1
A2Y 4
GND3
VCC 5
R32100R32100
+ C6910uF10V
+ C6910uF10V
R97130DNI
R97130DNI
SW2
SW RESET
RESETSW2
SW RESET
RESET12
34
C63.1uFC63.1uF
C74.1uFC74.1uF
C49.1uFC49.1uF
R23
1K
R23
1K
C64.1uFC64.1uF
C81 .01uFC81 .01uF
C65.1uFC65.1uF
C75.1uFC75.1uF
C54.1uFC54.1uF
R285221DNI
R285221DNI
+ C6810uF10V
+ C6810uF10V
R37130DNI
R37130DNI
C57.1uFC57.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DA14DA13DA12DA11DA10DA9DA8
DA7DA6DA5DA4DA3DA2DA1DA0
DA15
DB0
DB15DB14DB13DB12DB11DB10DB9DB8
DB7DB6DB5DB4DB3DB2DB1
DA_7DA_6DA_5DA_4DA_3DA_2DA_1DA_0
DB_0DB_1DB_2DB_3DB_4DB_5DB_6
DB_9DB_10DB_11DB_12DB_13DB_14DB_15
DA_15DA_14DA_13DA_12DA_11DA_10DA_9DA_8
DB_7
DB_8
+3.3VA
DB[0..15] SH1
DA[0..15] SH1PHSTR SH1
/RESET SH1,4
/CDC_PD SH4
TX_ENABLE SH1EXT_LO SH1SLEEP SH1PLL_VDD SH1
QFLAG SH1
PD_OUTBUF SH7CHIP_EN SH7
/PLLCK_EN SH1
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL D
TSW3003_EVMB
2 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL D
TSW3003_EVMB
2 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
INTERFACE CONTROL D
TSW3003_EVMB
2 7Wednesday, March 07, 2007
J31 - JUMPER PINS 1 & 2
JUMPER PINS 7 & 8 JUMPER PINS 11 & 12
JUMPER PINS 22 & 23 JUMPER PINS 26 & 27 JUMPER PINS 31 & 32
JUMPER PINS 20 & 21
JUMPER PINS 4 & 5
R108
22.1
R108
22.1 RN44816P-001-220
RN44816P-001-220
12345678 9
10111213141516
RN34816P-001-220
RN34816P-001-220
12345678 9
10111213141516
RN24816P-001-220
RN24816P-001-220
123456789
10111213141516
RN14816P-001-220
RN14816P-001-220
123456789
10111213141516
J29TSM-117-01-S-DV-LC
J29TSM-117-01-S-DV-LC
13
24
5678910111213141516171819202122232425262728293031323334
J30TSM-117-01-S-DV-LC
J30TSM-117-01-S-DV-LC
13
24
5678910111213141516171819202122232425262728293031323334
R101
22.1
R101
22.1
J31
HTSW-120-07-L-T
J31
HTSW-120-07-L-T
1
2
4 6
8
10 12
14
16 18
20
3
5
7 9
11
13 15
17
19 2122
23
2425
26
2728
29
3031
32
3334
35
36
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+5VA
+5VA
+5VA
+5VA
IOUTA2SH1
IOUTA1SH1
IOUTB2SH1
IOUTB1SH1
LONSH7LOPSH7
Title
Size Document Number Rev
Date: Sheet of
MODULATOR D
TSW3003_EVMB
3 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
MODULATOR D
TSW3003_EVMB
3 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
MODULATOR D
TSW3003_EVMB
3 7Wednesday, March 07, 2007
NOTE: DNI = DO NOT INSTALL
L2033nHL2033nH
12
R120
60.4
R120
60.4
C3813.3pFC3813.3pF
R29090.9R29090.9
R171
60.4
R171
60.4
C167DNIC167DNI
C2244.7pFDNI
C2244.7pFDNI
C168DNIC168DNI
C1562.2pFDNI
C1562.2pFDNI
+ C1614.7uF20V
+ C1614.7uF20V
R281115R281115
C1572.2pFDNI
C1572.2pFDNI
C3863.3pFC3863.3pF
R2350R2350
R184
60.4
R184
60.4
R133634
R133634
68 ohm @ 100MHz
FB5
68 ohm @ 100MHz
FB5
C3404.7pFDNI
C3404.7pFDNI
R118634
R118634
R134634R134634
R1790R1790
L2633nHL2633nH
12
R2360
R2360
C2254.7pFDNI
C2254.7pFDNIR119
634R119634
R180
60.4
R180
60.4
R172115
R172115
C162.1uFC162.1uF
C343
100pF
C343
100pF
L22
0
L22
01 2
R177115R177115
68 ohm @ 100MHz
FB4
68 ohm @ 100MHz
FB4
C1631000pFC1631000pF
L25
0
L25
01 2
R280115R280115
C1582.2pFDNI
C1582.2pFDNI
U18TRF3703-33
U18TRF3703-33
NC11GND2LOP3LON4GND5NC26
NC
37
GN
D8
QN
9Q
P10
GN
D11
GN
D12
VCCI 18GND 17
RFOUT 16NC5 15GND 14NC4 13
GN
D19
GN
D20
IP21
IN22
GN
D23
VC
C2
24
R28990.9R28990.9
L21
0
L21
01 2
+ C1604.7uF20V
+ C1604.7uF20V
C1712.2pFDNI
C1712.2pFDNI
L2333nHL2333nH
12
R2300
R2300
M SA
D EN
J32REFOUT
M SA
D EN
J32REFOUT
1
5234
C165.1uFC165.1uF
C2264.7pFDNI
C2264.7pFDNI
L19
0
L19
01 2
L2433nHL2433nH
12
C1641000pFC1641000pF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V_CTRL
V_CTRL
+3.3VCLK
+3.3VCLK AVCC
+3.3VCLK
+3.3VCLK
+3.3VCLK
+3.3VCLK+3.3VCLK
+3.3VCLK
AVCC
+3.3VCLK +3.3VCLK
CTRL_DATA SH5
REF_OSCSH7
CTRL_LE SH5
CTRL_CLK SH5
CLK2CB SH1CLK2B SH1
CLK1B SH1CLK1CB SH1
/RESET SH1,2
/CDC_PD SH2
Title
Size Document Number Rev
Date: Sheet of
CDC D
TSW3003_EVMB
4 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
CDC D
TSW3003_EVMB
4 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
CDC D
TSW3003_EVMB
4 7Wednesday, March 07, 2007
DNI = DO NOT INSTALLJP1 - JUMPER PINS 1 & 2JP2 - JUMPER PINS 1 & 2VCO_EN OPTION NOT AVAILABLE ON U1.
NOTES:
C1091uF20%25V
C1091uF20%25V
D13 LED greenREFD13 LED greenREF
C89.1uFC89
.1uFC92
.1uFC92
.1uF
R744.75KR744.75K
R50
0
R50
0
C103.1uF10%16V
C103.1uF10%16V
C91.1uFC91
.1uF
+ C11022uF20%10V
+ C11022uF20%10V
12
JP1VCXOB
JP1VCXOB1
32
R66
22.1
R66
22.1
R63
0
R63
0
R42130R42130
C102560pF10%50V
C102560pF10%50V R39
130R39130
C90.1uFC90
.1uF
C1041000pF
10%25V
C1041000pF
10%25V
R5982.5R5982.5
R52
150
R52
150R5882.5R5882.5
R47130R47130
R48
150
R48
150
R41130R41130
R7882.5R7882.5
M SA
D EN
J9OUTCLK1
M SA
D EN
J9OUTCLK1
1
5234
C100
.1uF
C100
.1uF
68 ohm @ 100MHz
FB1
68 ohm @ 100MHz
FB1
+C10110uF10V
+C10110uF10V
R40130R40130
JP2VCXO
JP2VCXO
1
32
U1
2111-491.52MHZ
U1
2111-491.52MHZ
V_CTRL1NC2GND3 OUT 4OUTB 5VCC 6
R5682.5R5682.5
R5382.5R5382.5
C94.1uFC94
.1uFC97.1uFC97.1uF
M SA
D EN
J8OUTCLK3
M SA
D EN
J8OUTCLK3
1
5234
C93.1uFC93
.1uF
D14 LED greenLOCK
D14 LED greenLOCK
C98.1uFC98.1uF
C99.1uFC99.1uF
D12 LED greenVCXO
D12 LED greenVCXO
R5582.5R5582.5
C95.001uFC95
.001uF
JP3JP312
C106 .1uF
10%16V
C106 .1uF
10%16V
R44130R44130
R73
162
R73
162
C96.01uFC96
.01uF+C83
10uF10V
+C8310uF10V
MS A
DE N
J4EXT_VCXO
MS A
DE N
J4EXT_VCXO
1
5234
C88.1uFC88
.1uF
R5482.5R5482.5
R6110KR6110K
R83150R83150
R7082.5R7082.5
R43130R43130
R6510KR6510K
C87.1uFC87
.1uF
R35 750R35 750
R641KDNI
R641KDNI
C86.1uFC86
.1uF
R34 750R34 750
+ C8410uF10V
+ C8410uF10V
R69
0
R69
0
C112
.1uF
C112
.1uF
C85.1uFC85
.1uF
R36 750R36 750
R49130R49130
C111
.1uF
C111
.1uF
M SA
D EN
J7OUTCLK2
M SA
D EN
J7OUTCLK2
1
5234
U12
CDCM7005
U12
CDCM7005
VCC 13
Y2B 8Y2A 7VCC 6VCC 5
VCC_CP33
AVCC32
NC34
Y3B 12Y3A 11VCC 10VCC 9
VCC 19
REF_SEL35
AVCC39AVCC38
SEC_REF37PRI_REF36
VCXO_IN43VCXO_INB42VCC41VBB40
/RESET or /HOLD 14VCC 15Y4A 16Y4B 17VCC 18
/PD 1VCC 2Y1A 3Y1B 4
VCC 20VCC 21
STATUS_VCXO or I_REF_CP 22STATUS_REF or PRI_SEC_CLK 23
GND 24
PLL_LOCK 25CTRL_DATA 26
AVCC27
CTRL_CLK28 CTRL_LE29
AVCC30 CP_OUT31
VCC44 VCC45 Y0A46 Y0B47 VCC48
C108.47uF10%16V
C108.47uF10%16V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3VA
+3.3VA +3.3VA
+3.3VA
+3.3VA +3.3VA
CTRL_CLK SH4
CTRL_DATA SH4
CTRL_LE SH4
SCLK SH1
SDIO SH1
PLL_CLK SH7
PLL_DATA SH7
PLL_LE SH7SDENB SH1
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE D
TSW3003_EVMB
5 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE D
TSW3003_EVMB
5 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
USB INTERFACE D
TSW3003_EVMB
5 7Wednesday, March 07, 2007
CLK
DATA
CTRL_LE
PLL_LE
OE
SDEN
SDIO
R88 100R88 100
U48
SN74HC241PW
U48
SN74HC241PW2Y4 3
1A121A241A361A482A1112A2132A3152A417GND10 2Y3 52Y2 72Y1 91Y4 121Y3 141Y2 161Y1 182OE 191OE1 VCC 20
R86 100R86 100
R125 100R125 100
R8410KR8410K
R68 22.1R68 22.1
R92 100R92 100
R67 22.1R67 22.1
R8110KR8110K
R75 22.1R75 22.1
C344.1uFC344.1uF
R82 100R82 100
R72 22.1R72 22.1
U50
FT245RL
U50
FT245RL
USBDM16
USBDP15
VCCIO4
NC18
RESET19
NC224
OSCI27
OSCO28
3V3OUT17
AGND25GND7GND18GND21TEST26 PWREN 12
WR 14
D1 5
D7 6
D5 9
D6 10
TXE 22
D4 2
D3 11
RXF 23
D0 1
RD 13
VCC20
D2 3
68 OHM @ 100MHz
FB6
68 OHM @ 100MHz
FB6
R90 22.1R90 22.1
J34
USB_B_S_F_B_TH
USB_CONNJ34
USB_B_S_F_B_TH
USB_CONN
VCC 1-DATA 2+DATA 3
GND 4
GND15
GND26
R7910KR7910K
R7710KR7710K
C38447pFC38447pF
R71 22.1R71 22.1
C38510nFC38510nF
U47
SN74AHC541PW
U47
SN74AHC541PWY8 11
A12A23A34A45A56A67A78A89GND10 Y7 12Y6 13Y5 14Y4 15Y3 16Y2 17Y1 18OE2 19OE11 VCC 20
R89 100R89 100
C347.1uFC347.1uF
C346.1uFC346.1uF
R76 22.1R76 22.1
+ C1694.7uF20V
+ C1694.7uF20V
C38347pFC38347pF
R99 100R99 100
C345.1uFC345.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+6V_IN
+6V
+6V
+3.3VA
+3.3VCLK
+6V
+5V_PLL
+6V
+5VA
+3.3V_PLL
+1.8VD
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION D
TSW3003_EVMB
6 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION D
TSW3003_EVMB
6 7Wednesday, March 07, 2007
Title
Size Document Number Rev
Date: Sheet of
POWER DISTRIBUTION D
TSW3003_EVMB
6 7Wednesday, March 07, 2007
68 OHM @ 100MHz
FB14
68 OHM @ 100MHz
FB14
68 OHM @ 100MHz
FB11
68 OHM @ 100MHz
FB11
SJP31.8/2.1
(1-2)
SJP31.8/2.1
(1-2)
1
32
C38.1uF10%16V
C38.1uF10%16V
12
+C3447uF10V20%
+C3447uF10V20%
C2710uF10%16V
C2710uF10%16V
12
+C2147uF
10V20%
+C2147uF
10V20%D16
LED green
+6VD16
LED green
+6V
C41uF20%25V
C41uF20%25V
+C4647uF10V20%
+C4647uF10V20%
68 OHM @ 100MHz
FB10
68 OHM @ 100MHz
FB10
R2830.1K
R2830.1K
C4710uF10%16V
C4710uF10%16V
12
U6
TPS76733QPWP
U6
TPS76733QPWP
GND/HTSNK22
NC3 17
GND3NC14EN5IN16
NC28
GND/HTSNK5 11
GND/HTSNK11
GND/HTSNK39OUT1 13GND/HTSNK410
IN27 RESET 16
GND/HTSNK6 12
OUT2 14FB/NC 15
NC4 18GND/HTSNK7 19GND/HTSNK8 20
PWRPAD 21
C2410uF10%16V
C2410uF10%16V
12
+C4510uF
16V10%
LOW ESR+
C4510uF
16V10%
LOW ESR
+C4147uF10V20%
+C4147uF10V20%
+C3710uF
16V10%
LOW ESR+
C3710uF
16V10%
LOW ESR
C4210uF10%16V
C4210uF10%16V
12
C43.1uF10%16V
C43.1uF10%16V
12
C1910uF
10%16V
C1910uF
10%16V
12
C36.1uF10%16V
C36.1uF10%16V
12
R21 100KR21 100K
C5.01uFC5
.01uF
R109300
R109300
C3510uF10%16V
C3510uF10%16V
12
+C1847uF
10V20%
+C1847uF
10V20%
R18 100KR18 100K
C34810uF10%16V
C34810uF10%16V
12R27
15.8KR2715.8K
C28.1uF10%16V
C28.1uF10%16V
12
U9
TPS76750QPWP
U9
TPS76750QPWP
GND/HTSNK22
NC3 17
GND3NC14EN5IN16
NC28
GND/HTSNK5 11
GND/HTSNK11
GND/HTSNK39OUT1 13GND/HTSNK410
IN27 RESET 16
GND/HTSNK6 12
OUT2 14FB/NC 15
NC4 18GND/HTSNK7 19GND/HTSNK8 20
PWRPAD 21
C48.1uF10%16V
C48.1uF10%16V
12
+C147uF
10V20%
+C147uF
10V20%
C20.1uF10%16V
C20.1uF10%16V
12
C3.1uF10%16V
C3.1uF10%16V
12
+C3947uF10V20%
+C3947uF10V20%
R13 100KR13 100K
C4410uF10%16V
C4410uF10%16V
12
J1
CONN JACK PWR
J1
CONN JACK PWR321
+C2647uF10V20%
+C2647uF10V20%
R28723.2KR28723.2K
68 OHM @ 100MHz
FB16
68 OHM @ 100MHz
FB16
68 OHM @ 100MHz
FB13
68 OHM @ 100MHz
FB13
J37
BANANA_JACK_RED+6V_IN
J37
BANANA_JACK_RED+6V_IN
+ C4010uF
16V10%
LOW ESR+ C40
10uF
16V10%
LOW ESR
U8
TPS76701QPWP
U8
TPS76701QPWP
GND/HTSNK22
NC3 17
GND3NC14EN5IN16
NC28
GND/HTSNK5 11
GND/HTSNK11
GND/HTSNK39OUT1 13GND/HTSNK410
IN27 RESET 16
GND/HTSNK6 12
OUT2 14FB/NC 15
NC4 18GND/HTSNK7 19GND/HTSNK8 20
PWRPAD 21
+C2510uF
16V10%
LOW ESR+
C2510uF
16V10%
LOW ESR
68 OHM @ 100MHz
FB15
68 OHM @ 100MHz
FB15
68 OHM @ 100MHz
FB12
68 OHM @ 100MHz
FB12
J38
BANANA_JACK_BLKGND
J38
BANANA_JACK_BLKGND
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCO_OUTP
VCO_OUTM
+3.3V_PLL
+5V_PLL
+5VA
+3.3V_PLL+3.3V_PLL
+3.3V_PLL
+5V_PLL
+5V_PLL
LOPSH3
LONSH3
REF_OSC SH4
REF_IN
REF_IN
PLL_CLKSH5PLL_DATASH5PLL_LESH5
PD_OUTBUFSH2CHIP_ENSH2
Title
Size Document Number Rev
Date: Sheet of
VCO D
TSW3003_EVMB
7 7Wednesday, May 09, 2007
Title
Size Document Number Rev
Date: Sheet of
VCO D
TSW3003_EVMB
7 7Wednesday, May 09, 2007
Title
Size Document Number Rev
Date: Sheet of
VCO D
TSW3003_EVMB
7 7Wednesday, May 09, 2007
NOTE: DNI = DO NOT INSTALL
MECHANICAL PARTS
JP6 - JUMPER PINS 2 & 3
C145.1uFC145.1uF
C15110pFC15110pF
SCREW PANHEAD 4-40 x 3/8SCREW PANHEAD 4-40 x 3/8
R114
49.9DNI
R114
49.9DNI
C15510pFC15510pF
M SA
D EN
J39LO_OUT
M SA
D EN
J39LO_OUT
1
5234
68 OHM @ 100MHz
FB9
68 OHM @ 100MHz
FB9
C14710pFC14710pF
R106
4.75K
R106
4.75K
R262
0
R262
0
+ C14810uF
10V
+ C14810uF
10V
U52
SN74LVC1G125DBVR
U52
SN74LVC1G125DBVR
OE1
A2Y 4
GND3
VCC 5
STANDOFF ALUM HEX 4-40 x .500STANDOFF ALUM HEX 4-40 x .500
R45
22.1
R45
22.1
R94
10K
R94
10K
TP4LOCK_DETECT
TP4LOCK_DETECT
C390
22pFDNI
C390
22pFDNI
C15222pFC15222pF
R96100R96100
U51
SN74LVC1G125DBVR
U51
SN74LVC1G125DBVR
OE1
A2Y 4
GND3
VCC 5
SCREW PANHEAD 4-40 x 3/8SCREW PANHEAD 4-40 x 3/8
C37710pFC37710pF
R1047.5kR1047.5k
R93100R93100
C13810,000pFC13810,000pF
R46
22.1
R46
22.1
R103100DNI
R103100DNI
STANDOFF ALUM HEX 4-40 x .500STANDOFF ALUM HEX 4-40 x .500
C126680pFC126680pF
C121.1uFC121.1uF
C15410pFC15410pF
L27
8.2nH
L27
8.2nH1 2
C123.1uFC123.1uF
R95
10K
R95
10K
R107
4.75K
R107
4.75K
U16
OSC-VECTRON
U16
OSC-VECTRON
REF1GND 4VDD8 OUT 5
L28
8.2nH
L28
8.2nH1 2
C120.1uFC120.1uF
SCREW PANHEAD 4-40 x 3/8SCREW PANHEAD 4-40 x 3/8
C119100pFC119100pF R110
649
R110
649
U53
OSC-VECTRONDNI
U53
OSC-VECTRONDNI
REF1GND 2VDD4 OUT 3
R288
6.34K
R288
6.34K
U17TRF3761
U17TRF3761
PD_OUTBUF1CHIP_EN2CLOCK3DATA4STROBE5GND16GND27DVDD18AVDD_PRES9GND310
GN
D4
11G
ND
512
VCO
_OU
TP13
VCO
_OU
TM14
AV
DD
_OU
TBU
F15
GN
D6
16A
VD
D_V
CO
BU
F17
EX
T_V
CO
_IN
18R
BIA
S2
19G
ND
720
AVDD 21GND8 22AVDD_CAPARRAY 23AVDD_BUF 24AVDD_VCO 25VCTRL_IN 26GND9 27RBIAS1 28AVDD_BIAS 29GND10 30
GN
D11
31A
VD
D32
GN
D12
33C
PO
UT
34A
VD
D_C
P35
AV
DD
_RE
F36
GN
D13
37R
EF_
IN38
LOC
K_D
ETE
CT
39D
VD
D2
40
PAD41
C127
1000pF
C127
1000pF
SCREW PANHEAD 4-40 x 3/8SCREW PANHEAD 4-40 x 3/8
C128330pFC128330pF
R1051KR1051K
+ C15010uF10V
+ C15010uF10V
C118.1uFC118.1uF
D15
LED green
LOCK_DETECTD15
LED green
LOCK_DETECT
C144.1uFC144.1uF
68 OHM @ 100MHz
FB3
68 OHM @ 100MHz
FB3
JP6
REF_CLK
JP6
REF_CLK
1
32
C14910pFC14910pF
R102300
R102300
+ C12210uF10V
+ C12210uF10V
C124.1uF
C124.1uF
68 OHM @ 100MHz
FB2
68 OHM @ 100MHz
FB2
STANDOFF ALUM HEX 4-40 x .500STANDOFF ALUM HEX 4-40 x .500
C391
22pFDNI
C391
22pFDNI
68 OHM @ 100MHz
FB7
68 OHM @ 100MHz
FB7
C15322pFC15322pF
68 OHM @ 100MHz
FB8
68 OHM @ 100MHz
FB8
STANDOFF ALUM HEX 4-40 x .500STANDOFF ALUM HEX 4-40 x .500
MS A
DE N
J35EXT_REF_CLK
MS A
DE N
J35EXT_REF_CLK
1
5234
C38710pFC38710pF
C117
1000pF
C117
1000pF
TP1TP1
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