True Random Number Generator based on a Sigma-Delta …True Random Number Generator based on a Sigma-Delta Modulator Master Thesis on System-on-Chip Design – Royal Institute of Technology

True Random Number Generator based on a Sigma-Delta Modulator

Master Thesis on System-on-Chip Design – Royal Institute of Technology – Stockholm - Sweden 1 / 71

Acknowledgements First of all, I would like to express my appreciation of Dr.-Ing Jens Sauerbrey for his invitation to do a master thesis project under his supervision and for his patient guidance during my master thesis project hold at Infineon Technologies AG in Munich. I was truly very fortunate to have the opportunity to work under him as a master student. In addition to providing his expert guidance in circuit design issues for Sigma-Delta modulators, he also provided help in technical writing style and presentation style, and I found this guidance to be extremely valuable from which I learned many practical issues concerning real analog circuit design. I enjoyed also his tips for hiking trips through the Alps and explanations of the funny embarrassing bureaucracy organization in Germany. I would also like to express my appreciation to Dr.-Ing. Roland Thewes who made it possible to have my master thesis project done at the Corporate Research group at Infineon Technologies AG in Munich. I think that the atmosphere in this research group was very good. When I started working in this group, I immediately noticed and valued the high level of communication and the free flow of ideas. I also found the environment to be very comfortable to work in, and people were very accepting and helpful. I feel very fortunate to have had the opportunity to work with the other workmates in this group. I appreciate Birgit Holzapfl for her guidance on CADENCE Spectre software system settings and friendship at Infineon Technologies AG. I also appreciate Dr.-Ing. Ralf Brederlow, who also did a work on true random number generator technique and also helped me get started on this project. I also enjoyed talking with him about a variety of things, including trips to the mountains close to the Alps south of Munich. I would also be thankful for Prof. Dr. Svante Signell from the Royal Institute of Technology – KTH – IMIT – in Stockholm in Sweden who was my supervisor and final examiner for this project as well as his support with administration matters related to the University and guidance on final adjustment on the thesis writing style and report’s publication. I am thankful for the big support given by Ms. May-Britt Eklund Larsson before my trip to Sweden and during my study time at KTH caring about bureaucracy matters for master students and giving advices for documents required by the Swedish government. I should include my appreciation to all other Professors and university personal stuff during my master thesis program at KTH. I should not forget the valuable comments and suggestion given by my master student friends and opponents on the thesis presentation Michael Wester and Maksim Bryzgalov besides other master student friends like Sezi Yamac, Sevag Balkorkian and Hendrik Tengstedt with whose I had very funny times by doing laboratory projects during my study time in Sweden. I am very thankful to Ph.D. Prof. Claudio Garcia, Ph. D. Prof. José Roberto Castilho Pereira and Ph.D. Prof. Silvio Ernesto Barbin from the Electrical Engineering Faculty at the Polytechnic School of São Paulo University during my bachelor degree graduation time in Brazil and enthusiastic support for my applications to a master degree scholarship in Europe as well as office university personal stuff who cared about special required documents and certificates. I would like to express my lovely appreciation to my mother Rosemarie Klan Wilde, brother Daniel Emiliano Klan Wilde and sister Marcia Gabriela Klan Wilde who always encouraged me to do my master thesis in Europe and helped me on document matters in Brazil while I was in Sweden and Germany. I am also very thankful to the IMIT and to the Royal Institute of Technology – KTH – both based in Stockholm in Sweden who accepted me as a master student on the Master of Science Program on System-on-Chip Design and to the financial support given by the Swedish Foundation for International Cooperation in Research and Higher Education – STINT – during all my study and project thesis’ period. I should not forget that the whole project was performed at Infineon Technologies AG in Munich in Germany which conceded me very useful and state-of-the-art computers and software to conduct and finish this work.



Index 1. Abstract ........................................................................................................................................................ 3 2. Introduction .................................................................................................................................................. 3 3. Current and Common Random Number Generators Methods and the AIS 31 Standard Document .. 4

3.1 Metastability Method.............................................................................................................................. 4 3.2 Astable Multivibrator Method ............................................................................................................... 4 3.3 Dual Oscillator Sampling Method......................................................................................................... 5 3.4 Direct Noise Amplification Method ...................................................................................................... 5 3.5 Discrete-Time Chaotic Method ............................................................................................................. 6 3.6 Hybrid Mixed Method............................................................................................................................. 6 3.7 AIS 31 Document Standard for True Random Number Generators.................................................. 7

Class P1 TRNGs.................................................................................................................................... 7 Class P2 TRNGs.................................................................................................................................... 8 AIS 31 Standard Statistical Tests ........................................................................................................ 8

4. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter.......................................... 11 4.1 Sigma-Delta Modulator Analog-to-Digital Converters...................................................................... 11

4.1.1 Advantages of Oversampling Converters .................................................................................. 11 4.1.2 Oversampling without Noise Shaping ........................................................................................ 11

Quantization Noise Modelling ........................................................................................................... 11 White Noise Assumption ................................................................................................................... 11 Oversampling without Noise Shaping .............................................................................................. 12

4.1.3 Oversampling with Noise Shaping .............................................................................................. 13 Noise Shaped Sigma-Delta Modulator.............................................................................................. 15 First-Order Noise Shaping ................................................................................................................. 15 Second-Order Noise Shaping............................................................................................................ 17

4.1.4 Sigma-Delta Modulator and Noise Modelling ............................................................................. 18 4.2 Second Order Low Pass Sigma-Delta Modulator ............................................................................. 19 4.3 Fourth Order Band Pass Sigma-Delta Modulator ............................................................................. 20 4.4 Second Order High Pass Sigma-Delta Modulator ............................................................................ 22 4.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures .................................. 24

4.5.1 Digital Signal-Processing Decimation Filter Structure .......................................................... 24 4.5.2 Thermal Noise, Quantization Noise and Oversampling Rate Analysis ................................ 27 4.5.3 Choice of the Digital Bit Stream Generator System and Analysis ....................................... 29 4.5.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests............................................. 30

5. High Pass Sigma-Delta Modulator System Level Design...................................................................... 34 5.1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization .................................. 34

The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................... 34 The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit....... 36 The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure ............................ 38 The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit .... 40

6. Requirements for the Different Components of the Analog Circuit System ....................................... 41 6.1 Switched-Capacitor Circuit Requirements ........................................................................................ 41

Differential Sinusoidal Input Signal Amplitude Influence Analysis............................................... 41 Switched-Capacitor Coefficients Scaling Analysis......................................................................... 42 Switched-Capacitor Parasitic Capacitance Analysis ...................................................................... 43

6.2 Operational Amplifier Requirements ................................................................................................. 45 Operational Amplifier Gain Analysis ................................................................................................ 45 Operational Amplifier Input Capacitance Analysis ......................................................................... 46 Operational Amplifier Bandwidth Analysis ...................................................................................... 47

6.3 Comparator Requirements.................................................................................................................. 48 Comparator Offset Analysis .............................................................................................................. 48 Comparator Hysteresis Analysis ...................................................................................................... 48

7. Analog Components Circuit Design ........................................................................................................ 50 7.1 Operational Amplifier Transistor Circuit Design .............................................................................. 50 7.2 Comparator Transistor Circuit Design .............................................................................................. 56 7.3 Transmission-Gate Transistor Circuit Design .................................................................................. 57

8. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design, Simulation & Analysis.......... 58 9. Conclusion and Future Works ................................................................................................................. 64 10. References ............................................................................................................................................... 66 11. Appendix .................................................................................................................................................. 71



1. Abstract

Random number generators are essential components of many cryptographic systems. In contrast to pseudo random number generators which are based on digital algorithms, true random number generators produce a random bit stream from a nondeterministic natural source. Thermal noise is a possible source of unpredictable random noise.

The intention of the work is to analyze the feasibility of using a Sigma-Delta modulator based analog-to-digital converter for true random number generation, whereas the noise source is integrated into modulator’s loop as well as design a Sigma-Delta modulator ADC circuit structure on 90nm CMOS technology and additional digital-signal processing blocks for generation of a random bit stream. Besides that the work includes compliance comparations to international standard requirements given by international standard randomness tests as well as optimization and non-idealities analysis of the Sigma-Delta modulator related to its switched-capacitor, operational amplifier, comparator and transmission-gate circuit design requirements and additionally external environment influence analyses over the final implementation in transistor level circuit design of the Sigma-Delta modulator analog-to-digital converter and aggregated digital-signal processing blocks for constitution of a whole true random number generation system. 2. Introduction The continuous and fast growing use of digital communication, mobile, computer and network systems has aroused data security issue concerns where some type of data cryptography protection is required. Cryptography allows for the private and secure exchange of authentic messages using carefully generated and distributed cryptographic keys for encryption and decryption. The security of most cryptographic systems relies on unpredictable and irreproducible digital keystreams using a nondeterministic random number generator [1]. Cryptographers often base RNG (Random Number Generator) designs on hidden sources such as keyboard latency [2], hard disk drive air turbulence [3] and computer system clock state [1]. Nevertheless, the security of these designs is often limited on the obscurity and the secrecy of the quasirandom source. Due to this fact, systems that use truly random noise mechanism, such as electronic thermal noise, radioactive decay and atmospheric noise provide the utmost cryptographic security because there is no need to protect the obscurity of the key generation method [1]. With the widespread application of system-on-chip on electronic systems, robust integrated-circuit RNG designs will be needed for secure communication applications. Hardware RNG can feature a very high throughput when well designed, but the produced bit streams usually show a certain level of correlation due to bandwidth limitation, fabrication tolerances, flicker noise, aging and temperature drifts as well as external electromagnetic deterministic interferences. Random noise sources, such as thermal and shot noise, which are actually the only white stochastic processes which can be exploited at the integrated-circuit level, are often masked by deterministic disturbances like substrate noise, flicker noise, power supply noise and external electromagnetic interferences requiring special hardware and EMC shielding to comply with the international standards for true random number generation [4 5 6 7]. A common procedure to remove statistical imperfections in the output bit stream is to process the sequence with a carefully designed correcting or decorrelating algorithm which, from a high speed near-random input stream, generates a lower speed bit stream with increased statistical quality, rising up the entropy contained in the input sequence [8 9 10 11]. The present work wants to study and design a robust, thermal noise-based TRNG IC subcell, suitable for integration with digital encryption circuitry by using a Sigma-Delta modulator Analog-to-Digital Converter in which after digital signal-processing just the desired frequency band portion of the spectrum which contains the useful thermal noise is used to generate a random bit stream at the output of the system. The next Section 3 describes current and common RNG techniques as well as the AIS 31 Standard Statistical Tests for randomness analysis of the output random bit stream. Section 4 discusses the different options of Sigma Delta modulator structures and choice of one of them for the current work based on oversampling rate, thermal and flicker noise influences over the modulator’s output spectrum and AIS 31 Standard Statistical Tests results of the TRNG system model. Still in the same section are defined the digital signal-processing decimation filter and algorithm for generation of the output random bit stream. Section 5 presents two Sigma-Delta modulator circuit construction options for the previous section chosen structure, reporting the circuit model simulation results and choice of one of the circuits. Section 6 comes with the system requirements for the each of different components of the analog circuit design. Section 7 gives the electronic design of each component to be used on the final Sigma-Delta modulator circuit using the 90nm CMOS technology library in CADENCE Spectre [73] including theirs transient, small-signal AC and large-signal DC simulation results and analysis. Section 8 presents the final Sigma-Delta modulator ADC circuit its simulation results and tolerance analysis to external environment influences and final TRNG with a Sigma-Delta modulator ADC system followed by Section 9 discussing conclusions, observations and future researches themes for this random number generation solution.



3. Current and Common Random Number Generators Methods and the AIS 31 Standard Document From references it is possible to classify some different integrated-circuit methods for producing random data sequences, which are given as follow: metastability, astable multivibrator, dual oscillator sampling, direct noise amplification, discrete-time chaotic systems and hybrid techniques. All these methods generate output bit streams that can be statistically proved by standard randomness tests. 3.1 Metastability Method

The metastability method [12 13 14], shown in Fig. 3.1, uses the known metastability behaviour of digital

circuits when the input to a flip-flop is asynchronous to the system clock to generate random bit stream sequences. The metastability occurs when the input changes in unison with the clock setup time. This phenomenon creates instability in the circuit and produces oscillations, which can determine the high or low state of a comparator to generate a truly random bit stream.

Fig. 3.1: Metastability method for true random number generator Usually this method requires some type of negative feedback loop control to adjust the probability of the output bit stream bias to 50%, which also generates some colouring on the output spectrum that reduces the final output entropy. Due to this fact, this method usually has a post-processing unit [13 14] which reduces the output bit stream rate. 3.2 Astable Multivibrator Method The astable multivibrator method, shown in Fig. 3.2, usually uses and electron trap [15] or the capacitor voltage [16] fluctuations in one of the arm branches from an astable multivibrator which output is used to trigger a 1 bit counter that generates a one-bit random number.

Fig. 3.2: Astable Multivibrator method for true random number generator



The electron trap fluctuations are usually very large compared with those of thermal noise, eliminating the amplification of the noise source which saves area and reduces power consumption [15]. The drawback lies on the high evident flicker noise property, which adversely affects the statistical balance of the output random numbers. One proposed solution is to use the capacitor voltage fluctuation instead of a pure MOS device which eliminates the flicker property and is approximately six orders of magnitude greater than the thermal noise signal [16]. 3.3 Dual Oscillator Sampling Method

The dual oscillator sampling method [8 9 10 17 18], shown in Fig. 3.3, produces randomness from phase noise in free-running oscillators. The output of the fast oscillator is sampled on the rising edge of a slower clock using a D flip-flop. Oscillator jitters causes uncertainty in the exact sample values, ideally producing a random bit for each sample. By carefully selecting the ratio between the two oscillator frequencies an artificially enhanced randomness can be achieved [18].

Fig. 3.3: Dual Oscillator Sampling method for true random number generator

Previous experiments have proven that this method is more robust in the presence of deterministic noise

because of nonlinear aliasing phenomenon associated with sampling [18]. The drawback on this topology is that typical levels of oscillator jitter are not enough to produce statistical randomness and bit-to-bit uncorrelation which invokes the necessity of post-processing units at the output to further randomize it, potentially compromising the unpredictability of the system. 3.4 Direct Noise Amplification Method

The direct noise amplification method [19 20 21 22 23 24], shown in Fig. 3.4, uses a high-bandwidth amplifier to process the tiny ac voltage produced by a noise source such as thermal or shot noise. Due to the low magnitude of these types of noise sources very high requirements are put in the design of the amplifier which needs to accurately amplified the signal to thresholds levels with no bias to a clocked comparator.

Fig. 3.4: Direct Noise Amplification method for true random number generator

This technique permits a good shielding of the noise source from external electromagnetic interferes, but lacks

of adequate shielding from power supply and substrate signals in an IC environment which prohibits the exclusive use of this method for IC-based cryptographic systems. Nevertheless, due to flicker noise and band limitation characteristics of the amplifier output, usually a post-processing unit and a zero offset feedback control are required to randomize the final output bit stream.



3.5 Discrete-Time Chaotic Method

The discrete-time chaotic method can further be subdivided into categories, the first corresponding to switching-capacitor dynamic systems [25 26], the second to switched-current [27 28 29 30] and the third to linear unbalanced circuits or pipelined ADCs [31 32 11]. Chaotic systems are usually implemented using discrete-time analog signal processing techniques [27]. As an example, take the Bernoulli shift map described by the following iterative relationship:

Xn = [2(Xn-1 – e(n)] mod 0.1 (3.1)

Where e(n) represents a Gaussian noise signal. It has been shown that sequences produced by the previous

iteration and similar systems are spectrally flat and uniformly distributed [33]. Furthermore, the divergence of trajectories associated with chaos, along with the inclusion of noise, renders sequences from the previous iteration unpredictable to an extent, qualifying the system to be used as a truly random bit source [3434].

Circuits which realize systems such as the previous iteration equation are similar to algorithmic A/D converters.

In addiction, the cascading of N stages of such a circuit that implements the given iteration equation turns into a classical N-bit algorithmic A/D converter with an input range of [0, 1]. Fig. 3.5 shows such a type of A/D-based RNG [11 32].

Fig. 3.5: Discrete-Time Chaotic method for true random number generator 3.6 Hybrid Mixed Method The hybrid method is a mixture of the precedent direct noise amplification, dual oscillator sampling and discrete-time chaotic methods [7], shown in Fig. 6. This method tries to take all advantages from these three methods to reduce or overcome drawbacks when separately used.

Fig. 3.6: Hybrid method for true random number generator

These solution have shown to be insensitive to non-random influences and is unaffected by minor circuit errors, such as mismatches, offsets, nonlinearities and process variations [7]. The drawback lies on the big amount of Si area and power dissipation that the circuit requires as well as the limitations for the operational amplifiers used on the direct amplification and on the A/D blocks.



3.7 AIS 31 Document Standard for True Random Number Generators Although random numbers play an important role in numerous cryptographic applications, ITSEC (Information Technology Security Evaluation Criteria [35]) and CC (Common Criteria [36]) do not specify any uniform evaluation criteria for random numbers. For this purpose the AIS 31 Document Standard [4] describes the evaluation criteria for true (physical) random number generators. Through this AIS 31 Document Standard, a TRNG (True Random Number Generator) contains an internal physical noise source. It usually delivers an analogue signal that is digitized for further processing. The digitized noise signal can be transformed into an internal random number sequence by means of post-processing in order to improve the probability distribution of the digitized noise signal sequence.

For good physical noise sources, post-processing is not necessary and the digitized noise signal can be

transmitted directly to the output block. In this case, the sequence of internal random numbers corresponds to the digitized noise signal sequence. The output block synchronizes the continuous or non-periodic generation of internal random sequence with the calling of the (external) random number sequence.

The assessment of a physical random number generator is essentially based on statistical tests. On the basis of

different potential attack scenarios, various applications can place different requirements on the properties of the external, and therefore of course also the internal, random numbers. In order to take this into account, the AIS 31 Standard Statistical Tests [4] introduces two functionality classes (P1 and P2). Roughly explaining, the P1 property requires the internal random numbers to be statistically inconspicuous. The P2-specific requirements should guarantee that they are practically impossible to determine even if the predecessors or successors are known. Depending on the maximum attack potential attributed to a potential perpetrator, the target of evaluation must itself recognize total failure or any interference that occurs in the noise source and may need to be able to resist systematic manipulation attempts.

Fig.3.7 shows a diagram with the essential parts of a TRNG. It represents the typical sequential processing of the signals.

Fig 3.7: AIS 31 Standard TRNG essential parts diagram Class P1 TRNGs TRNGs that belong to this class could be used in following type of applications:

- challenge-response protocols; - openly transmitted, non-constant initialization vectors; - seed generation for Deterministic RNGs of classes K1 and K2 [6]

The main requirements for the class P1 TRNGs are described by the AIS 31 Standard Statistical Tests

document [4] and resumed as follow: - random vectors formed from internal random numbers sequences pass the disjointness test T0 and the test

procedure and evaluation rules specified in [4], - if total failure of the noise source occurs when the TRNG is switched on, this must be detected

immediately, - if total failure of the noise source occurs while the TRNG is being operated, it has to be prohibited that

random numbers are output whose internal random sequence was generated completely after the total failure,

- the above properties must also be verified under the intended external usage conditions (temperature, power supply, etc.) insofar as these can influence the function of the noise source,

- an online test must be implemented that checks the quality of the internal random numbers when triggered externally.



Class P2 TRNGs TRNGs that belong to this class could be used in following type of applications:

- generation of signature key pairs, - generation of DDS signature (private key x or random number k), - generation of session keys for symmetric encryption mechanisms, - random padding bits, - zero-knowledge proofs, - generation of seeds for Deterministic RNGs in classes K3 and K4 [6].

The main requirements for the class P2 TRNGs are as described by the AIS 31 Standard Statistical Tests document [4] and resumed as follow:

- the TRNG belongs to class P1 with at least the same strength of mechanisms and functions; - digitized noise signal sequences meet particular criteria or pass statistical tests intended to rule out features

such as multi-step dependencies. Moreover, the entropy test T8, specified in [4], is passed; - if mathematical post-processing is present, it shall not reduce the average entropy per bit; - statistical minimum properties of the digitized noise signal sequence must be proved each time the TRNG

is started; - if total failure of the noise source occurs while the TRNG is in operation, it has to be prohibited that

random numbers are output whose corresponding internal random sequence was generated completely after the total failure;

- an online test must be implemented with which the statistical quality of the digitized noise signal sequence can be checked. It must be possible to trigger this online test externally or the TRNG must trigger at regular intervals;

- the above properties must also be verified under the intended external usage conditions (temperature, power supply, etc.) insofar as these can influence the function of the noise source;

- the TRNG must trigger the online test itself.

For detailed specification and how to apply the tests on the TRNG the original AIS 31 document [4] should be analyzed more carefully.

AIS 31 Standard Statistical Tests For the purpose of choice of the subsequent Sigma-Delta structures on the actual work the specified statistical

tests on AIS 31 document [4] will be used as quality parameters of the intended final solution. Tests to classify a TRNG under Class P1 and P2 are described as follow according to the AIS 31 document [4]:

Test T0 (Disjointness Test)

The sequence w1, …, w65535 ∈ 0,148 passes the disjointness test if the subsequent members are pairwise different.

From a sequence of 3145680 generated bits w1, …, w65535 numbers of 48 bits each one are built which are then compared one after other to check for the condition that one wn number is not equal to its preceding wn-1. If this condition passes for all numbers the test is fulfilled.

Test T1 (Monobit Test)

X = ∑=

20000

1jjb (3.2)

The bit sequence b1, …, b20000 passes the monobit test if 9654 < X < 10346.



Test T2 (Poker Test) For j = 1, … , 5000 let cj = 8.b4j-3 + 4.b4j-2 + 2.b4j-1 + b4j. Furthermore, f[i]:=| j: cj=i |, i ∈ [0,15] .

5000][.500016 15

0

2 −

= ∑=i

ifY (3.3)

From a set of 20000 generated bits 5000 numbers cj are created each from 4 subsequent bits as stated. From these 5000 numbers a frequency distribution for its values from 0 till 15 is built to later evaluate the Pocker Test parameter Y. The bit sequence b1, …, b20000 passes the Pocker Test (=χ2 modification test with 15 degrees of freedom ) if 1.03 < Y < 57.4.

Test T3 (Run Test)

A run is a maximum sub-sequence of consecutive zeroes or ones. The bit sequence b1, …, b20000 passes the run test if the number of occurring lengths lies within the permitted intervals, as specified at the Table 3.1. The runs of zeroes and ones are evaluated separately.

Run length Permitted Interval 1 2267 – 2733 2 1079 – 1421 3 502 – 748 4 233 – 402 5 90 – 223 ≥ 6 90 – 233

Table 3.1: Limits for Run Test Test T4 (Long Run Test)

A run of length ≥ 34 is called a long run. The bit sequence b1, …, b20000 passes the long run test if no long run occurs.

Test T5 (Autocorrelation Test)

For τ ∈ 1,…, 5000, ∑=

+⊕=5000

1

)(j

kjj bbZτ (3.4)

The bit sequence b1, …, b20000 passes the autocorrelation test (with shift τ ) if 2326 < Zτ < 2674. (Please note that the sub-sequence b10001, …, b20000 is not used in the test variable.)

Test T6 (Uniform Distribution Test) The sequence w1, …, wn ∈ 0,1k passes the uniform distribution test with parameters (k, n, a) if:

]2,2[|.1 aaxwnjn

kkj +−∈=≤ −− for all x ∈ 0,1k (3.5)

Test T7 (Comparative Test for Multinomial Distributions)

For each i ∈ 1, …, h let the n-element sample wi,1, …, wi,n assume values from the set 0,1, …(s-1). According to the null hypothesis, the multinomial distributions on which the individual samples are based are identical. Furthermore, for t ∈ 0, …, (s-1) let fi[t]:=|j: wij = t|, and let pt:= (f1[t]+ … + fh[t])/(hn) be the relative frequency for the occurrence of t determined from the total of all samples. Under the null hypothesis, the test variable t

stti

hi

npnptf∑∑−==

−)1,...,(0

2

,...,1

/)][( is

approximately χ2-distributed with (h-1)(s-1) degrees of freedom. In the special case where h = s = 2 and at the significance level α = 0.001, the rejection limit is 15.13.



Test T8 (Entropy Test)

The entropy test is performed in accordance with Coron [4]. The bit sequence b1, ..., b(Q+K)L is segmented into non-overlapping output words w1, …, wQ+K of length L. An is the distance from wn to its predecessor with the same value, and

An = n if no i < n exist with wn=wn-i Or

An = min i | i ≥ 1, wn = wn-i in all other cases Test variable f: 0,1(Q+K)L → R is determined for the Coron test by

∑+

+

−=

KQ

Qnc Ag

kSf

1

)(1)( where ∑−

=

=1

1

1)2log(

1)(i

k kig (3.6)

For a stationary binary-value random source with a finite memory, the expected value for test variable fc is closely related to the entropy increase per L-bit block. Indeed, if the noise source is independent, the two are equal. For ideal noise sources, a good approximation of the distribution of test variable fc is provided by a normal distribution with expected value µc and variance (τ c)

2:

KAgVarKLc n

cc))((),( =τ ,

KLeLdKLc

L

c2).()(),( += (3.7)

Where the parameters of the preceding equation 3.7 are given by following Table 3.2:

L Variance Var(g(An)) d(L) e(L) 3 2.5769918 0.3313257 0.4381809 4 2.9191004 0.3516506 0.4050170 5 3.1291382 0.3660832 0.3856668 6 3.2547450 0.3758725 0.3743782 7 3.3282150 0.3822459 0.3678269 8 3.3704039 0.3862500 0.3640569 9 3.3942629 0.3886906 0.3619091

10 3.4075860 0.3901408 0.3606982 11 3.4149476 0.3909846 0.3600222 12 3.4189794 0.3914671 0.3596484 13 3.4211711 0.3917390 0.3594433 14 3.4223549 0.3918905 0.3593316 15 3.4229908 0.3919740 0.3592712 16 3.4233308 0.3920198 0.3592384

infinite 3.4237147 0.3920729 0.3592016 Table 3.2: Entropy Tests Parameters For the case of L = 8, K = 256000 and Q = 256 the test passes if fc ≥ 7.976.



4. Possible TRNG Structures with a Sigma-Delta Modulator A/D Converter 4.1 Sigma-Delta Modulator Analog-to-Digital Converters 4.1.1 Advantages of Oversampling Converters Oversampling A/D converters have become popular for high-resolution medium-to-low speed applications. The major reasons for their popularity include the following characteristics: oversampling converters relax the requirements placed on analogue circuitry at the expense of more complicated digital circuitry.

This trade-off becomes more desirable for modern submicron technologies with low power supplies where complicated high-speed digital circuitry is more easily realized in less area, but the realization of high-resolution analog circuitry is complicated by low power-supply voltages and poor transistor output impedance (caused by short-channel effects).

With oversampling data converters, the analogue components have reduced requirements on matching

tolerances and amplifier gains. A second advantage of oversampling converters is that they simplify the requirements placed on analogue anti-aliasing filters for A/D converters. Furthermore, a sample-and-hold is usually not required at the input of an oversampling A/D converter. In this item, the basics of oversampling converters are discussed. Extra bits of resolution can be extracted from converters that sample much faster than the Nyquist rate.

In addiction, this extra resolution can be obtained with lower oversampling rates by spectrally shaping the

quantization noise through the use of a feedback structure. The use of shaped quantization noise applied to oversampling signals is commonly referred to as Sigma-Delta modulation. Simple first- and second- order Sigma-Delta modulators are discussed, followed by a discussion of which structure of the second-order Sigma-delta modulator should be used for the current development of a TRNG. 4.1.2 Oversampling without Noise Shaping It is possible to show that extra dynamic range can be obtained by spreading the quantization noise power over a larger frequency range, but only 3dB for every doubling of the sample rate. To obtain much higher dynamic-range improvements as the sampling rate is increased, noise shaping through the use of feedback can be used and is discussed on the following texts. Quantization Noise Modelling It is possible to model a quantizer as adding quantization error e(n), as show in Fig. 4.1. The output signal, y(n), is equal to the closest quantized value of x(n). The quantization error is the difference between the input and output values. This model is exact if one recognizes that the quantization noise error is not an independent signal but may be strongly related to the input signal, x(n). However, this linear model becomes approximate when assumptions are made about the statistical properties of e(n), such as e(n) being an independent white-noise signal. However, even though approximate, it has been found that this models leads to a much simpler understanding of Sigma-Delta modulators and with some exceptions is usually reasonably accurate. White Noise Assumption If x(n) is assumed uncorrelated and very active, e(n) can be approximated as an independent random number uniformly distributed between ±∆/2, where ∆ equals the difference between two adjacent quantization levels. Thus, the quantization noise power equals ∆2/12 [38] and is independent of the sampling frequency, fs. The spectral density of e(n), Se(f), is white and all its power is within ±fs/2 as shown in Fig. 4.1.

Fig. 4.1: Quantization Noise Modelling



Where kx in Fig. 4.1 is calculated by:

12)(

22

2/

2/

22/

2/

2 ∆=== ∫∫+

−

+

−sx

fs

fsx

fs

fs

fkdfkdffSe (4.1)

sx f

k 112

∆= (4.2)

Oversampling without Noise Shaping Oversampling occurs when the signals of interest are band-limited to f0 yet the sample rate is fs, where fs>2f0 (2f0 being the Nyquist rate or, equivalently, the minimum sampling rate for signals band-limited to f0). We define the oversampling ratio, OSR, as:

o

s

ffOSR

2= (4.3)

After quantization, since the signals of interest are all below f0, y1(n) is filtered by H(f) to create the signal y2(n), as shown in Fig. 4.2. This filter eliminates quantization noise greater than f0. Assuming the input signal is a sinusoidal wave, its maximum peak value without clipping is 2N(∆/2). For this maximum sinusoidal wave, the signal power, Ps, has a power equal to:

82

222 222 NN

Ps ∆=

∆= (4.4)

The power of the input signal within y2(n) remains the same as before since it was assumed the signal’s frequency content is below f0. However, noticing that the quantization noise is assumed to be a uniformly distributed spectrum over –fs/2 till fs/2, the quantization noise power is reduced to:

∆=∆=== ∫∫

−

+

− OSRffdfkdffHfSePes

f

fx

fs

fs

11212

2)()(22

022/

2/

220

0

(4.5)

Therefore, doubling OSR decreases the quantization noise power by one-half or, equivalently, 3 dB. It is possible also to calculate the maximum SNR (in dB) to be the ratio of the maximum sinusoidal power to the quantization noise in the signal y2(n):

)log(10223log10log10max 2 OSR

PePsSNR N +

=

= (4.6)

Which is:

)log(1076.102.6max OSRNSNR ++= (4.7) The first term is the SNR due to the N-bit quantizer while the OSR term is the SNR enhancement obtained from oversampling. Here we see that straight oversampling gives a SNR improvement of 3 dB/octave or, equivalently, 0.5 bits/octave. The reason for this SNR improvement through the use of oversampling is that when quantized samples are averaged together, the signal portion adds linearly, whereas the noise portion adds as the square root of the sum of the squares.

Fig. 4.2: Oversampling System without Noise Shaping



While oversampling improves the signal-to-noise ratio, it does not improve linearity [38]. However, with a high enough sampling rate, the output from a 1-bit converter can be filtered to obtain a higher bit resolution. This linearity is a result of a 1-bit A/D converter having only two output values and, since two points define a straight line, no trimming or calibration is required. This inherent linearity is one of the major motivations for making use of oversampling techniques with 1-bit A/D converters. 4.1.3 Oversampling with Noise Shaping The system architecture of a Sigma-Delta oversampling A/D converter and its related signals are shown in Fig. 4.3. The first stage is a continuous-time anti-aliasing filter and is required to band-limit the input signal to frequencies less than the difference between the sampling frequency fs minus the input signal Xin(t) bandwidth f0 as depicted on the block diagram of Fig. 4.4.

When the oversampling ratio is large, the anti-aliasing filter can often be quite simple. Following the anti-aliasing filter, the continuous-time signal, Xc(t) (Fig. 4.4a), is sampled by a sample-an-hold circuit. The resulting signal, Xsh(t) (Fig. 4.4b), is then processed by a Sigma-Delta modulator, which converts the analog signal into a noise-shaped low-resolution digital signal Xdsm(n) (Fig. 4.4c). This 1-bit digital signal is assumed to be linearly related to the input signal Xc(t) (Fig. 4.4a), although it includes a large amount of out-of-band quantization noise.

To remove this out-of-band quantization noise, the fourth block in the system is a digital decimation filter,

which converts the oversampled low-resolution digital signal into a high-resolution digital signal at a lower sampling rate usually equal or a little higher than twice the frequency of the desired bandwidth of the input signal. The decimation filter can be conceptually thought of as a low-pass filter, which generates Xlp(n) (Fig. 4.4d). Note that this low-pass filter will also remove any higher-frequency signal content that was originally on the signal, Xc(t) (Fig. 4.4a), and thus also acts as an anti-aliasing filter to limit signals to one-half the final output sampling rate, 2f0, as opposed to the anti-aliasing filter at the input, which needed to only limit signals to frequencies less than fs/2.

Next the Xlp(n) (Fig. 4.4d) signal is resampled by a down sampler at 2f0 generating finally the output signal

Xs(t) (Fig. 4.4e) by simply keeping samples at a submultiple of the oversampling rate and throwing away the rest. Depicted on Fig4.4e is an oversampling rate of 6.

This decimation process does not result in any loss of information, since the bandwidth of the signal was

assumed to be f0. In other words, the signal Xlp(n) has redundant spectra information since it is an oversampled signal where all of its spectral information lies well below π, and by throwing away samples, the spectral information is spread over 0 and π.

It should be mentioned that in many realizations where the Sigma-Delta modulator is built using switched-

capacitor circuitry, a separate sample-and-hold is not required, as the continuous-time signal is inherently sampled by the switches and input capacitors on the switched-capacitor Sigma-Delta modulator. It is of interest to look at what element most strongly affects the linearity of this oversampling A/D system. From the Sigma-Delta modulator, it should be noticed that an internal D/A converter is used whose output signal is combined with the input signal. As a result, the overall linearity of this Sigma-Delta modulator converter depends strongly on the linearity of its internal D/A converter especially in the case that the Sigma-Delta modulator uses multi bit D/A converters. However on this current work there is used a 1-bit D/A converter which is always linear and will not affect the linearity of the system as mentioned before.

Fig. 4.3: Block Diagram of a Low Pass Sigma-Delta oversampling A/D Converter



Fig. 4.4: Signals and Spectra of the Low Pass Sigma-Delta oversampled A/D Converter



Noise Shaped Sigma-Delta Modulator A general noise-shaped Sigma-Delta modulator and its linear model are shown in Fig. 4.5. This arrangement is known as an interpolative structure and is analogous to an amplifier realized using an operational amplifier and feedback. In this analogy, the feedback reduces the effect of noise of the output stage of the operational amplifier in the closed-loop amplifier’s output signal at low frequencies when the operational amplifier gain is high.

At high frequencies, when the operational amplifier’s gain is low, the noise is not reduced. Note that the

quantizer is shown for the general case where many output levels occur. While most present oversampling converters make use of 1-bit quantizers due to reasons already discussed, there is certainly no reason to restrict ourselves to such implementations. From Fig. 4.5 it is possible two write to different transfer functions, one called the Signal Transfer Function (STF) and the second defined as the Noise Transfer Function (NTF) which are given by following equations:

)(1)(

)()()(

zHzH

zUzYzSTF

+== (4.8)

)(11

)()()(

zHzEzYzNFT

+== (4.9)

Fig. 4.5: A general Sigma-Delta Modulator (a) and its equivalent linear model (b)

From equations (4.8) and (4.9) it is possible to observe that the zeros of the noise transfer function are equal to the poles of H(z). That means that, when H(z) goes to infinity, NTF(z) will go to zero. It is possible to write the output signal as the combination of the input signal and the noise signal as follow:

)()()()()( zEzNFTzUzSTFzY += (4.10) To shape the quantization noise in the case of a low-pass implementation, we choose H(z) such that its magnitude is large from 0 to f0. With such a choice, the signal transfer function, SFT(z), will approximate unity over the frequency band of interest very similarly to an opamp in a unity-gain feedback configuration. Furthermore, the noise transfer function, NTF(z), will approximate zero over the same band.

Thus, the quantization noise is reduced over the frequency band of interest while the signal itself is largely

unaffected. The high-frequency noise is not reduced by the feedback as there is little loop gain at high frequencies. However, additional post filtering can remove the out-of-band quantization noise with little effect on the desired signal. First-Order Noise Shaping The first-order noise shaping is realized when the noise transfer function, NTF(z), has a zero at dc (z = 1), so that the quantization noise is high-pass filtered. Since the zeros of NTF(z) are equal to the poles of H(z), it is possible to obtain first-order noise shaping by letting H(z) be a discrete-time integrator. Specifically:



11)(−

=z

zH (4.11)

From a frequency domain view, the signal transfer function, STF(z), from equation (4.8) is:

1

111

11

)()()( −=

−+

−== z

z

zzUzYzSTF (4.12)

And the noise transfer function, NTF(z), from equation (4.9) is:

)1(

111

1)()()( 1−−=

−+

== z

zzUzYzNTF (4.13)

The signal transfer function, STF(z), resumes into just a delay, while the noise transfer function, NTF(z), is a discrete-time differentiator, equivalently, a high-pass filter. The magnitude of the noise transfer function is given by:

fsfj

fsfjfs

fjfsfj

fsfj

fsfj

ejfsfej

jeeefNFTez

ππππ

ππ π −−−

−××

=××−=−=⇒→ 2sin22

1)(22

(4.14)

Taking the magnitude of both sides, it comes out the high-pass function:

=

sfffNFT πsin2)( (4.15)

The quantization noise power over the frequency band from 0 to f0 is given using equations (4.1) and (4.15) by:

∫∫−−

∆==fo

fo ss

fo

fo

dfff

fdffNFTfSePe

2222 sin21

12)()( π

(4.16)

Making the approximation that f0<<fs, so that it is possible to approximate sin(πf/fs) to be πf/fs:

3223

022 1

362

312

∆=

∆=OSRf

fPes

ππ (4.17)

Assuming the maximum signal power is the same as that obtained before in equation (4.4), the maximum SNR for this case is given by:

+

== 3

22 )(3log102

23log10log10max OSR

PePsSNR N

π (4.18)

Or, equivalently:

)log(3017.576.102.6max OSRNSNR +−+= (4.19) It is possible to observe that doubling the OSR gives an SNR improvement for a first-order modulator of 9dB or, equivalently, a gain of 1.5 bit/octave.



Second-Order Noise Shaping The modulator shown in Fig. 4.6 realizes second-order noise shaping. For this modulator the signal transfer

function using the same H(z) equation (4.11) is given by:

2)( −= zzSTF (4.20)

And the noise transfer function is given by:

21 )1()( −−= zzNTF (4.21)

Fig. 4.6: Second-Order Sigma-Delta Modulator System

The magnitude of the noise transfer function can be shown to be given by:

2

sin2)(

=

sfffNFT π

(4.22)

This results in the quantization noise power over the frequency band of interest being given by:

542 160

∆=

OSRPe π

(4.23)

Assuming the maximum signal power is that obtained in equation (4.4), the maximum SNR for this case is:

+

== 5

42 )(5log102

23log10log10max OSR

PePsSNR N

π (4.24)

Or, equivalently:

)log(509.1276.102.6max OSRNSNR +−+= (4.25) By doubling the OSR the SNR for a second-order modulator is improved by 15 dB or, equivalently, a gain of 2.5bit/octave. Fig. 4.7 depicts the different noise-shaping functions reported till now.

Fig. 4.7: Different Noise Shaping Transfer Functions



From Fig. 4.7 is it possible to observe that the second order system has a better noise-shaping function compared to the first-order system on the bandwidth on interest f0 for the case of a Low Pass Sigma-Delta Modulator, which turns into a better SNDR for the system as it can be compared between equations (4.19) and (4.25). Additionally, the second order system is unconditionally stable in opposite to higher order systems which stability needs to be certified and the behaviour of the real second order system approaches much more to the ideal system model compared to the real first order system behaviour to the ideal system model [38 39]. For this reason as first solution approach for this work further analysis will be done using a second-order Sigma-Delta modulator system which has also a better controllable parameterization by choosing the appropriate circuit structure. 4.1.4 Sigma-Delta Modulator and Noise Modelling The present work proposes a new method to generate random numbers in which a Sigma-Delta modulator ADC is used to filter out the natural thermal noise present on the switched capacitors which further is processed by a digital signal processing block to give out the random bit stream. The overall system view with Sigma-Delta Modulator ADC for use as a TRNG is shown in Fig. 4.8.

Fig. 4.8: TRNG with a Sigma-Delta Modulator A/D Converter Consider the general structure of a two stage Sigma-Delta modulator as shown in Fig. 4.9 with the noise due to the 1st and 2nd stage switched-capacitor circuits (Et1(z) and Et2(z)) and the quantization noise from the 1-bit ADC (Eq(z)) at the output included in the model.

Fig. 4.9: General structure of a Sigma-Delta Modulator with thermal and quantization noise modelling The general expressions for the transfer functions of this model are then as follow:

)()(21)(

)()()(

)()(21)(

)(2)()(

)()(21)(

)(1)()(

)()(211

)()()(

2

2

22

2

2

1

2

zHzHzH

zUzYzSTF

zHzHzH

zEtzYzNTF

zHzHzH

zEtzYzNTF

zHzHzEqzYzNTF

Et

Et

Eq

++==

++==

++==

++==

(4.26)

Setting H(z) with an appropriate transfer function there are three possible Sigma-Delta modulators that can be gotten from this structure which are given as follow:



4.2 Second Order Low Pass Sigma-Delta Modulator For

1

1

1)( −

−

−=

zzzH (4.27)

The general expressions for the transfer functions translate into:

2112

21

21 )(),1()(,)(,)1()( −−−−− =−==−= zzSTFzzzNTFzzNTFzzNTF EtEtEq (4.28) Whose spectra when applying the transformation 1== Tforez Tjϖ can be seen on following Fig. 4.10:

0 0.5 10

1

2

3

4|STF(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEq(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt1(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt2(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

Fig. 4.10: Transfer functions frequency response for the 2nd Order Low Pass Sigma-Delta Modulator

Applying a sinusoidal signal with frequency equal to 2π/ratio/OSR/2 [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig. 4.11 is generated. The left graphic on Fig. 4.11 presents the SNDR curves at the low frequency bandwidth of interest for different oversampling rates from 4 to 256 calculated by applying different sinusoidal signal amplitudes from -100dB to 0dB into the modulator’s circuit depicted of Fig. 4.9 using equation (4.27) for H(z). The right graphic on Fig 4.11 shows the maximum SNDR obtained for the used oversampling rates. As it is possible to see, for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements. From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical value calculated by equation (4.29) taken from reference [40] and the simulated value due to the fact that the equation (4.29) does not take into account non-linearity’s on the real system, but still gives a reasonable approach to the behaviour and quantification of the SNDR on the real system.

+= + )12(

)2()12(

23log10 L

ltheoretica OSRL

LSNRπ

, where L is the order of the system (4.29)



-100 -80 -60 -40 -20 00

20

40

60

80

100

120Lowpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256

Vin [dB]

SN

DR

[dB

]

101

102

0

20

40

60

80

100

120

OSR

SN

DR

[dB

]

Lowpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256

TheoreticalSimulated

Fig. 4.11: SNDR for different OSR on a 2nd Order Low Pass Sigma-Delta Modulator

4.3 Fourth Order Band Pass Sigma-Delta Modulator

To get a Band Pass Sigma-Delta Modulator a discrete-time low-pass-to-band-pass transformation [3] can be used:

111

)( <<−++−→ a

azazzz , which gives: 21

21

21)( −−

−−

++−−=

zazzazzH (4.30)

Where the case a = 0 generates 2zz −→ . Negative a gives systems closer to DC and positive a gives

systems with passband closer to π. By choosing a = 0 the Band Pass Sigma-Delta Modulator is placed exactly over π/2 which simplifies further digital signal processing algorithms. The general expressions for the transfer functions of this model are then as follow:

221

4322

221

43221

2

221

4322

1

221

43221

212)(

213)12()(

212)(

214)42(41)(

−−

−−−

−−

−−−−

−−

−−−

−−

−−−−

++++=

++−−+−−=

++++=

+++++++=

zaazzazzazSTF

zaazzazzaazzNTF

zaazzazzazNTF

zaazzazzaazzNTF

Et

Et

Eq

(4.31)



Whose spectra when applying the transformation 1== Tforez Tjϖ can be seen on following Fig. 4.12:

0 0.5 10

1

2

3

4|STF(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEq(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt1(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt2(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

Fig. 4.12: Transfer functions frequency response for the 4th Order Band Pass Sigma-Delta Modulator Applying a sinusoidal signal with frequency equal to ( (2.pi/4) + (2.pi/ratio/OSR/4) ) [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig. 4.13 is generated:

-100 -80 -60 -40 -20 00

20

40

60

80

100

120Bandpass 4th Order SDM, OSR = 4 8 16 32 64 128 256

Vin [dB]

SN

DR

[dB

]

101

102

0

20

40

60

80

100

120

OSR

SN

DR

[dB

]

Bandpass 4th Order SDM, OSR = 4 8 16 32 64 128 256


Fig. 4.13: SNDR for different OSR on a 4th Order Band Pass Sigma-Delta Modulator



The left graphic on Fig. 4.13 presents the SNDR curves at the band pass frequency bandwidth of interest for

different oversampling rates from 4 to 256 calculated by applying different sinusoidal signal input amplitudes from -100dB to 0dB into the modulator’s circuit depicted of Fig. 4.9 using the equation (4.30) for H(z) with parameter a set to zero to get a bandwidth of interest with central frequency on π/2 [rads/s].

The right graphic on Fig 4.13 shows the maximum SNDR obtained for the different used oversampling rates.

As it is possible to see, again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfill the AIS 31 Standard Statistical Tests requirements. From the same graphic it is possible to see a slightly difference of approximately 6dB between the theoretical value calculated by equation (4.29) from [40] and the simulated value for the cases of oversampling rates lower than 64 whose reasons were already explained previously. 4.4 Second Order High Pass Sigma-Delta Modulator

For

1

1

1)( −

−

+−=

zzzH (4.32)

The general expressions for the transfer functions translate into:

211

22

121 )(),1()(,)(,)1()( −−−−− =+−==+= zzSTFzzzNTFzzNTFzzNTF EtEtEq (4.33)

Whose spectra when applying the transformation 1== Tforez Tjϖ can be seen on following Fig. 4.14:

0 0.5 10

1

2

3

4|STF(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEq(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt1(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

0 0.5 10

1

2

3

4

|NTFEt2(z=ejω)|

ω [x(2π) rad/s]

Mag

nitu

de

Fig. 4.14: Transfer functions frequency response for the 2nd Order High Pass Sigma-Delta Modulator Applying a sinusoidal signal with frequency equal to ( pi - (2.pi/ratio/OSR/2) ) [rad/s] at the modulator’s input with ratio set to 4 and calculating the signal-to-noise ratio for different oversampling rates and different input amplitudes the following SNDR curve depicted on Fig. 4.15 is generated.



The left graphic on Fig. 4.15 presents the SNDR curves at the high frequency bandwidth of interest for different oversampling rates from 4 to 256 calculated by applying different sinusoidal input signal amplitudes from -100dB to 0dB into the modulator’s circuit depicted of Fig. 4.9 using the equation (4.32) for H(z).

The right graphic on Fig 4.15 shows the maximum SNDR obtained for the different used oversampling rates.

As it is possible to see, again for oversampling rates greater than 128 the system gives a SNDR greater than 80dB which further will be seeing in this work as enough to fulfil the AIS 31 Standard Statistical Tests requirements.

-100 -80 -60 -40 -20 00

20

40

60

80

100

120Highpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256

Vin [dB]

SN

DR

[dB

]

101

102

0

20

40

60

80

100

120

OSR

SN

DR

[dB

]

Highpass 2nd Order SDM, OSR = 4 8 16 32 64 128 256


Fig. 4.15: SNDR for different OSR on a 2nd Order High Pass Sigma-Delta Modulator

In a first system structure analysis, if it is considered that the noise present in the circuit is just composed of thermal and quantization noise then due to their uniform distributed spectral characteristics it would be possible to apply directly a Low Pass Sigma-Delta Modulator and the appropriate digital signal processing filters to obtain a final noise spectrum at the output composed by just thermal noise with the remaining quantization noise damped as much as possible with a magnitude as low as possible compared to the thermal noise.

But in a real application the total noise of the circuit is the summation of the power of the theoretical loop quantization noise, switched-capacitors thermal noise, digital signal processing truncation noise, operational amplifier thermal noise and the intrinsic flicker noise [38 52 53 54 55 56 57 58 59 60 61] which yields to the use of Sigma-Delta modulators that work in band frequencies where these remaining noise sources have less power magnitude than the circuit’s thermal noise. Taking into account the last observation then from the possible analyzed Sigma-Delta modulators the suitable ones to this application would be the band pass or the high pass structures. From previous Figs. 4.13 and 4.15 it is possible to observe that the band pass Sigma-Delta modulator has a slightly 6dB SNDR advantage over the high pass one for oversampling rates greater than 64, but it should be remembered that the high pass system in this case is a 2nd order system compared to 4th order band pass system which requires more area, circuitry and power consumption on the die. The further analysis then should be to find out which of the two appointed structures: band pass or high pass give out the best uniform distributed spectrum at the bandwidth of interest for later generation of the random output bit stream considering the amount of chip area, complexity to build the circuit, power consumption, required digital-signal processing filters and influence of the flicker noise at the output of each system.



4.5 Choice of the Sigma-Delta Modulator & DSP Decimation Filter Structures 4.5.1 Digital Signal-Processing Decimation Filter Structure

One usual approach [38] to digital signal process the output of a Sigma-Delta modulator system is shown in Fig. 4.16.

Fig. 4.16: Usual Sigma-Delta Modulator Output Decimation Processing System

The TSinc Filter block removes much of the quantization noise such that the output can be downsampled later. The TSinc Filter block is a cascade of L+1 (L is equal to order of the Sigma-Delta modulator) averaging filters with the following transfer function TSinc(z) given on next equation (4.34) taken from [38] and shown in Fig. 4.17 for OSR = 256 and cases L = 2 and L = 4:

0

)1(

1)1( 241,

111)(

ffOSRandOSRMwhere

zz

MzTSinc s

LM

L ==

−−=

+

−

−

+ (4.34)

0 0.2 0.4 0.6 0.8 1-450

-400

-350

-300

-250

-200

-150

-100

-50

0

ω [xπ rad/s]

Mag

nitu

de [

dB]

TSinc Filter Transfer Functions

M = 64, L = 2 M = 64, L = 4

Fig. 4.17: TSinc transfer functions for OSR = 256 with L = 2 and L = 4

Note that the factor M in equation (4.34) is the integer ratio of fs to 8f0. It is important to notify that the impulse response of this filter is finite, implying it is a FIR-type filter. In addiction, all of its impulse response coefficients are symmetric, and thus it is also a linear-phase filter [38].



The reason for choosing to use L+1 of these averaging filters in cascade is similar to the argument that the order of an analogue low-pass filter in an oversampling D/A converter should be higher than the order of the Sigma-Delta modulator. Specifically, the slope of the attenuation for this low pass filter should be greater than the rising quantization noise, so that the resulting noise falls off at a relatively low frequency. Otherwise, the noise would be the integrated over a very large bandwidth usually causing excessive total noise [38]. The Half Band Filter is characterized by the constrains that their passband and stopband ripples are the same (i.e., sp δδ = ) and that the cutoff frequencies are symmetrical around π/2 such that:

πωω =+ sp (4.35)

These properties, illustrated in Fig. 4.18, lead to a family of filters that exhibits odd symmetry around π/2 and

whose impulse response h(n) have zero values for all even values of n except n = 0. Therefore, these filters can be implemented with half the number of multiplications than arbitrary choices of filter designs. They are appropriate for sampling rate conversion ratios 2:1 and are useful for higher rate stages of multirate decimators or interpolators where conversion ratios of 2 occurs in each stage.

Fig. 4.18: Design Criteria for each stage Half Band Filter

The previous Sigma-Delta modulator output decimation processing system depicted on Fig. 4.16 can be

simplified by transforming the last three filter stages into one like depicted on Fig. 4.19 for simulation simplification purposes, where the two previous half filters were converted into a one fourth band filter including the TSinc compensation transfer function.

Fig. 4.19: Simplified Sigma-Delta Modulator Output Decimation Processing System The One Fourth Band Filter is characterized by the constrains that their passband and stopband ripples are the same (i.e., sp δδ = ) and that the cutoff frequencies are symmetrical around π/4 such that:

2πωω =+ sp (4.36)



Fig. 4.20: Design Criteria for the One Fourth Band Filter

As mentioned the One Fourth Band Filter has included into its final transfer function the TSinc Compensation function. On the following Fig. 4.21 it is possible to see the TSinc transfer function frequency response for the case of L = 2 and OSR = 256, as well as the One Fourth Band Filter with TSinc Compensation and the final product of both filter transfer functions at the output of the DSP decimation filter.

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

1.4

ω [xπ rad/s]

Mag

nitu

de

anti-TSinc One Fourth Band FilterTSinc Filter (M = OSR/4)Product

0.24 0.242 0.244 0.246 0.248 0.25 0.252 0.254 0.256 0.258 0.26-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

ω [xπ rad/s]

Mag

nitu

de [

dB]

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-350

-300

-250

-200

-150

-100

-50

0

50

ω [xπ rad/s]

Mag

nitu

de [

dB]



Fig. 4.21: Spectrums from the TSinc Filter (OSR = 256, L = 2), One Fourth Band Filter with TSinc Compensation and

the final product of the transfer functions.



4.5.2 Thermal Noise, Quantization Noise and Oversampling Rate Analysis With the previous simplified Sigma-Delta modulator output decimation processing system, two different simulation structures depicted in Fig. 4.22a and Fig. 4.22b, one applying the high pass Sigma-Delta modulator and the other one applying the band pass Sigma Delta modulator structures were built to find out which is the minimum required oversampling rate that generates a Sigma-Delta modulator output’s spectrum flatten enough to further fulfill the AIS 31 Standard Statistical Tests. It should be noticed as depicted on Fig. 4.22a and Fig. 4.22b that the outputs of the Sigma-Delta modulators must be multiplied by an appropriate sinus signal to modulate the signal Y(z) down to the low frequency baseband of work of the low pass decimation filter system.

Remembering that the proposed work uses the thermal noise to generate random numbers one possible source

comes from the switched-capacitors on the modulator circuit structure. From this physical phenomenon the total thermal noise mean-squared value on a capacitor [48] is calculated as:

CkTV rmsnoise =2

)( , where k is the Boltzmann constant (1.38x10-23 J/K), (4.37)

T is the temperature in Kelvin and C is the capacitor size given in Fahrads. It should be stated that this noise phenomenon for capacitors gives a fundamental limit on the minimum noise level across a capacitor. Thus, to lower the noise level, either the temperature must be lowered or the capacitance value must be increased. In this work instead, as it will be seen further, the thermal noise generated by the switched-capacitor must be as high as possible, but there are some limitations on the capacitor’s size concerning their relation to the flicker noise generated by the switching-transistors. For this actual analysis it will be considered just the thermal noise generated by the switched-capacitors, later the switching-transistors’ flicker noise will be introduced on the model.

Fig. 4.22 Simulation Structures for the Band Pass and High Pass Sigma-Delta Modulator Systems



From equation (4.37) it is possible to conclude that the thermal noise scaling factor on Fig. 4.22 is equivalent to the thermal noise generated by all the capacitors from the first stage of the switched-capacitor Sigma-Delta modulator circuit structure calculated by:

Thermal Noise Scaling Factor CkT= , (4.38)

It should be remembered from Figs. 4.12 and 4.14 and equations (4.31) and (4.33) for the transfer function NTFEt2(z) that the thermal noise generated by the capacitors that belong to the second stage for these Sigma-Delta modulator structures is shaped and is not appropriate to the generation of random numbers. On the other hand that means that the integrating-capacitor’s size on the modulator’s first stage will have a greater influence on the final output spectrum if the same integrating-capacitor size is used for both stages. If necessary the first stage switched-capacitors could be scaled even more down to get a higher non-shaped thermal noise at the output of the modulator. For these first simulations it was considered a temperature of 300 K and a capacitor of the size of 10fF. Later on this work, these two parameters and specially the last one will be modified to analyze their influence on the performance of the final electronic circuit design and over the AIS 31 Standard Statistical Tests results.

Performing some simulations with both Sigma-Delta modulator structures it is possible to see from the decimated output spectra on Fig. 4.23 that oversampling rates greater or equal to 128 generate noise power spectrums that start to approximate to a flatten white noise power spectrum desired for the this application. This happens because at considerable higher oversampling rates the thermal noise turns dominant in the spectrum once the quantization noise is damped and shaped by the Sigma-Delta modulator transfer function to lower magnitudes compared to the thermal noise.

It is also possible to percept that the high pass Sigma-Delta modulator has a slightly advantage over the band

pass Sigma-Delta modulator once the first structure requires a lower oversampling rate to achieve a flat spectrum with a lower order system transfer function which yields to two less operational amplifiers and less additional circuitry on a real system.

To certify this advantage a further AIS 31 Standard Statistical Tests analysis over the generated output bit

stream needs to be performed, but before that there is still open which kind of digital bit stream generator is going to be used after the decimation filter system and how the switching-transistors’ flicker noise influences the AIS 31 Standard Statistical Tests results.

4th Order Band Pass Sigma-Delta Modulator

0 0.2 0.4 0.6 0.8 1-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de [

dB]

OSR =64

Thermal NoiseSigma-Delta Modulator Decimated Output

0 0.2 0.4 0.6 0.8 1-190

-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de [

dB]

OSR =128


0 0.2 0.4 0.6 0.8 1-190

-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de

[dB

]

OSR =256


2nd Order High Pass Sigma-Delta Modulator

0 0.2 0.4 0.6 0.8 1-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de [

dB]

OSR =64


0 0.2 0.4 0.6 0.8 1-200

-190

-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de

[dB

]

OSR =128


0 0.2 0.4 0.6 0.8 1

-200

-190

-180

-170

-160

-150

-140

-130

-120

-110

-100

ω [xπ rad/s]

Mag

nitu

de

[dB

]

OSR =256


Fig. 4.22: Output’s spectra for different oversampling rates using a 4th order Band Pass Sigma-Delta Modulator and a 2nd order High Pass Sigma-Delta Modulator



4.5.3 Choice of the Digital Bit Stream Generator System and Analysis To translate the decimated output signal of the Sigma-Delta modulator ADC into a digital bit stream two digital post-processing system approaches were taken. The first was applying a simple “Zero-Cross Comparator” algorithm to generate the output bit states one and zero, which gives a digital output stream Bit Rate equal to: 02 fBitRate CompatorCrossZero =−− (4.38)

The second approach was using a here named “Gauss Distribution Comparator” algorithm which translates one decimated output sample value into one or more bits depending on how many areas the Gauss distribution of the decimated output signal was divided. In this case the digital output stream Bit Rate would be given by the following equation:

*

20 2,)(log2 +−− Ν∈=== icwherecNforNfBitRate iComparatorDistribGauss (4.39)

Fig. 4.24 shows the definition of parameter N as the number of areas by which the Gauss distribution of the

decimation filter output in subdivided, as well as how the areas are calculated and defined under the same distribution. The coefficients ci are calculated through the Error Gauss Distribution Area Function [73] defined by:

∫ −=x

t dteerf0

22π

(4.40)

It should be noticed that equation (4.40) is twice the integral of the Gauss Distribution function for variation

σ(x) = ½ and mean value Ēx = 0.

By applying just thermal noise at the input of the system depicted on Fig. 4.22 with a oversampling rate set to 256, performing a first set of simulations with a band pass and a second set with a high pass Sigma-Delta modulator ADC using in both the proposed “Gauss Distribution Comparator” algorithm at the output of the decimation filter it has shown that for values of N set from 4 to 262144 all AIS 31 Statistical Standard Tests where fulfilled certifying until this maximum value that the “Gauss Distribution Comparator” algorithm works. That means also that for this upper N limit it would be possible to generate 18 random bits for one decimated output value from the Sigma-Delta modulator ADC.

Greater N values could not be simulated due to the extensive amount of time and computation capacity that it

would take which is beyond the purpose of this work and was left for future studies. Nevertheless this first maximum N value limit shows that these 256 times oversampled with either high pass or band pass Sigma-Delta modulator ADC structures achieve a resolution greater or equal than 18 bits which mainly comes from its high order decimation filter output systems and enables the lost bit rate due to oversampling method to be recovered by applying this algorithm without loss of entropy.

Additionally analysis would be required to measure the upper N value limit, but for simplification purposes

and due to limited amount of time and computing processing capacity further simulations used the “Zero-Cross Comparator” algorithm to generate the digital random bit stream output.

Fig. 4.24: Areas definition on the Gauss Distribution Function for σ = ½ and Ēx = 0 of the output signal from the

DSP Decimation Filter for the cases of N equal to 4 and 8.



4.5.4 Flicker Noise Analysis over AIS 31 Standard Statistical Tests The flicker noise is not a totally modelled phenomenon nonetheless one main physical behaviour that could describe it happens in the interface between the gate oxide and the silicon substrate in a MOSFET. Since the silicon crystal reaches an end at this interface, many dangling bonds appear, giving rise to extra energy states as shown of Fig. 4.25. As charge carriers move at the interface, some are randomly trapped and later released by such energy states, introducing flicker noise in the drain current. In addition to trapping, several other mechanisms are believed to generate flicker noise [4].

Fig. 4.25 Dangling Bonds at the Oxide-Silicon Interface Fig. 4.26 Flicker Noise Spectrum Unlike thermal noise, the average power of flicker noise can not be predicted easily. Depending on the cleanness of the oxide-silicon interface, flicker noise may assume considerably different values and as such varies from one CMOS technology to another. The flicker noise is more easily modelled as a voltage source in series with the transistor’s gate [48] and roughly given by the power spectral density equation (4.42):

( )f

KfWLC

KV flicox

techn

11 2ker

2 =

= (4.42)

Where Ktech is a process-dependent constant of the order of 10-27 V2F for 90nm technology [52 53 54 55 56 57 58 59 60 61], Cox it the capacitance per unit area, W is the width and L the length of the device. As shown in Fig. 4.26 the noise spectral density is inversely proportional to the frequency. For this reason, flicker noise is also called 1/f noise. Equation (4.42) is only an approximation and in reality, the Flicker noise equation is somewhat more complex [4]. The inverse dependence of equation (4.42) on the area of the transistor WL suggests that to decrease flicker noise, the device area must be increased. It is also believed that PMOS devices exhibit less Flicker noise than NMOS transistors because the former carry the holes in a buried channel, i.e., at some distance from oxide-silicon interface. Nonetheless, this difference between PMOS and NMOS transistors is not consistently observed [48]. As shown in Fig 4.26 the Flicker noise has a stronger influence over the low and medium band frequencies which suggests that the high pass Sigma-Delta modulator would return better AIS Standard Statistical Tests results compared to the band pass Sigma Delta modulator structure. To analyze the Flicker noise influence over the Sigma-Delta modulator structure and over the results of AIS 31 Standard Statistical Tests, a flicker filter (-10dB/dec) transfer function was designed and added to the simulation system model depicted on Fig. 4.27 followed by an adjustable Flicker Noise Scaling Factor (Kflicker) parameter that for analyses purposes will be related to a new defined α parameter that represents the ratio between the frequency at which the flicker noise density spectrum magnitude is equal to the thermal noise density spectrum magnitude and half of the desired system sampling frequency. By multiplying half of the system sampling frequency fs by the α parameter one determines the Flicker Noise Corner Frequency of the system. The α and Kflicker parameters are defined on equations (4.42) and (4.43) and graphically shown on Fig. 4.28. For the case in which the thermal and flicker noise densities spectra have the same magnitude for a given α value, as exemplified on Fig. 4.28, it comes to:

1022

1kerker

ker

2ker <<=⇒=⇒= ααα

CkTKff

fK

fCkT

flics

CornerFlic

CornerFlic

flic

s (4.43)



Fig. 4.27 Modified Simulation System Structure for the Band Pass and High Pass Sigma-Delta Modulators including the Thermal & Flicker Noise Sources

Fig. 4.28 Parameter α definition and concept of Flicker Noise Corner Frequency From equations (4.42) and (4.43) it is possible to define a relation between the area of the transistors and the size of the switched-capacitors in use as follow:

102ker <<

=⇒= α

αεεCkT

t

KWLWLC

KK

ox

ro

tech

ox

techflic (4.44)

Where: - Ktech process-dependent constant on the order of 10-27 V2F for the 90nm technology, - εo permeability constant equal to 8.85x10-12 F/m, - εr relative permeability of the material in this 90nm technology equal to 3.9, - tox thickness of the gate dioxide to the channel of the transistor for 90nm technology equal to 1.3nm.

From equation (4.43) for a given parameter α and integrating-capacitor C values it is possible to calculate the Kflicker constant which is defined as the Flicker Noise Scaling Factor on the model of Fig. 4.27 and from there on using equation (4.44) calculate the maximum area of the switching transistors.



Using for simulation time processing reduction the previous defined “Zero-Cross Comparator” algorithm and generating some sets of 6 million output bit streams from the high pass Sigma-Delta modulator ADC system for different α parameter and integrating-capacitor C values it is possible to find out which are the switched-capacitor values that fulfil the complete set of AIS 31 Standard Statistical Tests as well as determines the estimated optimal area of the transistors as shown on Table 4.1 and Fig. 4.30.

Parameter α

C [fF] 0.005 0.002 0.001 0.0005 0.0002 0.0001 100 0 0 0 0 0 0 80 0 0 0 1 1 1 60 0 0 1 1 1 1 40 0 0 1 1 1 1 20 0 0 1 1 1 1

Table 4.1: Fulfilled or not fulfilled complete set of AIS 31 Standard Statistical Tests for different Flicker Noise Corner Frequency α parameter and integrating-capacitor values using the High Pass Sigma-Delta Modulator structure with a

oversampling rate of 256 and system sampling frequency fs of 25MHz From Table 4.1 and equation (4.44) it is possible to find out for different α parameters values the transistor areas for the technology of 90nm as shown in Fig. 4.30 and to calculate the total noise power density spectrum generated by the flicker and thermal noises as depicted on Fig. 4.29 in the case a integrating-capacitor of 25fF is used on the switched-capacitor circuit.

Fig. 4.29 Total [black], Thermal [blue] and Flicker [red] Noise Power Density spectra for a capacitor of 25fF and different Flicker Noise Corner Frequency α parameter values.

From the previous Table 4.1 and Fig. 4.29 it is also possible to predict that the flicker noise will have a much higher influence on the final AIS31 Standard Statistical Tests for the band pass Sigma-Delta modulator that works in a frequency range two times lower than that for the high pass Sigma-Delta modulator structure. Beside this characteristic the band pass Sigma-Delta modulator would use twice operational amplifiers to get a 4th order system which yields to more area, power consumption, flicker noise, time and complexity to design the overall circuit.



Taking into account these observations and from the previous analysis the work is going to be conducted studying the high pass Sigma-Delta modulator topology structure, its design and circuit implementation.

10-4

10-3

10-2

0

100

200

300

400

500

600

700

800

900

1000

WL

/ (W

L α

=0.

1)

α

Normalized Transistor Area versus α parameter | C = 25fF

Fig. 4.30 Normalized Transistors’ Area on 90nm technology for different Flicker Noise Corner Frequency α parameter

values using a capacitor of 25fF Table 4.2 shows the results of AIS 31 Standard Statistical Tests ran over 6 million random bits generated by the high pass Sigma-Delta modulator with integrating capacitor set to 25fF and Flicker Noise Corner Frequency parameter α set to 0.001 using the third order TSinc FIR filter together with the One Fourth Band with TSinc compensation FIR Filter and “Zero-Cross Comparator” algorithm on the system simulation model on Fig. 4.28. As it is possible to see all tests are fulfilled for this case. AIS 31 Standard Statistical Tests Result Limits Test 0 (Disjointness Test) Passed Passed or not Passed Test 1 (Monobit Test) Monobit = 9986 9654 < Monobit < 10346 Test 2 (Pocker Test) Χ = 4.498 1.03 < Χ < 57.4 Test 3 (Run Test) All passed Limits section 3.7 Test 3 Test 4 (Long Run Test) Long Run = 1 Long Run < 34 Test 5 (Autocorrelation) MaxCorr(4075) = 2572 2326 < MaxCorr < 2674 Test 6a (Empirical distribution for 1 disjoint sub-sequences) Χ = 0.001 Χ < 0.025 Test 6b (Emprcl distb 2 disj s-s) Χ = 0.005 Χ < 0.020 Test 7a (Emprcl dstrb 4 disj s-s) Χ2(1) = 5.264 Χ2(1) < 15.3 Test 7a (Emprcl dstrb 4 disj s-s) Χ2(2) = 0.986 Χ2(2) < 15.3 Test 7b (Emprcl dstrb 8 disj s-s) Χ2(1) = 0.648 Χ2(1) < 15.3 Test 7b (Emprcl dstrb 8 disj s-s) Χ2(2) = 0.269 Χ2(2) < 15.3 Test 7b (Emprcl dstrb 8 disj s-s) Χ2(3) = 6.228 Χ2(3) < 15.3 Test 7b (Emprcl dstrb 8 disj s-s) Χ2(4) = 0.925 Χ2(4) < 15.3 Test 8 (Strong Entropy) SE = 369.339 SE > 7.976 Table 4.2: Fulfilment of all AIS 31 Standard Statistical Tests for α = 0.001 and integrating capacitor set to 25fF on the

High Pass Sigma-Delta Modulator with a oversampling rate of 256 and system sampling frequency fs of 25MHz



5. High Pass Sigma-Delta Modulator System Level Design 5.1 Switched-Capacitor High Pass Sigma-Delta Modulator Circuit Realization The Classic Basic High Pass Sigma-Delta Modulator Cell Circuit Structure From the previous analysis on section 4.4 the basic transfer function cell to implement a High Pass Sigma-Delta Modulator is given by:

1

1

1)( −

−

+−=

zzzH (5.1)

From [38] the following circuit on Fig. 5.1 gives a similar transfer function for the Low Pass Sigma-Delta Modulator structure that needs to be modified on its pole for the new implementation as a High Pass version:

Fig. 5.1: Basic Low Pass Sigma-Delta Modulator Cell Circuit structure The actual Basic Low Pass Sigma-Delta Cell transfer function is given by:

−

−= −

−1

1

11

21

)()(

zz

CC

zVizVo

(5.2)

For C1 = C2 this system can be modelled as depicted on Fig. 5.2:

Fig 5.2: Basic Low Pass Sigma-Delta Modulator Cell Model

Which has the transfer function given by:

1

1

1)()(

−

−

−−=

zz

zUzY

(5.3)

If instead of taking the positive feedback from the output someone takes the negative one, the new system will

have a high pass behaviour as given by equation (5.4) and modeled by Fig. 5.3.



1

1

1)()(

−

−

+−=

zz

zUzY

(5.4)

Then rewriting the equation (5.2) to:

)(1)(2)(2)(1)(2)(2 11 TnTViCTnTVoCnTVoCzzViCzzVoCzVoC −−=−−⇒−=− −−

And taking the negative value of Vo(nT-T) from the capacitor C2 the final expression would then be:

11 )(1)(2)(2)(1)(2)(2 −− −=+⇒−−=−+ zzViCzzVoCzVoCTnTViCTnTVoCnTVoC

Fig 5.3: Basic high pass Sigma-Delta modulator cell model That would yield to the desired expression on equation 5.1 when C1 = C2. The idea is then to design a circuit which takes the negative value of the last integration stored on the capacitor C2. One possible structure that can execute such action using known circuits from [38] is given on Fig. 5.5 as well as the related circuit analysis and transfer function given on Fig 5.4 and equation (5.5).

Fig. 5.4: Basic High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analyze



Fig. 5.5: Basic High Pass Sigma-Delta Modulator Cell Structure From Fig. 5.5 the following difference-equation system analysis can be done:

)(4)2

(4

)(2)2

(2

431

)2

(4()(1)2

(2

nTVoCTnTVoC

TnTVoCTnTVoC

CCC

TnTVoCnTViCTnTVoC

−=−−

+=+

==

−−++=+

Thus:

)(1)1)((2))(4()(1)(2

nTViCzzVoCnTVoCnTViCTnTVoC

=+−++=+

This results into the following transfer function for the basic high pass cell given by:

+= −

−1

1

11

21

)()(

zz

CC

zVizVo

(5.5)

The Classic Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit Using the classic basic cell from Fig. 5.5 the following switched-capacitor circuit can be designed to implement a 2nd order high pass Sigma-Delta modulator circuit as shown in Fig. 5.7. The same circuit has the equivalent model as the structure depicted on Fig. 5.6.

Fig. 5.6 The classic 2nd Order High Pass Sigma-Delta Modulator Model.



It should be noticed that the equation (5.5) does not have a signal phase shift of 180˚ from the input to the

output which will result on the required wiring cross connection from the first to the second stages on the Sigma-Delta modulator circuit on Fig. 5.7 as well as the crossing of the input stage on the modulator which in this case is not necessary and independent of the input signal polarization.

Another observation that should be taken into account is that on the same switched-circuit both operational

amplifiers and comparator are ideal models with high gain, infinite bandwidth and high slew rate characteristics for execution of first circuit simulations. Through simulation of the discrete-time model on Fig. 5.6 and simulation of the switching-capacitor circuit model on Fig. 5.7 it is possible to validate the circuit and its functionality as shown in Fig. 5.8 where on the upper graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view of the high pass output baseband spectrum are shown. As it can be seen on Fig. 5.7 this switching-circuit requires at least 22 switched-capacitors and enhanced current driving operational amplifier outputs, especially the first stage which outputs have 3 capacitors to drive per output. This circuit needs four distinguished clock signals to work compared to a classical 2nd second order low pass Sigma-Delta modulator version which has just two clocks. There are visible some possible modifications that could reduce the number of the switching gates on the circuit, but looking carefully again to some of the previous difference-equations a reduced and simplified version of the circuit can be designed.

Fig. 5.7 Classic 2nd Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-150

-100

-50

0Spectral Comparation Classic 2nd Ord High Pass SDM | OSR = 256

ω [xπ rad/s]

Am

plit

ude

[dB

]

0.993 0.994 0.995 0.996 0.997 0.998 0.999 1-150

-100

-50

0Spectral Comparation at the Baseband Classic 2nd Ord High Pass SDM | OSR = 256

ω [xπ rad/s]

Am

plitu

de

[dB

]

Discrete-Time System ModelSwitched-Capacitor Circuit

Fig. 5.8 Spectral simulation results for the classic 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor

circuit with a differential sinusoidal input signal of 0.25Vpp (-12dB) at the frequency of (0.998π) rads/s and OSR = 256.

The Reduced Basic High Pass Sigma-Delta Modulator Cell Circuit Structure Another possible circuit structure that realizes the same basic cell transfer function from equation (5.1) with less transistors and capacitors is depicted in Fig. 5.9 and analyzed on Fig. 5.10:

Fig. 5.9: Reduced basic High Pass Sigma-Delta Modulator Cell Structure



Fig. 5.10: Reduced High Pass Sigma-Delta Modulator Basic Cell Structure Circuit Analysis

From the analysis on Fig 5.10 the resulting transfer function for this basic structure is:

+−= −

−1

1

11

21

)()(

zz

CC

zVizVo

(5.4)

With the same analysis used on the first structure on Fig. 5.10 it is also possible to derive more two other structures as given in Fig. 5.11 as well as their corresponding transfer functions:



Fig. 5.11: Reduced basic High Pass Sigma-Delta Modulator Cell Structures with different transfer functions The Reduced Second Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit Using the reduced basic cell structure from Fig. 5.11a the following switched-capacitor circuit can be designed to implement a 2nd order high pass Sigma-Delta modulator circuit as shown in Fig. 5.12. The same circuit has the equivalent model as the structure depicted on Fig. 5.6. Through simulation of both models it is possible to check the validation of the circuit and its functionality as shown if Fig. 5.13.

Fig. 5.12 Reduced 2nd Order High Pass Sigma-Delta Modulator Switching-Capacitor Circuit



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-150

-100

-50

0Spectral Comparation Reduced 2nd Ord High Pass SDM | OSR = 256

ω [xπ rad/s]

Am

plit

ude

[dB

]

0.993 0.994 0.995 0.996 0.997 0.998 0.999 1-150

-100

-50

0Spectral Comparation at the Baseband Reduced 2nd Ord High Pass SDM | OSR = 256

ω [xπ rad/s]

Am

plitu

de [d

B]

Discrete-Time System ModelSwitched-Capacitor Circuit

Fig. 5.13 Spectral simulation results for the reduced 2nd Order High Pass Sigma-Delta Modulator Switched-Capacitor Circuit with a differential sinus input signal of 0.25Vpp (-12dB) at the frequency of (0.998π) rads/s with OSR = 256. Through simulation of the discrete-time model on Fig. 5.6 and simulation of the switched-capacitor circuit model on Fig. 5.12 it is possible to validate the circuit and its functionality as shown in Fig. 5.13 where on the upper graphic a high pass transfer function behaviour of the output spectrum and on the graphic below a detailed insight view of the high pass output baseband spectrum are shown. As it can be seen on Fig. 5.12 this switching-circuit requires 50% less switched-capacitors compared to the previous version and operational amplifier’s outputs with less driving strength. The only drawback is that it still requires four distinguished clock signals to work compared to a classical 2nd order low pass Sigma-Delta modulator version which has just two clocks, required is this new structure due to the polarization switching behaviour on the integrating capacitors to get a high pass transfer function of the reduced basic cells. From both analyzed switching-circuits it is evident the advantage of the reduced version which is going to be used at analysis for the determination on further components requirements. However, it should be noticed that one possible disadvantage of this reduced structure could arise from the parasitic capacitance on the switched integrating-capacitor which is not built as in the conventional layout structure as on the classic structure. This circuit characteristic will be analyzed more carefully on the coming section. 6. Requirements for the Different Components of the Analog Circuit System 6.1 Switched-Capacitor Circuit Requirements Differential Sinusoidal Input Signal Amplitude Influence Analysis One factor that should be taken into account is the need or not for a differential sinusoidal input signal at the frequency of π/2 rad/s for a better shape on the final output spectrum and its influence on the SNDR curves for different amplitude values. For this purpose, through some simulations using the equivalent discrete-time system model from Fig. 5.6, the following SNDR curve depicted on Fig. 6.1 was calculated.

Applying two differential sinusoidal signals at the input of the circuit, one signal named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude changing from 0.00Vpp to 1.00Vpp and the other one called Vin0.998π with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinus signal at the output results on the following left SNDR curves depicted on Fig. 6.1 for a oversampling rate of 256.



As it is possible to see on the right SNDR versus Vinπ/2 curve on Fig. 6.1, there is no influence of Vinπ/2, the differential sinusoidal input signal amplitude at the frequency of π/2 rad/s, on the final SNDR curve, which suggests that the system input path could be probably taken out from the final circuit topology depicted on Fig. 5.12. However, due to initial conditions on the circuit structure on Fig. 5.12 this input path should be implemented to start-up the Sigma-Delta modulator circuit at initial power on conditions and to result on a better spectrum shape and decorrelation of the output of the Sigma-Delta modulator ADC.

-50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNDR HPSDM 2nd Order | OSR =256 | Diff Vinπ/2

Vin0.998π [dB]

SN

DR

[d

B]

0 0.2 0.4 0.6 0.8 10

20

40

60

80

100

120

Vinπ/2 [V] | Vin0.998π = -6 dB

SN

DR

[d

B]

SNDR HPSDM 2nd Order | OSR =256 | Diff Vinπ/2

0.00 Vpp0.25 Vpp0.50 Vpp0.75 Vpp1.00 Vpp

Fig. 6.1 SNDR for different amplitudes of the differential sinus input signal at the frequency of π/2 for the 2nd Order

High Pass Sigma-Delta Modulator Circuit Switched-Capacitor Coefficients Scaling Analysis Concerning the power source and reference voltages on which the switched-capacitor circuit will be implemented later, a scaling factor should be applied over the capacitor values to limit the internal operational amplifier output signals to the reference voltages of the circuit. To find out the scaling factors that should be used the following 2nd order high pass Sigma-Delta modulator system shown in Fig. 6.2 can be modeled to later apply the scaling factors over the capacitors on the switched-capacitor circuit for the high pass Sigma-Delta modulator circuit from Fig. 5.12.

Fig. 6.2 System model of 2nd Order High Pass Sigma-Delta Modulator with scaling factors



Defining two parameters γ and β it is possible to control the values for the k parameters of the given system through following relations:

K11 = γ k12 = 1 k13 = γ k21 = β / γ k22 = 1 k23 = β (6.1) By setting γ = 1/3.5 and β = 1/6.5 and applying a differential sinus signal input of -3dB at the frequency 0.998π

rad/s the signals o1 and o2 are scaled as depicted on Fig. 6.3:

0 1 2 3 4 5 6 7 8 9 10

x 105

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Scaled HPSDM 2nd Ord - o1 Signal

Mag

nitu

de

[V]

[s]

0 1 2 3 4 5 6 7 8 9 10

x 105

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Scaled HPSDM 2nd Ord - o2 Signal

Mag

nitu

de [

V]

[s]

Fig: 6.3 Signals o1 and o2 from 2nd Order High Pass Sigma-Delta Modulator of Fig. 6.5

From Fig. 6.3 it is possible to see that the signals o1 and o2 are within the reference voltages Vref+ = +1.00V and Vref- = -1.00 V in the model. Just to notice, these scaling factor values will be applied over the capacitor values from the switched-capacitor circuit from Fig. 5.12 later on the transistor circuit level design. In addiction to that, it should be reinforced that for this scaling method the parameters k12 and k22 do not need to be scaled and remain unchanged as well as their corresponding integrating-capacitors on the circuit on Fig. 5.12. Switched-Capacitor Parasitic Capacitance Analysis Contrary to classical switched-capacitor circuits where sensitive capacitor nodes are placed always on the top plate, resulting into low parasites the proposed reduced modulator structure uses integrating-capacitors with changing polarity where this is not possible. Due to this fact and due to the existence of intrinsic parasitic capacitances from the switched-capacitor top and bottom plates a set of simulations including parasitic capacitances in the circuit structure of Fig. 6.4 were performed to check the influences and quantify the minimum tolerance required to achieve a SNDR curve as close as possible to the theoretical SNDR curve of the high pass Sigma-Delta modulator on Fig. 4.15. The top parasitic capacitor was disconsidered, due to its little parasitic influence on the capacitor value and the bottom parasitic capacitor was scaled to 0.3%, 0.5%, 0.7%, 1%, 2% and 5% of the correspondent capacitor value. Applying two differential sinusoidal input signals, one named Vinπ/2 at the frequency of π/2 rad/s with differential amplitude of 0.5Vpp and the second differential sinusoidal input signal called Vin0.998π at the frequency of 0.998π rad/s with differential amplitude ranging from -48 to -3 dB the following left SNDR curves shown on Fig. 6.5 were calculate for these different parasitic scaling factors for an OSR equal to 256. From the right SNDR versus Bottom Parasitic Capacitor curve on Fig. 6.5 the bottom parasitic capacitance should then have a parasitic value lower than 1% to achieve the desired theoretical SNDR curve from Fig. 4.15. From previous works and layout methodologies it is possible to achieve such tolerance values [62 63 64 65 66].



Fig. 6.4 2nd Order High Pass Sigma-Delta Modulator switching-capacitor circuit including the top and bottom parasitic capacitances from the switched-capacitor plates

-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics

Vin0.998π [dB] | Vinπ/2 = 0.5V

SN

DR

[dB

]

5.0%2.0%1.0%0.7%0.5%0.3%

0 1 2 3 4 50

20

40

60

80

100

120

SN

DR

[dB

]

Bottom Cap Parasitic [%] | Vin0.998π = -6dB

SNR HPSDM 2nd Ord | OSR = 256 | Diff Bottom Cap Parasitics

Fig. 6.5 SNDR for different bottom capacitor parasitic tolerances on the 2nd High Pass Sigma-Delta Modulator Circuit



6.2 Operational Amplifier Requirements Operational Amplifier Gain Analysis With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its minimum gain must be analyzed to achieve a SNDR curve close to the theoretical one from Fig. 4.15. Implementing the circuit shown in Fig. 5.12 and modeling the operational amplifier like depicted on Fig. 6.6 a set of circuit simulations and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig. 6.7. Note that for this first operational amplifier’s characteristic estimation the frequency bandwidth is not modeled and is considered infinite.

Fig. 6.6 Operational amplifier with gain modelling for PSPICE simulations

-50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNDR Simulink Scaled HPSDM 2nd Ord | Vinπ/2 = 0.5Vpp | Diff OpAmp Gain

Vin0.998π [dB]

SN

DR

[d

B]

0 10 20 30 40 50 60 70 800

20

40

60

80

100

120

SN

DR

[d

B]

Gain [dB] | Vin0.998π = -6 dB

SNDR Simulink Scaled HPSDM 2nd Ord | Vinπ/2 = 0.5Vpp | Diff OpAmp Gain

G = 74dBG = 66dBG = 60dBG = 54dBG = 46dBG = 40dBG = 34dBG = 26dBG = 20dBG = 14dBG = 6dBG = 0dB

Fig. 6.7: SNDR for different operational amplifier gains on the 2nd Order High Pass Sigma-Delta Modulator Circuit

By giving different gain values and applying two differential sinusoidal signals at the input of the circuit, one

named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude 0.5V and another one called Vin0.998π with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig. 6.8 for an oversampling rate of 256. As it possible to see from the right SNDR versus Gain curve on Fig. 6.8 the minimum required operational amplifier gain should be greater than 40dB.



Operational Amplifier Input Capacitance Analysis With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its maximum input capacitance requirements must be analyzed to achieve a SNDR curve close to the theoretical one from Fig. 4.15.

Implementing the circuit shown in Fig. 5.12, scaling the input and feedback circuit paths with the corresponding scaling factors calculated on the previous section 6.2 and connecting to each of the two operational amplifier’s signal inputs a capacitor, a set of circuit simulations with different values for this input capacitor and further SNDR calculations where performed resulting on the following SNDR curves given on Fig. 6.8. Note that for the estimation of the operational amplifier input capacitance its gain was set to 40dB from the minimum established from last analysis and its frequency bandwidth is considered infinite.

By giving different operational amplifier input capacitance values ranging from 0.20 to 5.00 times the value of the integrating-capacitor, applying two differential sinusoidal signals at the input of the circuit, one named Vinπ/2 with a frequency exactly on π/2 rad/s and with a differential amplitude of 0.5Vpp, another one called Vin0.998π with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the left SNDR curves depicted on Fig. 6.9 for a oversampling rate of 256. From the right SNDR versus Input Capacitance curve on Fig. 6.9 it is possible to percept that for an input capacitance value of the same other or lower than the integrating capacitor value it is possible to achieve a SNDR curve close to the theoretical one on Fig. 4.15. It means that the input capacitance of the individual operational amplifier inputs should be maximum of the order or lower than the integrating-capacitor value that will be used on the final circuit.

-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNDR HPSDM 2nd Ord | OSR = 256 | Diff CinOpAmp

Vin0.998π [dB] | Vinπ/2 = 0.0V

SN

DR

[dB

]

0 1 2 3 4 50

20

40

60

80

100

120

SN

DR

[dB

]

(CinOpAmp/Ci) [fF] | Vin0.998π = -3dB

SNDR HPSDM 2nd Ord | OSR = 256 | Diff CinOpAmp

5.00 x Ci2.00 x Ci1.00 x Ci0.50 x Ci0.20 x Ci

Fig. 6.8: SNDR for different operational amplifier’s input capacitance values on the 2nd Order High Pass Sigma-Delta

Modulator Circuit



Operational Amplifier Bandwidth Analysis With the previous circuit topology from Fig. 5.12 some operational amplifier characteristics concerning its bandwidth must also be analyzed to achieve a SNDR curve close to the theoretical one from Fig. 4.15. Implementing the circuit shown in Fig. 5.12 and modelling the operational amplifier like depicted on Fig. 6.9 a set of circuit simulations and further SNDR calculations where performed resulting on the following left SNDR curves given on Fig. 6.12.

Fig. 6.9 Operational amplifier with frequency bandwidth modelling for simulations

From circuit in Fig. 6.10 it is possible to find out the relation between the -3dB gain frequency and the 0dB

gain frequency for an amplifier with a RC low pass filter at its output:

Fig 6.10 Operational amplifier with a low pass filter at the output circuit modelling

22

2

22

22

)(1)()(

=

+=

RCwG

wVinwVout

(6.1)

1,23 >>=− Gfor

RCGf dB π

(6.2)

The same can be found for the 0dB frequency:

( )2

2

2

22

1)(1)(

)( =

+=

RCwG

wVinwVout

(6.3)

1,20 >>= Gfor

RCGf dB π

(6.4)

From equations (6.2) and (6.4) it is possible to find the relation:

dBdB ff 03 2=− (6.5) It should be noticed that for the purpose of the simulations the gain in the voltage gain source model in Fig. 6.9

are set to 5000 (74dB) which is enough given the SNDR versus Gain curve on Fig. 6.2. The value of the resistor R is given by equation (6.6):



dBfCR

0

1500022

1 ×××=π

(6.6)

The parameter R on the model on Fig 6.9 is then related through equation (6.6) to the 0dB gain frequency of

the operational amplifier for a given capacitor value C on this simulation set on 1nF. By specifying different R values and applying two differential sinusoidal signals at the input of the circuit, one named Vinπ/2 with a frequency exactly on π/2 rad/s and with differential amplitude of 0.5Vpp and the other one called Vin0.998π with a frequency of 0.998π rad/s and varying its differential amplitude from -48dB to 0dB and calculating the SNDR for this last sinusoidal signal at the output of the system results on the following left SNDR curves depicted on Fig. 6.11 for a oversampling rate of 256.

As it possible to see from the right SNDR versus f0dB curve on Fig. 6.11 the minimum required operational amplifier 0dB gain frequency, f0dB, should be greater than 4 times the sampling frequency fs in use on the system.

-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp f0dB

Vin0.998π [dB] | Vinπ/2 = 0.5V

SN

DR

[dB

]

0 2 4 6 8 10 12 14 160

20

40

60

80

100

120

SN

DR

[dB

]

(f0dB/fs) | Vin0.998π = -6dB

SNDR HPSDM 2nd Ord | OSR = 256 | Op Amp f0dB

16 x f0dB/fs12 x f0dB/fs8 x f0dB/fs4 x f0dB/fs3 x f0dB/fs2 x f0dB/fs1 x f0dB/fs

Fig. 6.11: SNDR for different f0dB values of the operational amplifier on the 2nd Order High Pass Sigma-Delta

Modulator Circuit 6.3 Comparator Requirements Comparator Offset Analysis With the same idea of the operational amplifier requirement analysis the comparator should be checked for its offset influence over the SNDR curve. Using the scaled model of Fig. 6.3 and setting different switching voltage values for the comparator (1-bit A/D Converter) the following SNDR curves result as depicted on left Fig. 6.12. From the right SNDR versus Offset curve on Fig. 6.12 it is possible to see that for an offset voltage value ranging from -50mV to 50mV the SNDR curve achieves the desired values compared to the theoretical one from Fig. 4.15 for OSR equal 256. Comparator Hysteresis Analysis The comparator should also be checked for its hysteresis influence over the SNDR curve. Using the scaled model of Fig. 6.3 and setting different switching value points for a hypothetical symmetrical comparator’s hysteresis curve the following left SNDR curves result as depicted on Fig. 6.13. From the right SNDR versus Hysteresis Switching Point curve on Fig. 6.13 it is possible to observe that for hysteresis symmetrical switching voltage values lower than |100mV| the SNDR curve achieves the desired values compared to the theoretical one from Fig. 4.15 for OSR equal 256.



-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNR HPSDM 2nd Ord | Vπ/2 = 0.5V | Diff Offset Comp

V0.998π [dB]

SN

DR

[dB

]

-0.90-0.70-0.50-0.20-0.10-0.05-0.020.00+0.02+0.05+0.10+0.20+0.50+0.70+0.90

-1 -0.5 0 0.5 10

20

40

60

80

100

120

Offset [V] | V0.998π = -21 dB

SN

DR

[dB

]

SNR HPSDM 2nd Ord | Vπ/2 = 0.5V | Diff Offset Comp

Fig. 6.12 SNDR for different comparator’s offset switching voltage values on the 2nd Order High Pass Sigma-Delta Modulator Circuit

-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120

SNR HPSDM 2nd Ord | Vπ/2 = 0.5V | Diff Histeresis Comp

V0.998π [dB]

SN

DR

[dB

]

0.00+0.01+0.02+0.05+0.10+0.20+0.50+0.90

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

20

40

60

80

100

120

Hysteresis Switchting Point [V] | V0.998π = -21 dB

SNR HPSDM 2nd Ord | Vπ/2 = 0.5V | Diff Histeresis Comp

Fig. 6.13 SNDR for different comparator’s symmetrical hysteresis witching voltage values on the 2nd Order High Pass

Sigma-Delta Modulator Circuit



7. Analog Components Circuit Design 7.1 Operational Amplifier Transistor Circuit Design Having in mind that the main application of this TRNG with a Sigma-Delta modulator ADC is oriented to low power and restricted area on die applications, it should be established a sampling frequency that fulfils the usually necessary random bit stream rates and leaves a big security margin concerning to influences of the flicker noise of the switching-transistors over the AIS Standard Statistical Test results. It should also be remembered that if needed the random bit stream rate could be increased by applying the “Gauss Distribution Comparator” algorithm as mentioned before. For the purpose of this work it was considered a sampling frequency of 25MHz which translates to an output random bit stream close to 100k bits/s with a clock signal waveform drawn as it follows on Fig. 7.1.

Fig. 7.1 Signal “o” sampling frequency clock waveform

From previous section 4.5.4 concerning the thermal and flicker noise analysis the integrating-capacitor value

for the switching-circuit design should lay between 20fF to 60fF and in this case was chosen to be 25fF which imposes some additional characteristics and limits that the operational amplifier, comparator and transmission gate need to satisfy to allow the proper operation of the system.

Using the parameters on Fig. 7.1 it is possible to calculate the required minimal output driving current of the operational amplifier if it is taken into account that it needs to drive at least 750fF of capacitive load at each of its outputs as it is possible to see from the switched-capacitor circuit in Fig. 5.12 once the scaling factor are properly applied for the chosen integrating-capacitor value and taking also into account the capacitors of the common-mode feedback control circuit in the operational amplifier output stage. For the 90nm MOS technology in use the nominal Vss to Vdd source voltage is 1.20V which follows to a minimal output driving current given by:

)(5

51

)( VssVddfCT

VssVddCdtdVCIout sloadloadload −×××=−=> (7.1)

As stated on equation (7.1) if it is taken into account that the sampled voltage needs to reach its 100% value in one fifth of the sampling period time and additionally applying a security factor of 2 times then it comes to a minimum required driving current Iout of 225uA.

The second important factor to be taken in account is the operational amplifier input capacitance which for a differential MOS pair input is mainly given by the size of the differential input pair transistors. From previous section 6.2 it was mentioned that the operational amplifier input capacitance should be equal or less than the integrating capacitor value. In this design, the integrating capacitor was established to 25fF then the simulation measured operational amplifier input capacitance should be equal or lower than this value. From the previously determined requirements the following operational amplifier circuit with bias and additional common-mode feedback control (CMFB) circuit was designed as depicted on Fig. 7.2 and Fig. 7.3. As shown on Figs. 7.4 and 7.5 through CADENCE Spectre small-signal AC and large-signal DC simulation analysis the circuit satisfies the previous determined operational amplifier requirements for nominal conditions (Vdd-Vss = 1.20V, Temperature = 27 °C) as stated on Table 7.1:

Parameter Simulated Required Limit DC Gain 43dB DC Gain>40dB f0dB 182MHz f0dB/fs>4, fs=25MHz Phase Margin 70° Phase Margin > 50° Iout 300uA Iout>=225uA Cin 4fF Cin≤25fF

Table 7.1: Operational amplifier simulated and required parameters



Fig. 7.2 Operational Amplifier Transistor Circuit Design

As it is possible to observe on Fig. 7.2 the operational amplifier is built on two amplification stages: the first stage being a folded-cascode circuit composed by the biasing current-mirrored transistors Q6, Q10 and Q11, differential input pair Q7 and Q8, cascode transistors Q12 and Q13 and by the folded transistors Q14 and Q15. The second stage being composed by two common-source circuits through transistors Q18 and Q19 and biasing transistors Q16 and Q17. Additionally there is a simple current mirror biasing circuit composed by transistors Q1, Q2, Q3, Q4 and Q5. It should be noticed that transistors Q7 and Q8 must be reduced on area size as much as possible to reduce the input capacitance of the operational amplifier’s input, the drawback is that they have a strong contribution on the first stage folded-cascode amplification which for this configuration achieves less than 10dB gain, for that reason a second amplification stage was added to achieve an overall gain higher than the required 40dB and that could drive at least 300uA at each output. To satisfy the required phase margin additionally phase compensation capacitors C1 and C2 were inserted between the input and output of the second stage as seen on the circuit.

When using fully-differential operational amplifiers in a feedback application, the applied feedback determines the differential signal voltages, but does not affect the common-mode voltages. It is therefore necessary to add additional circuitry to determine the output common-mode voltage and to control it to be equal the halfway between the power-supply voltages. The circuit that does this functionality on the operational amplifier circuit is the common-mode feedback circuit (CMFB) given on Fig. 7.3 [49 50]. In this circuit, capacitors named Cc generate the average of the output voltages, which is used to create control voltages for the operational amplifier current sources. The DC voltage across Cc is determined by capacitors Cs, which are switched between bias voltages and between being the parallel with Cc. This circuit behaves like a switched-capacitor low-pass filter having a DC input signal. The bias voltage is designed to be equal to the difference between the desired common-mode voltage and the desired control voltage used for the operational amplifier current sources [38].



The capacitors labelled Cs should be between one-quarter the sizes of the non-switched capacitors Cc. Due to the fact that the operational amplifiers’ outputs need to drive at least 225uA each, a high capacitor value is necessary on the CMFB circuit, but using a larger capacitance value overloads the operational amplifier more than necessary during the “e” clock phase. Reducing the capacitor too much causes common-mode offset voltages due to charge injection of the switches [38] and additionally by reducing the capacitor too much it creates a possible capacitor voltage-divider between the parasitic capacitance of transistors Q16 and Q17 and their correspondents Cc capacitors on the CMFB circuit structure which also yields to common-mode offset voltages. There is an optimum value which for this circuit was achieved after some circuit simulations and controllability performance verification of the common-mode feedback circuit yielding to the capacitor values given on the circuit depicted on Fig. 7.3.

Fig. 7.3 Operational Amplifier Transistor Common Feedback Circuit Design

The final phase and gain small-signal AC circuit simulation for this operational amplifier configuration can be seen on Fig. 7.4 which returns the DC Gain, f0dB and Phase Margin parameters given on Table 7.1 fulfilling the previous determined requirements for each one. The large-signal DC Vin Sweep analysis depicted on Fig. 7.5 shows the voltage swing of the internal signals “int_outp” and “int_outn” relative to the first amplification stage of the circuit of Fig. 7.2 as well as the voltage swing of the operational amplifier output signals “outp” and “outn” which saturation limits comply with the maximum and minimum values of the previous scaled output signals “o1” and “o2” from Fig. 6.3. Additionally to these nominal condition simulations a set of Monte-Carlo circuit simulations were performed to check out the robustness and tolerance of the designed operational amplifier to temperature, power-source voltage, process fabrication and mismatch variations as well as to measure the distributions of parameters DC Gain, f0dB and Phase Margin and yield fabrication of the operational amplifier circuit. For these Monte Carlo simulations there were taken into account statistical models for process fabrication and mismatch variations on the 90nm MOS technology used by the CADENCE Spectre [73] simulation CAD tool. For each temperature there were simulated three different power-source voltages and the respective distributions of the parameters DC Gain, f0dB and Phase Margin shown on Figs. 7.6, 7.7 and 7.8.



Fig. 7.4 Operational amplifier CADENCE Spectre small-signal AC gain and phase analysis

Fig. 7.5 Operational amplifier CADENCE Spectre large-signal DC Vin Sweep analysis



Fig. 7.6 Operational amplifier Monte Carlo phase margin, DC gain and f0dB histograms for different power supply voltages at the temperature of -40°C

Fig. 7.7 Operational Amplifier Monte Carlo phase margin, DC gain and f0dB histograms for different power supply voltages at the temperature of +27°C



Fig. 7.8 Operational Amplifier Monte Carlo phase margin, DC gain and f0dB histograms for different power supply voltages at the temperature of +100°C

As it can be seen on Figs. 7.6, 7.7 and 7.8 the chosen temperatures are -40°C, +27°C and +100°C, two extreme environment temperatures and one ambient temperature. For the power-supply voltage it was considered a tolerance of +/- 10% over the nominal value of 1.20V taken into account possible variations of such order for the kind of application where this system could be applied. From the right distribution curves on Figs. 7.6, 7.7 and 7.8 it is possible to observe that the f0dB parameter fulfils in 95% of the cases its minimum allowed value of 4fs with fs equal to 25MHz for any temperature and power-supply voltage and that the higher the temperature the lower gets the distribution mean value and more narrowed becomes the distribution curve for different power-supply voltages. Looking at the middle distribution curves on Figs. 7.6, 7.7 it shows that the DC Gain parameter fulfils on at least 85% of the cases its minimum required value of 40dB having just a low performance of 60% on the case for the extreme temperature of +100°C like depicted on the middle distribution curve on Fig. 7.8. It is also possible to see that the distribution mean value keeps relative constant as well as the distribution curve keeps the same wide spreading under different temperature and power-source voltage conditions. Finally at the left distribution curves on Fig. 7.7 and 7.8 it is also possible to see that the Phase Margin parameter fulfils on at least 82% of the cases the minimum required value of 50° having just a low performance of 40% on the case of extreme low temperature of -40°C like depicted on the middle distribution curve on Fig. 7.6. It it also possible to observe that the higher the temperature the higher gets the distribution mean value and more narrowed becomes the distribution curve for different power-supply voltages. From these distribution curves some improvements should be done on the design of the operational amplifier circuit, but that would take more time on its design and due to the lack of time and considering that for the nominal conditions the current design has an average simulation process yield higher than 80% it was decided to keep using it as it is and further works could improve it if stronger requirements are imposed on the environment temperature that such application would be used.



7.2 Comparator Transistor Circuit Design From the previously determined requirements the following comparator circuit was designed as depicted on Fig. 7.9. As it is possible to see the comparator is built on two stages: the first being a clocked differential pair amplifier composed by transistor Q1 to Q10 and the second a NAND based SR latch composed by transistor Q11 to Q22.

Fig. 7.9 Comparator Circuit Design Performing a large-signal DC Vin Sweep CADENCE Spectre circuit simulation of the circuit the following hysteresis curve for the comparator output under nominal temperature and power-source conditions was taken depicted on Fig. 7.10. The comparator fulfils its requirements with hysteresis symmetrical switching value between -100mV to 100mV.

Fig. 7.10 Comparator Hysteresis Curve

The offset voltage is possible to estimate if we take into account that the threshold voltage mismatch σ∆Vt of a transistor pair is proportional to the inverse of the square root of the active device area with the matching parameter A∆Vt [67 68 69 70]:

WL

A VtVt

∆∆ =σ (7.2)

Taken from the reference [67] that A∆Vt is estimated to be around 3mVµm for the 90nm CMOS technology then using the input pair transistors’ size, it is possible to calculate that the comparator’s offset will be between -11mV to 11mV which is in compliance to the previous determined offset limits for the comparator between -50mV and 50mV.



7.3 Transmission-Gate Transistor Circuit Design To design the transmission-gate it should be remembered from section 7.1 that the switched-capacitors drive currents of the maximum order of 300uA from the operational amplifier. Establishing that the sampled voltage on the integrating switched-capacitor should achieve 100% of its magnitude before one-fourth the system’s sampling period the transmission-gate on resistance should then be lower than:

sonson Cf

RTCR10

1215 <⇒< (7.2)

This gives a transmission gate on resistance of maximum 160kΩ for an integrating switched-capacitor of 25fF and system sampling frequency of 25MHz. Besides this requirement, the switching transistors should have an area that reduces as much as possible the flicker noise of the system. Through CADENCE Spectre [73] circuit simulation the designed transmission-gate depicted on Fig. 7.11 gives a maximum on resistance of 6.3kΩ as shown on Fig. 7.12 and a transistor area of 51200 nm2 which fulfils the desired Flicker Noise Corner frequency from Fig. 4.30 if it is considered that the Flicker Noise Corner Frequency is 1000 times smaller than half the system sampling frequency.

Fig. 7.11 Transmission Gate Transistor Circuit Design

Fig. 7.12 Transmission Gate Active On Resistance



8. TRNG with a Sigma-Delta Modulator ADC Transistor Circuit Design, Simulation & Analysis Once designed all basic analog components circuits the following switched-capacitor Sigma-Delta modulator was built as depicted on Fig. 8.1 with corresponding clock signals given on Fig. 8.2.

Fig. 8.1 Switched-Capacitor Sigma-Delta Modulator Circuit Design

Fig. 8.2 Clock Signals for the Switched-Capacitor Transistor Circuit Design Using the Input Circuit on Fig. 8.3a with the circuit on Fig. 8.1 to reduce computation for first simulations some CADENCE Spectre [73] transient simulations were performed to check out the robustness and calculate the output spectrum and limitations of the circuit under ambient temperature of +27°C and different power-supply voltages as shown of Figs. 8.4, 8.5 and 8.6. For this simulations the differential sinusoidal signal input was set to -18dB with frequency at 12.48MHz which corresponds to 0.998π rad/s with a system sampling frequency of 25MHz.



Fig. 8.3 Switched-Capacitor Input Circuit Looking at the shape of the output spectrum on Figs. 8.4, 8.5 and 8.6 it is possible to recognize a high pass transfer function system. Looking carefully on the high pass baseband of work spectrum it is also possible to observe that the lower the temperature the less tolerance the circuit has to lower values of power-supply voltages. On Fig. 8.4 it is shown that for a power-supply voltage below minus 5% of its nominal value of 1.20V the noise is increased at the desired high pass baseband of work which would succeed on a lower SNDR operation point for the Sigma-Delta modulator. The same appointment and behaviour happens for the ambient temperature of +27°C, but for power-supply voltage minus 10% under its nominal value. One reason for this drawback is that by lowering the power supply voltage the operational amplifier operational working point derivates from its nominal polarization condition which degrades the required parameters for a proper operation of the Sigma-Delta modulator. The second reason is that by lowering the power-supply voltage the 90nm transistor MOS characteristics for nominal operation voltage of 1.20V are taken out from their voltage source-drain quiescent operation point that could be overcome just with lower transistor voltage threshold which design and study is beyond this work and open for further ones. One possible simpler solution would be to increase the nominal power-supply voltage on at least 10% to achieve then an overall tolerance of ±10% for any case of extreme temperatures. The second set of circuit simulations was to determine the SNDR curve of the Sigma-Delta modulator for different differential sinusoidal input signal amplitudes ranging from -48dB to -3dB for different power-supply voltages at the ambient temperature of +27°C as depicted on Fig. 8.7. As previously mentioned for power-supply voltages below minus 5% of the nominal value the Sigma-Delta modulator does not achieve its proper operation, meaning that either the nominal power-supply voltage should be increased or the nominal power-supply voltage of 1.20V should have a tolerance on the range of ±5%. Applying then the Input Circuit of Fig. 8.3b and introducing the additional clock signals of Fig. 8.8 to control the transmission-gates of the Input Circuit so that an artificial inbuilt sinusoidal sampled signal of one fourth of the system sampling frequency could be generated without additionally external circuitry for a future die fabrication some CADENCE Spectre [73] transient simulations were ran for different first stage input capacitor scaling factors to find the optimum value for which the Sigma-Delta modulator outputs a flatten spectrum at the high pass baseband frequency range of work as shown on Fig. 8.9. Finally on Fig. 8.11 are shown the optimum first stage input capacitor’s values and the final scaled switched-capacitor 2nd Order High Pass Sigma-Delta Modulator Transistor Design for this project. To run the fully set of statistical tests it would be required to sample at least 1.54 billion samples from CADENCE Spectre [73] transient simulation which its beyond the computer’s memory size and computation time processing. Only a real integrated-circuit system version could give that amount of samples in much less time. The only way to apply all tests is by producing a real die and performing real measures, but that was left for future works.



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-140

-120

-100

-80

-60

-40

-20

0Output q Spectrum / T = -40°C

Mag

nitu

de

[dB

]

ω [xπ rad/s]

0.985 0.99 0.995 1-140

-120

-100

-80

-60

-40

-20

0

Mag

nitu

de [

dB]

ω [xπ rad/s] Baseband

Discrete-Time System ModelCADENCE Spectre Vdd-Vss = 1.08VCADENCE Spectre Vdd-Vss = 1.14VCADENCE Spectre Vdd-Vss = 1.20VCADENCE Spectre Vdd-Vss = 1.26VCADENCE Spectre Vdd-Vss = 1.32V

Fig. 8.4 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of -40°C with

a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-140

-120

-100

-80

-60

-40

-20

0Output q Spectrum / T = +27°C

Mag

nitu

de

[dB

]

ω [xπ rad/s]

0.985 0.99 0.995 1-140

-120

-100

-80

-60

-40

-20

0

Mag

nitu

de [

dB]



Fig. 8.5 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +27°C with

a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-140

-120

-100

-80

-60

-40

-20

0Output q Spectrum / T = +100°C

Mag

nitu

de

[dB

]

ω [xπ rad/s]

0.985 0.99 0.995 1-140

-120

-100

-80

-60

-40

-20

0

Mag

nitu

de [

dB]



Fig. 8.6 Sigma-Delta Modulator Output Spectrum for different power supply voltages at the temperature of +100°C

with a differential sinusoidal signal input of -18dB at 12.48MHz and sampling frequency of 25MHz

-60 -50 -40 -30 -20 -10 00

20

40

60

80

100

120SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C

Vin0.998π [dB]

SN

DR

[dB

]

Vdd-Vss = 1.08VVdd-Vss = 1.14VVdd-Vss = 1.20VVdd-Vss = 1.26VVdd-Vss = 1.32V

1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.40

20

40

60

80

100

120

SN

DR

[dB

]

(Vdd-Vss) [V] | Vin0.998π = -15dB[dB]

SNDR HPSDM 2nd Ord | OSR = 256 | T = 27°C

Fig. 8.7: High Pass Sigma-Delta Modulator SNDR curve for different power-supply voltage values at the ambient temperature of +27°C



Fig. 8.8 Clock Signals for the Input Transistor Circuit Design

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-120

-100

-80

-60

-40

-20

0HPSDM 2nd Orded Output Spectrum | OSR = 256 | T = 27°C | Vdd-Vss = 1.20V

ω [xπ rad/s] | fs = 25MHz

Mag

nitu

de [

dB]

Fig. 8.9 Clock Signals for the Input Transistor Circuit Design

This final 256 times oversampled 2nd order high pass Sigma-Delta modulator with a sampling frequency of

25MHz, under nominal power-supply voltage of 1.20V and ambient temperature of +27°C together with the digital signal-processing decimation filter with a “Zero-Cross Comparator” algorithm explained before gives a random bit stream of 100Kbs/s at the output of the final TRNG system structure depicted on Fig. 8.10. The simulated dynamic power consumption for the Sigma-Delta modulator transistor circuit on Fig. 8.11 is 1.6mW. For estimation of Sigma-Delta modulator on die chip area it was taken from reference [51] the non-cascaded second order Sigma-Delta modulator with total capacitance per stage of 2pF which has an area of 0.096 mm2 and due to the fact that the area is mainly determined by the size of the capacitors the estimated area for this totally new 2nd order high pass Sigma-Delta modulator built on 90nm CMOS technology would be around 3 times smaller given an area of 0.032 mm2 which is comparable to other TRNG references and integrated-circuits mentioned at the introduction of this work and listed on Table 8.1 for comparisons. Looking on the system of Fig. 8.10 besides the 2nd order high pass Sigma-Delta modulator it would be also interesting to implement the sinusoidal multiplication and the 3rd Order TSinc FIR Filter in a CMOS hardware system due to the required high clock frequency for this filter in this system and known effective hardware implementation for this kind of filter [38]. The One Fourth Band with TSinc Compensation FIR Filter and the “Zero-Cross Comparator” algorithm could then be implemented in a DSP microprocessor system with such filters’ orders that it does not degrade the resolution of the previous Sigma-Delta modulator once its resolution is going to decide the performance of the overall system and additionally leaves the option to implement the “Gauss Distribution Comparator” algorithm described before if a higher random output bit stream rate is desired for an application with possibility to achieve more then 1.76Mbs/s at the output of the system.



Fig. 8.10 Final TRNG with a Sigma-Delta Modulator ADC System



Fig. 8.11 Switched-Capacitor Sigma-Delta Modulator Circuit Design with additional Input Circuit Ref. / Year Method Technology Area Voltage Power Clk Freq. Bit Rate Tests [12] 2001 Metastability n. a. n. a. 5.0V n. a. 25MHz n.a. n. s. [13] 2002 Metastability AMS 0.6um n. a. 3.3V n. a. 100MHz 100Mbs/s n. s. [16] 2004 Astable Multivibrator SBD-MOS n. a. 5.0V n. a. 16MHz 50Kbs/s FIPS [37] [9 10] 1999 Dual Osc. Sampling n. a. n. a. 3.3V n. a. n. a. 75Kbs/s FIPS [37] [17] 2004 Dual Osc. Sampling CMOS 0.18um n. a. 1.8V n. a. 1GHz 1Gbs/s FIPS [37] [8] 2003 Dual Osc. Sampling CMOS 0.18um 0.0016mm2 3.3V 2.3mW 10GHz 10Mbs/s FIPS [37] [19] 1997 Direct-Noise Amplif. CMOS 1.2um 2.92mm2 5.0V 37mW 10KHz 5Kbs/s n. s. [22] 2003 Direct-Noise Amplif. CMOS 2um 0.443mm2 1.8V 1mW 2.5KHz 2Kbs/s n. s. [24] 2002 Direct-Noise Amplif. CMOS 0.18um 0.025mm2 3.3V 3.6mW 10MHz 5Mbs/s n. s. [23] 2001 Chaotic System CMOS 0.8um 0.0042mm2 5.0V 1mW 1MHz 1Mbs/s n. s. [28] 2005 Chaotic System CMOS 0.25um 0.022mm2 2.5V 117mW 10MHz n.a. n. s. [29 30] 2001 Chaotic System CMOS 0.8um n. a. 5.0V n. a. 5MHz 1Mbs/s n. s. [31] 2000 Chaotic System AMS 0.6um n. a. 5.0V n. a. 12MHz 4Mbs/s FIPS [37] [32] 2005 Chaotic System n. a. n. a. 1.5V n. a. n.a. 10Mbs/s FIPS [37] [7] 2000 Hybrid System CMOS 2um 1.5mm2 3.0V 3.9mW n.a. 1Mbs/s n. s. [21] 2006 Direct-Noise Amplif. CMOS 0.12um 0.009mm2 1.5V 50uW 5MHz 200Kbs/s n. s. This Work

Sigma-Delta Mod.

CMOS 90nm

~0.032mm2

1.2V

1.6mW

25MHz

with ZCC ~ 100Kbs/s

with GDC ≥1.76Mbs/s

AIS 31 [4]

n. a. = not available / n. s. = not standard / ZCC = Zero-Cross Comparator / GDC = Gauss-Distribution Comparator Table 8.1 Characteristics performance comparison for different TRNG methodologies

It should be noticed that the FIPS [37] Standard Statistical Tests (SSTs) have similarities to the AIS 31 SSTs [4], but the FIPS allows that some tests to have a certain percentage of error on the randomness on the generated bit stream which is not allowed on the AIS 31 Standard Statistical Tests. For better comparison it would be necessary to make a carefully analysis over the FIPS SSTs results with the AIS 31 SSTs results. 9. Conclusion and Future Works As stated at the beginning, this work intended to study the feasibility of random number generation through a Sigma-Delta modulator with additional digital signal-processing block system through a noise source integrated into the modulator’s feedback loop. This was accomplished through the final built on 90nm CMOS technology totally new 2nd order high pass Sigma-Delta modulator transistor circuit and established requirements for additional digital-signal processing blocks for conception of an entire True Random Number Generation system based on a totally new principle besides the other ones already mentioned at the references. From the initial three possible studied low pass, band pass and high pass Sigma-Delta modulator structures it came out through system model simulations concerning the oversampling rate, thermal noise magnitude and Flicker Noise Corner Frequency influences over the output spectrum and AIS 31 Standard Statistical Tests results that the high pass system has the desired robustness and qualified itself appropriate to be implemented as a circuit solution. It should be mentioned that for the first time a totally new designed high pass Sigma-Delta modulator was built and used, but it should be noticed that due to the fact that the thermal noise is the useful signal to be extracted from the system, there is no need for a high order decimation filter rather than if a high pass Sigma-Delta modulator would be used to other analog signal-processing application which in this case it would be very difficult to design a decimation filter that fulfills the desired Nyquist frequency. The fact that the thermal noise is the useful signal in this work also allows the use of a relaxed decimation filter because the convolution of part of the upper side spectrum at half the sampling frequency will not effect the proper operation of the high pass Sigma-Delta modulator because there would be added just more thermal noise at the baseband frequency of work which could still be used to generate random numbers. Additionally to these relaxing requirements this high pass system also holds an enhanced advantage regarding influences of the Flicker noise over the output spectrum and generated random output bit stream. Together with the first system simulations there were also determined the DSP decimation filter requirements as well as there were defined and implemented two possible algorithms for the generation of the final random output bit stream where one of them named “Gauss Distribution Comparator” algorithm enables the increase of the out bit stream rate despite of the reduction caused by to the oversampling rate process that follows the signal-processing decimation and without lose of the output entropy if instead a “Zero-Cross Comparator” algorithm is applied. Although many simulations were ran to certify this new “Gauss Distribution Comparation” approach, due to the high amount of necessary computation capacity and lack of time further simulations were decided to be done using the “Zero-Cross Comparator” algorithm leaving the option open for the use or not of a higher bit rate on future works.



Followed by this analysis there came out two possible topologies to implement the high pass transfer function with a switched-capacitor circuit. Through a carefully analyze on the transfer function equations it was found out that by switching the polarity of the integrating-capacitor on the classic basic low pass cell circuit on alternating clock cycles a high pass transfer function could be implemented with less switching-gates and switched-capacitors for a whole 2nd order high pass Sigma-Delta modulator structure. One classical and one reduced circuit structures were built testifying that they were equivalent and that the reduced version could be used on the further requirement analysis for the different components of the analog circuit design. Using this reduced version and its equivalent discrete-time system model there were determined the parameter requirements characterization for the operational amplifier, comparator, transmission gate and scaled switched-capacitor for their further implementation using a 90nm CMOS library technology on transistor circuit level design. Through these required parameters the operational amplifier with common-mode feedback control, the latched comparator, the transmission gate and the switched-capacitor transistor circuits were built compounding finally the whole Sigma-Delta modulator Analog-to-Digital converter circuit. There were then ran circuit simulations for different power-supply voltages and environment temperatures to measure the Sigma-Delta modulator circuit robustness, limitations and characteristic SNDR curve for different differential sinusoidal input amplitudes under these different conditions for comparations with theoretical previous results. Through these analysis it was determined the required scaling factor for the input signal circuit and finally using the previous designed digital signal-processing decimation filter and “Zero-Cross Comparator” algorithm an entire TRNG system was built. The totally new concept of TRNG with a totally new 2nd order high pass Sigma-Delta modulator built on this work shows that this concept of random number generation is one more possible solution and comparable in performance to other mentioned works. It should be noticed that this is just an initial and original study which opens themes for many other researches like the usage of higher order high-pass Sigma-Delta modulator ADCs with multi bit structures and analysis of the required decimation signal-processing filter resolution which could yield to less digital-signal processing area and power consumption. Another possible study would be the design of an enhanced operational amplifier on 90nm CMOS technology which Monte-Carlo analysis achieve higher percentage process and mismatch fabrication yields. One interesting study would also be the design of a decimation signal-processing system which could make fulfill all those AIS 31 Standard Statistical Tests that does not pass when the Flicker Noise Corner frequency gets higher. Besides that it would be interesting to implement a layout version of this 2nd order high pass Sigma-Delta modulator to generate the requested amount of random bits to apply the fully AIS 31 Standard Statistical Tests as well as implement on a DSP system the “Gauss Distribution Comparator” algorithm to achieve higher output bit stream rates and analyze the trade offs between the One Fourth with TSinc Compensation Filter requirements and the parameter N for the “Gauss Distribution Comparator” algorithm. It would be also interesting to check out the robustness of the system on a real hardware application to power-source supply tolerance, environment temperature, electromagnetic interference and other external influences over the generated random output bit stream to better classify this system accordingly to the AIS 31 Document Standard requirements [4]. Additionally to the present built circuit it would be probably required and automatic feedback control system which measures the distribution of the random bits to recalibrate it to AIS 31 Standard Statistical Tests limits.



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[36] “Common Criteria for Information Technology Security Evaluation CEM-99/045, Part 2: Evaluation Methodology, Version 1.0, August 1999. [37] “National Institute of Standards and Technology, Data encryption standard” Federal Information Processing Standards Publications, FIPS PUB 140-2, NIST SP 800-2214. Sigma-Delta Modulator [38] Johns, D. A., Martin, K., “Analog Integrated Circuit Design”, John Wiley & Sons, Inc., 1997, ISBN 0-471-14448-7 [39] Norsworthy, S., Schrei, R., Temes, G. C., “Delta-Sigma Data Converters – Theory, Design, and Simulation”, IEEE Press, 1997, ISBN 0-7803-1045-4 [40] Brandt, B., "Oversampled Analog-to-Digital Conversion", Technical Report No. ICL91-009, Stanford University, August 1991. [41] Schreier, R., Snelgrove, M., “Bandpass Sigma-Delta Modulation”, Electronics Letters, vol. 25, no. 23, November 1989. [42] Jantzi, S., Schreier, R., Snelgrove, M., “Bandpass Sigma-Delta Analog-to-Digital Conversion”, IEEE Transactions on Circuits and Systems, vol. 38, no. 11, September 1991. [43] Jantzi, S. A., Schreier, R., Suelgrove, M., “A Bandpass Sigma-Delta A/D Converter for a Digital Am Receiver“, IEE International Conference On Analogue-to-Digital and Digital-to-Analogue Conversion, September 1991. [44] Brigati, S., Francesconi, F., Malcovati, P., Tonietto, D., Bashirotto, A., Maloberti, F., “Modeling Sigma-Delta Modulator Non-Idealities in Simulink”, Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 2, Jun 1999. Digital Signal Processing [45] Oppenheim, A. V., Schafer R. W., “Digital Signal Processing”, Prentice-Hall, 1975, ISBN 0-13-214635-5 [46] Schreier, R., Snelgrove, W. M., “Decimation for Bandpass Sigma-Delta Analog-to-Digital Conversion”, IEEE International Symposium on Circuits and Systems, vol. 3, May 1990. Thermal Noise & Flicker Noise & Transistor Circuit Design [47] Abidi, A.A., “High-Frequency Noise Measurements on FETs with Small Dimensions”, IEEE Transactions Electronic Devices, vol. 33, Nov. 1986. [48] Razavi, B., “Design of Analog CMOS Integrated Circuits”, McGraw Hill International Edition, 2001, ISBN 0-07-118815-0 [49] Senderowicz, D., “A Family of Differential NMOS Analog Circuit for PCM Codec Filter Chip”, IEEE Journal of Solid-State Circuits, vol. 17, Dec. 1982. [50] Castello, R., Gray, P. R., “A High-Performance Micropower Switched-Capacitor Filter”, IEEE J. of Solid-State Circuits, vol. 20, Dec. 1985. [51] Sauerbrey, J., Wittig, M., Schmitt-Landsiedel, D., Thewes, R., "0.65V Sigma-Delta modulators", Proc. ISCAS, pp. I1021-I1024, 2003. Flicker Noise [52] Nemirovsky, Y., Jakobson, C. G., “1/f Noise in CMOS Transistors for Analog Applications”, IEEE Transactions on Electron Devices, Vol. 48, May 2001. [53] Knitel, M. J., Woerlee, P.H., “Impact of Process Scaling on 1/f Noise in Advanced CMOS Technologies”, IEDM, Dec 2000.



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11. Appendix

Documents

True Random Number Generator based on a Sigma-Delta …True Random Number Generator based on a Sigma-Delta Modulator Master Thesis on System-on-Chip Design – Royal Institute of Technology