Trigger Board CDRMatthew Warren University College London11 October 2002

Trigger Board CDR - Matthew Warren UCL

OverviewVME Module- 6U, Slave - 16 bit Data Bus (D32 okay, but only lower 16 bits data)All requirements not known - Incoming trigger unspecified - Use in alien crates possible - Trigger destinations unspecified (HCAL ReadOut design?)= Must have flexible I/O= Able to operate at 5V= Configurable operation - CPLD ideal

Trigger Board CDR - Matthew Warren UCL

On the PCBFront-panel and Back-plane NIM/LVDS - see next slideSingle, large CPLD2 Delay-units - 64 2-5ns steps each - detect excessive Activity 50MHz Local ClockBase Address select hex-switchesSuper-dumb Mode jumpers - bypasses CPLD entirelyPower pin select jumpers - including JAux option8 pin Debug header for scope or logic analyserBuffers for all VME signals

Trigger Board CDR - Matthew Warren UCL

External I/OFront-panel NIM: 10 Inputs, 10 Outputs - Double height LEMO 00 connectors - Each signal connected to CPLD LVDS: 10x4 Fan-out - 4 IDC 20-way connectors - 10 Individual CPLD signals - Fanned-out with hardware - Custom PSU powered (only works is our crate)

Back-plane LVDS: 4 Outputs - uses custom J2 pins - custom PSU powered

Trigger Board CDR - Matthew Warren UCL

Generic OperationCPLD SigInVMEenSigInVSigenSigOutSigOutNIM - All Inputs have OutputsIn-Modify-Out designAllows master-slave configuration of multiple Trigger BoardsBSigOutLSigOut

Trigger Board CDR - Matthew Warren UCL

Firmware (or Why Use a CPLD...)VME Interface (asynchronous)VME generated Triggers etc. Status registerTest registers (and stand-alone testability)Signal enables (Inputs and Outputs)Generate stand-alone 12.5MHz read-out clockLong Delays (20ns/80ns steps)Trigger-Veto-Abort cycle state-machineActivity Auto-Abort (using delay-units)Counters (Trigger number etc.)Timers

Trigger Board CDR - Matthew Warren UCL

CPLD/PinsRequirements:- 167 pins + 20% margin = ~200 pins- 7ns required for 50Mhz clock- 5V Component simplifies design- Need ample logic

Quickest design route Xilinx Spartan II - Schematics for other components - Firmware too

Trigger Board CDR - Matthew Warren UCL

Signal Group

Pins

Signal Front Panel

33

Signal Backplane

4

VME

101

Debug Connector

8

Delay Units

16

LEDs

5

Total

167

SummaryMissing info on input/output and specific functions?Goal is to have room for whatever is asked of us:- Enough I/O- Enough Pins Enough Support Hardware

Trigger Board CDR - Matthew Warren UCL