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Trends in Pixel Detectors: Tracking and ImagingNorbert Wermes

(Invited Paper)

Abstract— For large scale applications, hybrid pixel detectors,in which sensor and read-out IC are separate entities, constitutethe state of the art in pixel detector technology to date. Theyhave been developed and start to be used as tracking detectorsand also imaging devices in radiography, autoradiography,proteincrystallography and in X-ray astronomy. A number of trends andpossibilities for future applications in these fields with improvedperformance, less material, high read-out speed, large radiationtolerance, and potential off-the-shelf availability have appearedand are momentarily matured. Among them are monolithic orsemi-monolithic approaches which do not require complicatedhybridization but come as single sensor/IC entities. Most ofthese are presently still in the development phase waiting tobe used as detectors in experiments. The present state in pixeldetector development including hybrid and (semi-)monolithic pixeltechniques and their suitability for particle detection and forimaging, is reviewed.

Index Terms— pixel detector, hybrid pixels, monolithic pixels,tracking, imaging

I. I NTRODUCTION

Albeit being similar at first sight, the requirements forcharged particle detection in high energy physics comparedtoimaging applications with pixel detectors can be very differ-ent. In particle physics experiments charged particles, usuallytriggered by other subdetectors, have to be identified withhigh demands on spatial resolution and timing. In imagingapplications the image is obtained by the un-triggered accumu-lation (integrating or counting) of the quanta of the impingingradiation, often also with high demands (e.g.> 1 MHz per pixelin certain radiography or CT applications). Si pixel detectors forhigh energy charge particle detection can assume typical signalcharges collected at an electrode in the order of 5,000-10,000electrons even taking into account charge sharing between cellsand detector deterioration after irradiation to doses as high as60 Mrad. In 3H-autoradiography, on the contrary, or in X-ray astronomy the amount of charge to be collected with highefficiency can be much below1000 e. The spatial resolution isgoverned by the attainable pixel granularity from a few to about10µm at best, obtained with pixel dimensions in the order of50µm to 100µm. The requirements from radiology are similar.Mammography (∼ 80µm pixel dimensions) is most demandingwith respect to space resolution. Some applications in autora-diography, however, require sub-µm resolutions, not attainable

N. Wermes is with Bonn University, Physikalisches Institut, Nussallee 12,D-53115 Bonn, Germany, email: wermes@physik.uni-bonn.de

Work supported by the German Ministerium fur Bildung, Wissenschaft,Forschung und Technologie (BMBF) under contract no.05HA8PD1, bythe Ministerium fur Wissenschaft und Forschung des LandesNordrhein–Westfalen under contract no. IVA5 − 106 011 98, and by the DeutscheForschungsgemeinschaft DFG

with present day semiconductor detectors. For applications withlower demands on the spatial resolution (PSF ∼5-10µm)but with requirements on real time and time resolved dataacquisition, semiconductor pixel detectors are very attractive.

Very thin detector assemblies are mandatory for vertex detec-tors at collider experiments, in particular for the plannedlineare+e− collider. This imposes high demands on the detectordevelopment. While silicon is almost a perfect material forparticle physics detectors, allowing the shaping of electric fieldsby tailored impurity doping, the need of high photon absorptionefficiency in radiological applications requires the studyanduse of semiconductor materials with high atomic charge, suchas GaAs or CdTe. For such materials the charge collectionproperties are much less understood and mechanical issues inparticular those related to hybrid pixels are abundant, mostnotably regarding the hybridization of detectors when theyarenot available in wafer scale sizes. Finally, for applications inhigh radiation environments, such as hadron colliders, radiationhard sensors are developed using either Si with a dedicateddesign or CVD-diamond.

II. H YBRID PIXELS: THE STATE OF THE ART IN PIXEL

DETECTORTECHNOLOGY

In the hybrid pixel techniquesensor and FE-chips are sepa-rate parts of the detector module connected by small conductingbumps applied by using the bumping and flip-chip technology.All LHC-collider-detectors [1], [2], [3] ALICE, ATLAS, andCMS, LHCb for the RICH system [4], as well as somefixed target experiments (NA60[5] at CERN and BTeV[6] atFermilab) employ the hybrid pixel technique to build largescale (∼m2) pixel detectors. Pixel area sizes are typically50µm×400µm as for ATLAS or100µm ×150µm as for CMS. Thedetectors are arranged in cylindrical barrels of2−3 layers anddisks covering the forward and backward regions. The mainpurpose of the detectors at LHC is (a) the identification of shortlived particles (e.g. b-tagging for Higgs and SUSY signals), (b)pattern recognition and event reconstruction and (c) momentummeasurement. The detectors need to withstand a total (10 yr)particle fluence of1015neq corresponding to a radiation doseof about 50 Mrad. The discovery that oxygenated silicon isradiation hard with respect to the non-ionizing energy lossofprotons and pions [7] saves pixel detectors at the LHC forwhich the radiation is most severe due to their proximity to theinteraction point.n+ electrode in n-bulk material sensors havebeen chosen to cope with the fact that type inversion occursafter aboutΦeq = 2.5×1013cm−2. After type inversion thepn-diode sits on the electrode side thus allowing the sensor to be

operated partially depleted. Figure 1(a) shows the developmentof the effective doping concentration and the depletion voltageVdep as a function of the fluence expected for 10 years ofoperation at the LHC (see also [8]). Figures 1(b) and (c) showthe ATLAS pixel sensor wafer with 3 tiles [9] and the detectorresponse after irradiation over two adjacent pixels showing avery homogeneous charge collection except for some tolerableloss at the outer edges and in an area between the pixels. Theseare due to the bump contact and a bias grid, respectively, whichhas been designed to allow testing of the sensors before bondingthem to the electronics ICs.

Fig. 1

(A) EFFECTIVE DOPING CONCENTRATION AND DEPLETION VOLTAGE AS A

FUNCTION OF THE FLUENCE, (B) ATLAS SILICON PIXEL WAFER WITH 3

TILES, AND (C) CHARGE COLLECTION EFFICIENCY IN TWO ADJACENT

PIXELS AFTER IRRADIATION.

The challenge in the design of the front-end pixel electronics[10], [11] can be summarized by the following requirements:low power (< 50µW per pixel), low noise and thresholddispersion (together< 200e), zero suppression in every pixel,on-chip hit buffering, and small time-walk to be able to assignthe hits to their respective LHC bunch crossing. The pixelgroups have reached these goals in several design iterationsusing first radiation-soft prototypes, then dedicated radharddesigns, and finally using deep submicron technologies [11].While CMS uses analog readout of hits up to the countinghouse, ATLAS obtains pulse height information by means ofmeasuring thetime over threshold(ToT) for every hit.

The chip and sensor connection is done by fine pitch bump-ing and subsequent flip-chip which is achieved with either PbSn(solder) or Indium bumps at a failure rate of< 10−4. Figure 3shows rows of50µm pitch bumps obtained by these techniques.

Fig. 2

(LEFT) INDIUM (PHOTO AMS, ROME) AND (RIGHT) SOLDER(PBSN,

PHOTO IZM, B ERLIN) BUMP ROWS WITH50µM PITCH.

Indium bumping is done using a wet lift-off techniqueapplied on both sides (sensor and IC) [12]. The connectionis obtained by thermo-compression. The Indium joint is com-paratively soft and the gap between IC and sensor is about6µm. PbSn bumps are applied by electroplating [13]. Here thebump is galvanically grown on the chip wafer only. The bumpis connected by flip-chipping to an under-bump metallizationon the sensor substrate pixel. Both technologies have beensuccessfully used with 8” IC-wafers and 4” sensor wafers.

In the case of ATLAS amoduleof 2.1x6.4 cm2 area consistsof FE-chips bump-connected to one silicon sensor. The I/O linesof the chips are connected via wire bonds to a kapton flex circuitglued atop the sensor. The flex houses a module control chip(MCC) responsible for front end time/trigger control and eventbuilding. The total thickness at normal incidence is in excess of2% X0. Figure 3 shows a241Am (60 keVγ) source scan of anATLAS module with 46080 pixels and an amplitude spectrumobtained using the ToT analog information without clusteringof pixels.

The modules are positioned by dedicated robots on carbon-carbon ladders (staves) and cooled by evaporation of a fluorinertliquid (C3F8) at an input temperature below−20oC in orderto maintain the entire detector below−6oC to minimize thedamage induced by radiation. This operation requires pumpingand the cooling tubes must stand16 bar pressure if pipe block-ing occurs. All detector components must survive temperaturecycles between−25oC and room temperature. The LHC pixeldetectors are presently in production. A sketch of the finalATLAS pixel detector is shown in fig. 4.

III. T RENDS IN HYBRID PIXEL DETECTORS

To improve the performance of Hybrid Pixel detectors in cer-tain aspects several ideas and developments are being pursued.

A. HAPS

Hybrid (Active) Pixel Sensors (HAPS) [14] exploit capacitivecoupling between pixels to obtain smaller pixel cells and pixel

Fig. 3

(TOP) SCAN OF AN ATLAS PIXEL MODULE (46080PIXELS) WITH A 241AM

(60 KEV γ) SOURCE AND(BOTTOM) THE CORRESPONDING AMPLITUDE

SPECTRUM OBTAINED USING THE SIGNAL AMPLITUDE VIA

TIME-OVER-THRESHOLD(TOT) WITHOUT CLUSTERING.

Fig. 4

V IEW OF THE ATLAS PIXEL DETECTOR IN ITS PRESENT DESCOPED

VERSION WITH TWO BARREL LAYERS AND2X3 DISKS.

pitch with a larger readout pitch resulting in interleaved pixels.The pixel pitch is designed for best spatial resolution usingcharge sharing between neighbors while the readout pitch istailored to the needs for the size of the front-end electronicscell. This way resolutions between 3µm and 10µm can beobtained with pixel (readout) pitches of 100µm (200µm) asis shown in fig. 5(b) together with the layout of a prototypesensor in fig. 5(a).

B. MCM-D

The present hybrid-pixel modules of the LHC experimentsuse an additional flex-kapton fine-print layer on top of the Si-sensor (fig. 6(a)) to provide power and signal distribution to

Fig. 5

(LEFT) LAYOUT OF A HAPSSENSOR WITH DIFFERENT PIXEL AND

READOUT PITCHES, (RIGHT) MEASURED SPATIAL RESOLUTIONS BY

SCANNING WITH A FINE FOCUS LASER.

and from the module front-end chips. An interesting alternativeto the flex-kapton solution is the so-called Multi-Chip-ModuleTechnology deposited on Si-substrate (MCM-D) [16]. A multi-conductor-layer structure is built up on the silicon sensor. Thisallows to bury all bus structures in four layers in the inactivearea of the module thus avoiding the kapton flex layer andany wire bonding at the expense of a small thickness increaseof 0.1% X0. In addition, the extra freedom in routing makesit possible to design pixel detectors which have the samepixel dimensions throughout the sensor, i.e. without larger edgepixels usually necessary to accommodate the sensor area whichremains uncovered by electronics in between chips. Figure 6(b)illustrates the principle and fig. 6(c) shows scanning electronmicrophotographs (curtesy IZM, Berlin) of a via structure madein MCM-D technology.

C. Active edge 3-D silicon

The features of doped Si allow interesting geometries withrespect to field shapes and charge collection. So-called 3Dsilicon detectors have been proposed [17] to overcome sev-eral limitations of conventional planar Si-pixel detectors, inparticular in high radiation environments, in applications withinhomogeneous irradiation and in applications which require alarge active/inactive area ratio such as protein crystallography[18]. A a 3D-Si-structure (fig. 7(a)) is obtained by processingthe n+ and p+ electrodes into the detector bulk rather thanby conventional implantation on the surface. This is doneby combining VLSI and MEMS (Micro Electro MechanicalSystems) technologies. Charge carriers drift inside the bulkparallel to the detector surface over a short drift distanceoftypically 50µm. Another feature is the fact that the edge of thesensor can be a collection electrode itself thus extending theactive area of the sensor to within about 10µm to the edge.This results from the undepleted depth at this electrode. Edgeelectrodes also avoid inhomogeneous fields and surface leakage

Fig. 6

(A) SCHEMATIC VIEW OF A HYBRID PIXEL MODULE SHOWING ICS BONDED

VIA BUMP CONNECTION TO THE SENSOR, THE FLEX HYBRID KAPTON

LAYER ATOP THE SENSOR WITH MOUNTED ELECTRICAL COMPONENTS,

AND THE MODULE CONTROL CHIP(MCC). WIRE BOND CONNECTIONS ARE

NEEDED AS INDICATED. (B) SCHEMATIC LAYOUT OF A MCM-D PIXEL

MODULE. (C) SEM PHOTOGRAPH OF AMCM-D VIA STRUCTURE (TOP)

AND A CROSS SECTION AFTER BUMP DEPOSITION(BOTTOM).

currents which usually occur due to chips and cracks at thesensor edges. This is seen in fig. 7(b) which shows the twostructures in comparison. The main advantages of 3D-silicondetectors come from the fact that the electrode distance isshort (50µm) in comparison to conventional planar devices atthe same total charge, resulting in a fast (1-2 ns) collectiontime, low (< 10V) depletion voltage and, in addition, a largeactive/inactive area ratio of the device.

The technical fabrication is much more involved than forplanar processes and requires a bonded support wafer and re-active ion etching of the electrodes into the bulk. A compromisebetween 3D and planar detectors, so called planar-3D detectorsmaintaining the large active area, use planar technology butwith edge electrodes [19], obtained by diffusing the dopantfrom the deeply etched edge and then filling it with poly-silicon.Prototype detectors using strip or pixel electronics have beenfabricated and show encouraging results with respect to speed(3.5 ns rise time) and radiation hardness (> 1015 protons/cm2)[20].

D. Diamond Pixel Sensors

Diamond as a potentially very radiation hard material hasbeen explored intensively by the R&D collaboration RD42 atCERN [21]. Charge collection distances up to 300µm havebeen achieved. Diamond pixel detectors have been built withpixel electronics developed for the ATLAS pixel detector andoperated as single-chip modules in testbeams [22]. A spatialresolution ofσ = 22µm has been measured with 50µm pixelpitch, compared to about 12µm with Si pixel detectors of thesame geometry and using the same electronics. This reveals

Fig. 7

(TOP) SCHEMATIC VIEW OF A 3D SILICON DETECTOR, (BOTTOM)

COMPARISON OF THE CHARGE COLLECTION IN3D-SILICON AND

CONVENTIONAL PLANAR ELECTRODE DETECTORS.

the characteristic systematic spatial shifts observed in CVDdiamond due to the crystal growth. Grain structures are formedin which trapped charges at the boundaries produce polarizationfields inside the sensor which cause the observed spatial shiftsof the order of 100-150µm.

IV. H YBRID PIXELS IN IMAGING APPLICATIONS

A. Counting Pixel Detectors for (Auto-)Radiography

A potentially new route in radiography techniques is thecounting of individual X-ray photons in every pixel cell. Thisapproach offers many features which are very attractive forX-ray imaging: full linearity in the response function and aprincipally infinite dynamic range, optimal exposure timesanda good image contrast compared to conventional film-foil basedradiography. It thus avoids over- and underexposed images.Counting pixel detectors must be considered as a very directspin-off of the detector development for particle physics intobiomedical applications. The analog part of the pixel electronicsis in parts close to identical to the one for LHC pixel detectorswhile the periphery has been replaced by the counting circuitry[23].

The challenges to be addressed in order to be competitivewith integrating radiography systems are: high speed (> 1MHz) counting with a range of at least 15 bit, operation withvery little dead time, low noise and particularly low thresholdoperation with small threshold dispersion values. In particularthe last item is important in order to allow homogeneousimaging of soft X-rays. It is also mandatory for a differential

Fig. 8

IMAGE OF A 55FE POINT SOURCE TAKEN WITH THEMEDIPIX2 COUNTING

CHIP AND A SILICON SENSOR(14X14 MM2)[26].

energy measurement, realized so far as a double threshold withenergy windowing logic [24], [25]. A differential measurementof the energy, exploiting the different shapes of X-ray spectrabehind for example tissue or bone, can enhance the contrastperformance of an image. Finally, for radiography high photonabsorption efficiency is mandatory, which renders the not easytask of high Z sensors and their hybridization necessary.

Progress with counting pixel systems have been reported atthis conference [26], [27], [28]. The MEDIPIX chip developedby the MEDIPIX collaboration [29], [25] uses256 × 256,55×55µm2 pixels fabricated in0.25µm technology, energywindowing via two tunable discriminator thresholds, and a 13bit counter. The maximum count rate per pixel is about 1 MHz.Figure 8 shows an image of a55Fe point source obtained withthe Medipix2 chip bonded to a 14x14 mm2, 300µm thick Sisensor [26]. A similar image with a single chip CdTe detectorand a higher energy109Cd source (122 keVγ) has also beentaken and the capability to detect low energy beta decays fromtritium has been demonstrated [26].

A Multi-Chip module with 2x2 chips using high-Z CdTesensors with the MPEC chip [27] is shown in fig. 9. The MPECchip features32 × 32 pixels (200×200µm2), double thresholdoperation, 18-bit counting at∼1 MHz per pixel as well aslow noise values (∼120e with CdTe sensor) and thresholddispersion (21e after tuning) [30], [27]. A technical issue hereis the bumping of individual die CdTe sensors which has beensolved using Au-stud bumping with In-filling [31].

A challenge for counting pixel detectors in radiology is tobuild large area detectors. Commercially available integratingpixellated systems such as flat panel imagers [32], [33] consti-tute the levelling scope.

Fig. 9

(LEFT) 2X2 MULTI -CHIP CDTE MODULE WITH COUNTING PIXEL

ELECTRONICS USING THEMPECCHIP ON A USB BASED READOUT BOARD

[27], (RIGHT) IMAGE OF A COGWHEEL TAKEN WITH 60 KEV X- RAYS.

B. Protein Crystallography

Hybrid Pixel detectors as counting imagers lead the wayto new classes of experiments in protein crystallography withsynchrotron radiation [34]. Here the challenge is to image,with high rate (∼1-1.5 MHz/pixel) and high dynamic range,many thousands of Bragg spots from X-ray photons of typically12 keV or higher (corresponding to resolutions at the 1A

range), scattered off protein crystals. The typical spot size of adiffraction maximum is100−200µm, calling for pixel sizes inthe order of100−300µm. The high linearity of the hit countingmethod and the absence of so-called ”blooming effects”, i.e. theresponse of non-hit pixels in the close neighborhood of a Braggmaximum, makes counting pixel detectors very appealing forprotein crystallography experiments. A systematic limitationand difficulty is the problem that homogeneous hit/count re-sponses in all pixels, also for hits at the pixel boundariesor between pixels where charge sharing plays a role mustbe maintained by delicate threshold tuning. Counting pixeldevelopments are made for ESRF (Grenoble, France) [35]and SLS (Swiss Light Source at the Paul-Scherrer Institute,Switzerland) beam lines. The PILATUS 1M detector [36] atthe SLS (217µm ×217µm pixels) is made of fifteen 16-chip-modules each covering8 × 3.5 cm2, i.e. a total area of40 × 40cm2. Figure 10(a) shows a photograph of this detectorwith 15 modules and close to 106 pixels covering an area of20×24 cm2 [37]. It is the first large scale hybrid pixel detectorin operation. Figure 10(b) shows a Bragg image of a Lysozymewith 10s exposure to 12 keV sychrotron X-rays [37]. Manyspots are contained in one pixel which is the limit of theachievable point spread resolution.

In summary hybrid pixel detectors are the present stateof the art in pixel detector technology. For tracking as wellas for imaging applications large (∼m2) detectors are beingbuilt or already in operation (PILATUS). On the negative sideare the comparatively large material budget, the complicatedassembling (hybridization) with potential yield pitfalls, andthe difficulty to obtain high assembly yields with non-waferscale high-Z sensor materials. As trends within this technology,

Fig. 10

(TOP) PHOTOGRAPH OF THE20X24 CM2 LARGE PILATUS 1M DETECTOR

FOR PROTEIN CRYSTALLOGRAPHY USING COUNTING HYBRID PIXEL

DETECTOR MODULES, (BOTTOM) IMAGE OF LYSOZYME TAKEN WITH

PILATUS [37], THE INSERT SHOWS THATBRAGG SPOTS ARE OFTEN

CONTAINED IN ONE PIXEL.

interleaved pixels and MCM-D promise better resolution andmore homogeneous modules, while 3D-silicon detectors canaddress applications in high radiation environments or thosewhere a large active/inactive area ratio is mandatory.

V. M ONOLITHIC AND SEMI-MONOLITHIC PIXEL

DETECTORS

Monolithic pixel detectors, in which amplifying and logiccircuitry as well as the radiation detecting sensor are one entity,produced in a commercially available technology, are the dreamof semiconductor detector developers. This will not be possiblein the near future without compromising. Developments andtrends in this direction have much been influenced by R&Dfor vertex tracking detectors at future colliders such as a

Linear e+e− Collider [38]. Very low (≪1% X0) material perdetector layer, small pixel sizes (∼20µm×20µm) and a goodrate capability (80 hits/mm2/ms) is required, due to the veryintense beamstrahlung of narrowly focussed electron beamsclose to the interaction region which produce electron positronpairs in vast numbers. High readout speeds of50 MHz line ratewith 40µs frame time are necessary.

Fig. 11

(A) SKETCH OF A MONOLITHIC PIXEL DETECTOR USING A HIGH

RESISTIVITY BULK WITH PMOS TRANSISTORS AT THE READOUT(AFTER

[39]), (B) PRINCIPLE OF ANMONOLITHIC ACTIVE PIXEL SENSOR(MAPS)

[41] TARGETING CMOSELECTRONICS WITH LOW RESISTIVITY BULK

MATERIAL . THE CHARGE IS GENERATED AND COLLECTED BY DIFFUSION IN

THE FEWµM THIN EPITAXIAL SI -LAYER .

Among the developments of monolithic or semi-monolithicpixel devices perhaps the following classifying list can bemade.

- Non-standard CMOS on high resistivity bulkThe first monolithic pixel detector, successfully operatedin a particle beam already in 1992 [39], used a highresistivity p-type bulk p-i-n detector in which the junctionhad been created by an n-type diffusion layer. On oneside, an array of ohmic contacts to the substrate served ascollection electrodes (fig. 11(a)). Due to this only simplepMOS transistor circuits sitting in n-wells were possiblein the active area. The technology was certainly non-standard and non-commercial. No further developmentemerged.

- CMOS technology with charge collection in epi-layerCommercial CMOS technologies use low resistivitysilicon which is not suited for charge collection. However,in some technologies an epitaxial silicon layer of a fewto 15µm thickness can be used [40], [41], [42]. Thegenerated charge is kept in the epi-layer by potential wellsat the boundary and reaches an n-well collection diodeby thermal diffusion (fig. 11(b)). The signal charge istherefore very small (<1000e) and low noise electronicsis a real challenge. As this development uses standardprocessing technologies it is potentially very cheap.Despite using CMOS technology the potential of fullCMOS circuitry in the active area is not available (onlynMOS) because of the n-well/p-epi collecting diodewhich does not permit other n-wells.

Fig. 12

(A) CROSS SECTION THROUGH A MONOLITHICCMOSON SOI PIXEL

DETECTOR USING HIGH RESISTIVITY SILICON BULK INSOLATED FROM THE

LOW RESISTIVITY CMOSLAYER WITH CONNECTING VIAS IN BETWEEN

[15], [47], (B) CROSS SECTION THROUGH A STRUCTURE USING

AMORPHOUS SILICON ON TOP OF STANDARDCMOS VLSI ELECTRONICS

[48], [49].

- CMOS on SOI (non-standard)In order to exploit high resistivity bulk material, theauthors of [47] develop pixel sensors with full CMOScircuitry using the Silicon-on-Insulator (SOI) technology.The connection to the charge collecting bulk is doneby vias (fig. 12(a)). The technology offers full chargecollection in 200–300µm high resistive silicon with fullCMOS electronics on top. At present the technology ishowever definitely not a commercial standard and thedevelopment is still in its beginnings.

- Amorphous silicon on standard CMOS ASICsHydrogenated amorphous-Silicon (a-Si:H), where theH-content is up to 20%, can be put as a film on topof CMOS ASIC electronics. a-Si:H has been studiedas a sensor material long ago and has gained interestagain [48], [49] with the advancement in low noise, lowpower electronics. The signal charge collected in the<30µm thick film is in the range of 500-1500 electrons.A cross section through a typical a-Si:H device is shownin fig. 12(b). From a puristic view it is more a hybridtechnology, but the main disadvantage of the hybridizationconnection is absent. The radiation hardness of thesedetectors appears to be very high>1015cm−2 due tothe defect tolerance and defect reversing ability of theamorphous structure and the larger band gap (1.8 eV).The carrier mobility is very low (µe = 2-5 cm2/Vs, µh =0.005 cm2/Vs), i.e. essentially only electrons contribute tothe signal. Basically any CMOS circuit and IC technologycan be used and technology changes are uncritical forthis development. For high-Z applications poly-crystallineHgI2 constitutes a possible semiconductor film material.The potential advantages are small thickness, radiationhardness, and low cost. The development is still in itsbeginnings and – as for CMOS active pixel sensors – areal challenge to analog VLSI design.

- Amplification transistor implanted in high resistivity bulkIn so-called DEPFET pixel sensors [50] a JFET or MOS-

FET transistor is implanted in every pixel on a sidewardsdepleted [56] bulk. Electrons generated by radiation in thebulk are collected in a potential minimum underneath thetransistor channel thus modulating its current (fig. 13). Thebulk is fully depleted rendering large signals. The smallcapacitance of the internal gate offers low noise operation.Both together can be used to fabricate thin devices. Thesensor technology is non-standard and the operation ofDEPFET pixel detectors requires separate steering andamplification ICs (see below).

Fig. 13

PRINCIPLE OF OPERATION OF ADEPFETPIXEL STRUCTURE BASED ON A

SIDEWARDS DEPLETED DETECTOR SUBSTRATE MATERIAL WITH AN

IMBEDDED PLANAR FIELD EFFECT TRANSISTOR. CROSS SECTION(LEFT) OF

HALF A PIXEL WITH SYMMETRY AXIS AT THE LEFT SIDE , AND POTENTIAL

PROFILE(RIGHT).

Because CMOS active pixels and DEPFET pixels are mostadvanced in their development, they are discussed in moredetail below.

A. CMOS Active Pixels

The main difference of CMOS monolithic active pixel sen-sors [40] to CMOS camera chips is that they are larger inarea and must have a 100% fill factor for efficient particledetection. Standard commercial CMOS technologies are usedwhich have a lightly doped epitaxial layer between the lowresistivity silicon bulk and the planar processing layer. Theepi-layer is – technology dependent – at most 15µm thick andcan also be completely absent. Collaborating groups aroundIReS&LEPSI [42], [43], RAL [44] and Irvine-LBNL-Ohio [45]use similar approaches to develop large scale CMOS activepixels also called MAPS (Monolithic Active Pixel Sensors)[41]. Prototype detectors have been produced in0.6µm,0.35µmand0.25µm CMOS technologies [54], [52].

In the MAPS device (fig. 11(b)) electron-hole pairs createdby ionization energy loss in the epitaxial layer remain trappedbetween potential barriers on both sides of the epi-layer andreach, by thermal diffusion, an n-well/p-epi collection diode.The sensor is depleted only directly under the n-well collectiondiode where full charge collection is obtained; the chargecollection is incomplete in all other areas. With small pixel cellscollection times in the order of100ns are obtained. The signal

is small, some hundred to 1000e, depending on the thicknessof the epi-layer. A chip submission using a process with noepi-layer, but with a low doped substrate of larger resistivityhas also been tried (MIMOSA-4) [53] which proved to functionwith high detection efficiency for minimum ionizing particles.This renders the uncertainty and dependence on the future oftheepi-layer thickness in different technologies less constraining.

Matrix readout performed using a standard 3-transistor cir-cuit (line select, source-follower stage, reset) commonlyem-ployed by CMOS matrix devices, but can also include cur-rent amplification and current memory [54]. For an imagetwo complete frames are subtracted from each other (CDS)which suppresses switching noise. Noise figures of 10-30e andS/N ∼20 have been achieved with spatial resolutions below5µm. The radiation hardness of CMOS devices is always acrucial question for particle detection in high intensity colliders.MAPS appear to sustain non-ionizing radiation (NIEL) to∼1012neq while the effects of ionizing radiation damage (IEL)are at present still unclear [55]. Apart from this the focus offurther development lies in making larger area devices andin increasing the charge collection performance in the epi-layer. For the former, first results in reticle stitching, that iselectrically connecting IC area over the reticle border, havebeen encouraging (fig. 14(a)) [52]. Full CMOS stitching overthe reticle boarder still has to be demonstrated. The poor chargecollection by thermal diffusion is another area calling forideas.Approaches using more than one n-well collecting diode [44], aphoto-FET [54], [42], [43], or a photo-GATE [46] are currentlyinvestigated. The photo-FET called technique (fig. 14(b)) hasfeatures similar to those of DEPFET pixels (see below). ApMOS FET is implanted in the charge collecting n-well andsignal charges affect its gate voltage and modulate the transistorcurrent.

Fig. 14

(A) SEAMLESS STITCHING IN BETWEEN WAFER RETICLES TO OBTAIN

LARGE AREA CMOSACTIVE PIXELS, (B) SCHEMATIC OF A PMOS

PHOTO-FETTO IMPROVE CHARGE COLLECTION INMAPS.

Above all, the advantages of a fully CMOS monolithic devicerelate to the adoption of standard VLSI technology and itsresulting low cost potential (potentially∼25$ per cm2). In turnthe disadvantages also come largely from the dependence oncommercial standards. The thickness of the epi-layer varies for

different technologies. It becomes thinner for smaller processesand with it also the number of produced signal electronsvanishes. Only a few processing technologies are suited. Withthe rapid change of commercial process technologies this isanissue of concern. The fact that good detector performance hasbeen seen with non-epi wafers material provides some relief.Furthermore, in the active area, due to the n-well collectiondiode, no CMOS (only nMOS) circuitry is possible. The voltagesignals are very small (∼mV), of the same order as transistorthreshold dispersions requiring very low noise VLSI design.The radiation tolerance of CMOS pixel detectors for particledetection beyond 1012 neq is still a problem although theachieved tolerance should be sufficient for a Linear Collider.Improved readout concepts and device development for highrate particle detection at a linear collider is under development[38]. For the upgrade of the STAR microvertex detector the useof CMOS active pixels is planned [54].

B. DEPFET Pixels

The Depleted Field Effect Transistor structure (DEPFET)[50] provides detection and amplification properties jointly andhas been experimentally confirmed and successfully operated assingle pixel structures and as large (64x64) pixel matrices[51].The DEPFET detector and implanted amplification structure isshown in fig. 13. Sidewards depletion [56] provides a parabolicpotential which has – by appropriate biasing and a so-calleddeep-n implantation – a local minimum for electrons (∼ 1µm)underneath the transistor channel. The channel current canbesteered and modulated by the voltage at the external gate and- important for the detector operation - also by the deep-n potential (internal gate). Electrons collected in the internalgate are removed by a clear pulse applied to a dedicatedCLEAR contact outside the transistor region or by other clearmechanisms. The very low input capacitance (∼ few fF) andthe in situ amplification makes DEPFET pixel detectors veryattractive for low noise operation [57]. Amplification values of400 pA per electron collected in the internal gate have beenachieved. Further amplification enters at the second level stage(current based readout chip).

DEPFET pixels are currently being developed for three verydifferent application areas: vertex detection in particlephysics[58], [59], X-ray astronomy [60] and for biomedical autoradio-graphy [57]. Figure 15 summarizes the achieved performancein noise and energy resolution with single pixels structures (fig.15(a)) and in spatial resolutions with 64x64 pixels matrices (fig.15(b)). With round single pixel structures noise figures of 2.2eat room temperature and energy resolutions of 131 keV for 6keV X-rays have been obtained. With small (20x30µm2) linearstructures fabricated for particle detection at a Linear Colliderthe noise figures are about 10e. The spacial resolution read offfrom fig. 15(b) in matrices operated with 50 kHz line rates is[59]

σxy = (4.3 ± 0.8)µm or 57 LPmm

for 22 keV γ

σxy = (6.7 ± 0.7)µm or 37 LPmm

for 6 keV γ

The capability to observe tritium in autoradiographical ap-plications is shown in fig. 15(c).

Fig. 15

(A) RESPONSE OF A SINGLEDEPFETPIXEL STRUCTURE TO6KEV X- RAYS

FROM AN 55FE SOURCE, (B) IMAGE OBTAINED WITH 55FE AND A TEST

CHART, THE SMALLEST STRUCTURES HAVE A PITCH OF50µM AND ARE

25µM WIDE , (C) 3H LABELLED LEAF.

The very good noise capabilities of DEPFET pixels are veryimportant for low energy X-ray astronomy and for autora-diography applications. For particle physics, where the signalcharge is large in comparison, this feature is used to designvery thin detectors (∼50µm) with very low power consumptionwhen operated as a row-wise selected matrix [59]. Thinning ofsensors to a thickness of 50µm using a technology based ondeep anisotropic etching has been successfully demonstrated[61]. For the development of DEPFET pixels for a LinearCollider matrix row rates of 50 MHz and frame rates for520x4000 pixels of 25 kHz, read out at two sides, are targeted.Sensors with cell sizes of 20x30µm2 have been fabricated andcomplete clearing of the internal gate, which is important forhigh speed on-chip pedestal subtraction, has been demonstrated[59]. A large matrix is readout using sequencer chips for rowselection and current based chip for column readout [59]. Bothchips have been developed at close to the desired speed fora Linear Collider. The estimated power consumption for afive layer DEPFET pixel vertex vertex detector is only 5Wrendering a very low mass detector without cooling pipesfeasible. The most recent structures use MOSFETs as DEPFETtransistors for which the radiation tolerance still has to beinvestigated.

VI. SUMMARY

Driven by the demands for high spatial resolution and highrate particle detection in high energy physics, semiconductorpixel detectors have started to also become exploited forimaging applications. Hybrid pixel detectors, in which sensorand electronic chip are separate entities, connected via bumpbonding techniques represent today’s state of the art for both,particle detection and imaging applications. New trends includeinterleaved pixels having different pixel- and readout-pitches,MCM-D structures and 3D-silicon detectors with active edges.

Monolithic or semi-monolithic detectors, in which detector andreadout ultimately are one entity, are currently developedinvarious forms, largely driven by the needs for particle detectionat future colliders. CMOS active pixel sensors using standardcommercial technologies on low resistivity bulk and SOI pixels,a-SI:H, and DEPFET-pixels, which try to maintain high bulkresistivity for charge collection, classify the differentways tomonolithic detectors which are presently carried out.

ACKNOWLEDGMENT

The author would like to thank W. Dulinski, M. Caccia, P.Jarron, P. Russo, C. da Via’, and S. Parker for providing newmaterial and information for this presentation.

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