TransmissionGate

8/10/2019 TransmissionGate

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Elmore Delay (HO)

Application of Elmore Delay to Mux Design (Ex.

7.4)

Logical Effort of CMOS Transmission Gate (

Dynamic D-Latch

Dynamic Logic


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Distributed RC line as a lumped RC

Ladder


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Lumped


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NMOS TG as a D-Latch

CLK=1, Q=DCLK=1 0, Qlastis stored on C2CLK=0, high impedance state.


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Problems with NMOS TG

1. Q can only rise to VDD-VT2. Clock feedthrough at Q when CLK goes low

3. The output stored in a high-Z stage after

CLK goes low is susceptible to all of the charge loss

mechanisms.

4. is not available


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CMOS TG as a latch

1. Q can only rise to VDD-VT2. Clock feed through at Q when CLK goes low

3. The output stored in a high-Z stage afterCLK goes low is susceptible to all of the charge

loss

mechanisms.

4. is not available


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CMOS TG with a

1. Q can only rise to VDD-VT2. Clock feed through at Q when CLK goes low

3. The output stored in a high-Z stage afterCLK goes low is susceptible to all of the charge

loss

mechanisms.

4. is not available


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Use feedback to statically hold the

logic value when the latch is off (1)

We can NOT drive a load from internal Q


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Use feedback to statically hold the

logic value when the latch is off (2)


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No Feedback when the latch is ON


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Problem & Solution

CLK

Problem: If D and Qprevare different:

Driver + TG1 will drive Q to a different

value while INV2 and NMOS of TG2 will

drive Q to Qprev

Solution: Size the forward path so that it is stronger than the feedback path.


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Adjust VS

Knob:

as defined in EQ. 4.15

Increase(WNLP)/(LNWP) Decreased VS.

Decrease(WNLP)/( LNWP) Increased VS.


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Increase WP to adjust VS

WN/LN=200nm/200nm

WP/LP=200nm/200nm

WN/LN=200nm/200nm

WP/LP=460nm/200nm


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Typical D-Latch Implementation in

CMOS


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CMOS

CLK=1

10


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CMOS

CLK=0

Qprev=1

10


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CMOS

CLK

Qnow=0

Qprev=1

1 0

Optional


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CMOS

CLK

Qnow=1

Qprev=00 1

Node X may have difficulty transitioning to 1 until

is 0.Optional


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Schematic of a TG Based D latch


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Simulation of D-Latch


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Zoom in to a transition


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Positive Edge D Flip-flop

D is only transmitted to the output on the rising edge of CLK


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Positive Edge D FF (CLK=0)


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Positive Edge D FF (CLK=1)


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Dynamic NAND

CLK=0 (Pre-Charged Phase)

NMOS is OFF. OUT is charged to VDD.

CLK=1 (Logic Evaluation Phase)NMOS is ON.

If either A or B is GND, OUT=VDD.

If A=B=1, OUT=GND

Precharge Phase is only a small portion of the

clock cycle.

Disadvantage:

All dynamic logic circuits require a clock.


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General Structure of a Dynamic Gate

Disadvantage:

All dynamic logic circuits require a clock


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Examples

Example 7.6

P7.5 (a)

P7.5 (b)


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Problem of Domino Logic Gates

1. During the precharge phase, the output voltage is high.

2. There is an active path to ground as soon as the foot transistor is turned on.

3. Once an output node has been discharged, it cannot go high until the next prechargephase.


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Solution

1. Define each stage as a dynamic gate plus aninverter.

2. The output of each stage is now 0during precharge.

Therefore all NMOS transistors are off during

precharge and can only be turned on during the

evaluation phase.

Disadvantage: An inverter can not be created!


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Domino Cascaded Gates

During the pre-charge phase (=0), Y1, Y2 and Y3 are charged to VDD simultaneously.

=0 does not have to last very long since all stages are pre-charged simultaneously.

has a high duty cycle.

Note: There is no direct current from VDD to GND.


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Exercise

c

b

a

clk

clk

VDD

OutX


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Solution:

Out A BC

1. NMOS network implements

while X implements OUT.

2. The output of Inverter implements


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Implement the expression

Out AB BC C


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Solution

a

b

c

b

clk

clk

VDD

Out

c


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Propagation Delay of Domino

Cascaded Gates

The propagation delay is determined by:

1. The falling edge of the dynamic block

2. The rising edge of the inverter

Y1,Y2and Y3fall like dominos.


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Improve the Rise Time of an Inverter

Design a static inverter with strong pull-up

Increase the size of the PMOS device.

DecreaseWNLP/LNWP Increased Vsof the inverter

StaticInverter

Domino

Gate


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Logical Effort Comparison

5/3 2/3 assuming that CLK is does not

arrive prior to either A or B


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Dynamic NOR Gate

The Dynamic NOR gate is a faster circuit

because only one NMOS device is driven

The pull-down transistors do not fight with the

pull-up devices.


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Limitations of Domino Logic

Charge Sharing

Vx(initially)=0

V*=(Cout)/(Cx+Cout)VDD


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Minimizing the effect of Charge

Sharing Using Keepers

The keepers keep VX at VDD and reduce

charge sharing to minimum. The keeper

transistor is weak enough (small W/L ratioby using a large L) that when X=VDDGND.

NMOS can prevail over weak PMOS.

Disadvantage: large driver requirement of IN

Keepers

X


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Enhancement

The INV sees a minimum length device.

The effective pull-up strength is controlled

by the long device.

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