Towards High-Throughput with Low-Effort Programming: From General-Purpose Manycores to Dedicated Circuits

J. Andrade1, G. Falcao1, V. Silva1, M. Owaida2, C. Antonopoulos2,

N. Bellas2 and P. Ienne3 1Instituto de Telecomunicações, University of Coimbra, Portugal; 2Dept. of Computer and Communications Engineering, University of Thessaly, Greece; 3École Polytechnique Fédérale de Lausanne, Switzerland Abstract Parallel programming models, such as OpenCL, have emerged in the recent past to bring GPU application development effort at par with conventional CPU programming. The higher throughputs achieved have benefited a wide realm of scientific applications. However, even though from CPUs to GPUs the computational power-to-watt-ratio is substantially higher, there subsists a large spectrum of applications that cannot enjoy the benefits of manycore execution due to the power consumption incurred. While RTL design typically requires long development times, OpenCL to RTL translation tools have been developed to assist and ameliorate the programming effort required to target FPGA accelerators. The profits of FPGA design using OpenCL models are tremendous, as kernels can be developed in a unified parallel programming model. We analysed a dataset of short- and long-block LDPC decoders to quantify the throughput-to-effort achieved by extending the OpenCL portability to FPGAs. Also, we identified a series of challenges to be tackled in the near future in order to convey low effort designs to the high throughput levels achieved with dedicated RTL.

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Linear Block Code: Parity Equations, Tanner Graph and Belief-Propagation

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c0+c3+c6=0

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Initialization

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