Published: January 10, 2011

r 2011 American Chemical Society 767 dx.doi.org/10.1021/nl103977d |Nano Lett. 2011, 11, 767–771

LETTER

pubs.acs.org/NanoLett

Toward Intrinsic Graphene Surfaces: A Systematic Study onThermal Annealing and Wet-Chemical Treatment of SiO2-SupportedGraphene DevicesZengguang Cheng, Qiaoyu Zhou, Chenxuan Wang, Qiang Li, Chen Wang,* and Ying Fang*

National Center for Nanoscience and Technology, 11 Beiyitiao Street, Zhongguancun, Beijing 100190, People's Republic of China

bS Supporting Information

ABSTRACT: By combining atomic force microscopy and trans-port measurements, we systematically investigated effects ofthermal annealing on surface morphologies and electrical proper-ties of single-layer graphene devices fabricated by electron beamlithography on silicon oxide (SiO2) substrates. Thermal treatmentabove 300 �C in vacuum was required to effectively remove resistresidues on graphene surfaces. However, annealing at hightemperature was found to concomitantly bring graphene in closecontact with SiO2 substrates and induce increased coupling between them, which leads to heavy hole doping and severe degradationof mobilities in graphene devices. To address this problem, a wet-chemical approach employing chloroform was developed in ourstudy, which was shown to enable both intrinsic surfaces and enhanced electrical properties of graphene devices. Upon the recoveryof intrinsic surfaces of graphene, the adsorption and assisted fibrillation of amyloidβ-peptide (Aβ1-42) on graphenewere electricallymeasured in real time.

KEYWORDS: Graphene, electrical properties, thermal annealing, wet-chemical treatment, sensor

Graphene, a distinct two-dimensional building block, hasattracted enormous research interest due to its superb

physical properties and future promise in nanoelectronics.1-6 Gra-phene is in general integrated into devices by lithography on standardSiO2 substrates, but exposure to resist polymers during fabricationprocesses inevitably contaminates hydrophobic graphene surfaceswith resist residues which cannot be removed by standard solventssuch as acetone or Remover PG.7-9 Former studies have shown thatresist residues can act as external scattering centers and degradetransport properties in single-layer graphene whose atoms are allexposed directly to extrinsic impurities.8,10-12 In order to exploreapplication potentials of graphene-based devices, facile and reliablemethods for producing clean graphene surfaces are of centralimportance. Thermal annealing has been investigated as a commonmethod to eliminate contamination and restore clean surfaces ofgraphene.7,8,13-16Nevertheless, a wide range of annealing conditionshave been reported along with diverse thermal effects on graphenedevices, and a deep understanding of interaction between grapheneand its local environment during processing is still lacking and highlydesired. In this study, we carried out a systematic study of ther-mal effects on graphenedevices. Although annealing above 300 �C invacuum can eliminate resist residues on graphene surfaces, itsimultaneously brings graphene in close contact with corru-gated SiO2 substrates and accordingly induces large perturbationto electrical properties of graphene devices. On the other hand,wet-chemical treatment with chloroform was found to be effec-tive in both restoring intrinsic surfaces and improving electricalperformances of graphene devices.

Graphene flakes were deposited through mechanical exfolia-tion of natural graphite on silicon substrate coated with 285 nmof SiO2.

2,17 The height of freshly cleaved single-layer graphene istypically 0.6-0.8 nm on SiO2 (Figure S1, Supporting In-formation). E-beam lithography on poly(methyl methacrylate)(PMMA) resist and subsequent thermal evaporation were in-troduced to pattern 5 nm Cr/100 nm Au electrodes of graphenefield effect transistors (FETs). After lift-off, graphene deviceswere first ultrasonicated in acetone for 10 min before character-ization. Figure 1a shows the topographic imaging by tappingmode atomic force microscopy (AFM) on a typical single-layergraphene device. The height of the graphene sheet increased to∼1.5 nm after fabrication due to a thin resist film covering thesurface of the graphene device.8 The root-mean-square (rms)surface roughness of the graphene sheet was measured to be0.54 nm whereas the SiO2 substrate gave a much smoothersurface with a rms roughness of 0.17 nm, which shows that thehydrophobic surface of graphene is more susceptible to resistcontamination than SiO2 and standard acetone cleaning cannotcompletely remove resist residues due to their strong van derWaals interaction with graphene. We believe that the uncontrol-lable surface covering of resist from fabrication is partly respon-sible for the large variation of reported properties in graphenedevices.8,12,13

Received: November 12, 2010Revised: January 3, 2011

768 dx.doi.org/10.1021/nl103977d |Nano Lett. 2011, 11, 767–771

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To examine effects of thermal treatment, graphene deviceswere sequentially annealed from 100 to 400 �C in vacuum witheach anneal being 3 h in duration. As shown in the AFMtopographic image of Figure 1b, resist contamination cannotbe effectively removed at 200 �C although the height and the rmssurface roughness of the graphene sheet decreased to 1.1 and0.42 nm, respectively, due to the partial desorption of resist residuesby annealing. After thermal treatment at 300 �C for 3 h, most of theresist residues were removed from the graphene surface, which thusgave a much smoother graphene surface with a rms roughness of0.20 nm (Figure 1c). Notably, the height of the graphene sheet afterannealing at 300 �C was measured to be only 0.4 nm, even lowerthan freshly transferred single-layer graphene before any fabricationprocessing (Figure S1, Supporting Information). We further in-creased the annealing temperature to 400 �C, which resulted incomplete removal of resist contamination from the graphene surfaceand a further reduced rms roughness of 0.15 nm (Figure 1d andFigure S2, Supporting Information). Surprisingly, the graphene sheetis now hardly discernible from the SiO2 substrate in the AFMtopographic imaging, indicating that either the height of the graphenesheet is below the detection limit of our AFM equipment or theirsurface roughness obscures the difference between graphene andthe SiO2 substrate. We note that similar results with the height ofgraphene sheets below resolution were reproduced on other gra-phene devices after annealing at 400 �C in vacuum (Figure S3,Supporting Information). The interlayer distance in bulk graphite is∼0.3 nm, and the larger height of 0.6-0.8 nmmeasured from freshlyprepared single-layer graphene has been attributed to a “dead” spacebetween graphene and SiO2 substrates.

2 Thus, our results show thatannealing above 300 �C in vacuum compresses the “dead” space andbrings graphene to close contact with SiO2 substrates.

The effects of thermal treatment on electrical properties of thesame graphene device are summarized in Figure 2. The two-probemobilities of the as-made graphene transistor gated through SiO2

were estimated based on the capacitance model,18 which resulted in

2000 and 1600 cm2/(V s) for holes and electrons, respectively. TheDirac point, the point of minimum conductivity, of the device settlesat a back gate voltage of 48 V (Figure 2a), which is due to dopingeffects from both the SiO2 substrate and the PMMA surface layer.Upon annealing at medium temperatures of 100 and 200 �C, theDirac point of the graphene device shifts toward 0 V due to partlyevaporated absorbents (PMMA residues and trapped absorbents bythe PMMA) from the graphene surface. Further, the mobilities forboth hole and electron carriers increased with annealing (Figure 2b),indicating improved electrical properties by reduced surface contam-ination of the graphene device.11 After annealing at 300 �C, mostresist residues on the graphene surface were removed as shown inFigure 1c; however, the mobilities of the graphene device started todegrade and its Dirac point shifted positively again. Heavy holedoping and seriously degraded carrier mobilities of graphene deviceswere observed after thermal treatment at 400 �C (Figure 2 andFigure S3, Supporting Information).13,14 Thus the optimal electricalperformance of graphene devices does not concur to the situationwith the cleanest graphene surfaces by thermal annealing.

To illustrate the degraded electrical performance in graphenedevices after thermal treatment, we then carried out Ramanspectroscopy to probe structural and doping characteristics ofgraphene. Figure 3 highlights Raman results from a graphenedevice before thermal treatment and after annealing at 400 �C.First, the absence of any defect-related D-band at ∼1350 cm-1

Figure 1. Thermal annealing effects on surface morphologes of gra-phene. (a) AFM topographic image of a graphene device before anythermal treatment. The height of the graphene sheet is 1.5 nm as shown inthe height profile along the dashed blue line. The rms surface roughness of0.54 nm was acquired on a 1� 1 μm2 scan window highlighted by the redbox. The scale bar is 1μm. (b-d) AFM images of the same graphene deviceafter thermal annealing in vacuum at 200 �C (b), 300 �C (c), and 400 �C(d), respectively. The height (h) and rms surface roughness (Ra) of thegraphene sheetweremeasured to be: h=1.1 nmandRa = 0.42nm(200 �C),h = 0.40 nm and Ra = 0.20 nm (300 �C), Ra = 0.15 nm (400 �C),respectively. Scale bars represent 1 μm.

Figure 2. Thermal annealing effects on electrical properties of graphene.(a) Annealing temperature dependence of conductance vs back gate voltage(Vg) characteristics. The source-drain voltage was biased at 0.03 V in dcmode and measurements were taken under ambient conditions right afterannealing. (b) Calculated two-probe mobilities of the graphene device as afunction of the annealing temperature. After annealing at 400 �C, the Diracpoint of the graphene devicewas above 65V and out of the safe sweep rangeof the gate voltage applied through 285 nm of SiO2.

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shows that there is no damage to the sp2 hybridized carbonstructure of graphene by thermal treatment in vacuum even up to500 �C (Figure S4, Supporting Information). Second, G and 2Dbands of the graphene sheet drastically blue-shifted 12 and10 cm-1, respectively, after thermal treatment at 400 �C.Blue-shifted Raman bands can be caused by either compressivestrain or hole-doping in graphene.19-21 The thermal expansioninduced strain to graphene in our temperature range is estimatedto be ∼0.3%,22 which cannot account for the large Raman bandshifts here. Further, former studies have shown that strain-induced shift of the G band would be ∼2 times smaller thanthat of the 2D band, which is inconsistent with our results.20 Wethus attribute the blue-shifted G and 2D bands in Figure 3 toa high level of hole doping in the graphene device and thecorresponding hole concentration in graphene is estimated tobe ∼1 � 1013/cm2 after thermal annealing at 400 �C.19

From our correlated AFM, transport, and Raman results, wecan conclude that (1) standard solvents such as acetone cannoteliminate PMMA resist residues from graphene surfaces, (2) nodefects are introduced to activate the D band of graphene bythermal treatment in vacuum up to 500 �C, (3) annealing above300 �C is required to effectively remove resist residues ongraphene surfaces, and (4) annealing above 300 �C in vacuuminduces increased coupling between graphene and corrugatedSiO2 substrates, which leads to both heavy hole doping and

severe degradation of electrical properties in graphene devices.We note that the mechanism of heavy hole doping in annealeddevices is not clear at this stage. Increased charge transfer withunderlying SiO2 substrates might contribute to the hole dopingin graphene,23 although former studies also indicate that hightemperature annealing can assist the adsorption of H2O and O2

molecules on graphene and result in hole doping.15

To address problems associated with thermal treatment, wefurther investigated wet-chemical approaches based on strongsolvents for PMMA to effectively clean graphene devices withoutcompromising their electrical properties. Chloroform was cho-sen to treat graphene devices because, as a common solvent,chloroform has high dissolvability for PMMA and is misciblewith traditional lithography solvents such as acetone and 2-pro-panol. AFM topographic imaging of a typical graphene deviceafter chloroform cleaning and subsequent 2-propanol rinsing ispresented as the inset in Figure 4, which shows that the surface ofthe graphene sheet is now clear of resist residues and its rmsroughness accordingly reduces to 0.16 nm. The height of theexposed graphene sheet was measured to be ∼0.7 nm on SiO2

substrate, comparable to freshly cleaved single layers.Electrical measurements of the same graphene device before

and after chloroform cleaning are also summarized in Figure 4.The black curve shows the conductance of the device, with onlyacetone cleaning, plotted against the applied back gate voltage,which gives a Dirac point at 38 V and two-probe mobilities of1700 and 1600 cm2/(V s) for holes and electrons, respectively.After chloroform treatment, the Dirac point of the device shiftedto close to 0 V as illustrated by the red curve in Figure 4,indicating substantially reduced hole doping in the graphenedevice. Importantly, the two-probe mobilities of the graphenedevice increased greatly to 3100 and 2700 cm2/(V s) for hole andelectron carriers, respectively. Thus, in contrast to thermalannealing, our facile wet-chemical treatment with chloroformcan render both intrinsic surfaces and improved electrical proper-ties of graphene devices (Figure S6, Supporting Information).

Self-assemblies of Aβ peptide are of central relevance to thepathology of Alzheimer’s disease, and their fibrillation has beenshown to be assisted by interaction with freshly cleaved surfacesof highly oriented pyrolytic graphite (HOPG).24,25 Grapheneshares identical honeycomb crystal lattice and similar surface

Figure 3. Raman characterization of graphene before and after annealing.(a) Raman spectra of a typical graphene device without any thermal treat-ment (black curve) and after annealing at 400 �C for 3 h in vacuum (redcurve). (b, c) Zoom-ins of RamanGband (b) and 2Dband (c), respectively.

Figure 4. Wet-chemical treatment of resist-contaminated graphene.Conductance vs back gate voltage characteristics of a typical graphene devicebefore (black) and after chloroform cleaning (red). The dc bias voltage wasset at 0.03 V, and the measurements were carried out under ambientconditions. Inset: AFM topographic image of the graphene device aftercleaning. The rms surface roughness of 0.16 nm was acquired in the areahighlighted by the red box. Scale bar represents 1 μm.

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properties with HOPG, thus Aβ peptides are expected to self-assemble into nanofibers on graphene with intrinsic surfaces.26

To demonstrate the capability of our wet-chemical approach,graphene FETs with recovered clean surfaces were applied tointerface directly with Aβ peptide molecules,27,28 and real-timeelectrical response to peptides from a typical graphene device issummarized in Figure 5. Upon switching to 2 μM Aβ1-42solution, the conductance of the graphene device started todecrease due to the capture of peptidemolecules on the graphenesurface, and the positively shifted Dirac point of the device showsthat Aβ1-42 molecules act as hole-dopants for graphene (FigureS5, Supporting Information). A total conductance change aslarge as 40% was achieved when the interaction between Aβ1-42and the intrinsic surface of graphene stabilized after∼100 min,29

and we note that the adsorption of Aβ1-42 on graphene surfacesis irreversible. AFM imaging after solution measurements con-firms that the fibrillation of Aβ1-42 was specific on graphenesurfaces and no fibers were observed on SiO2 substrates (Figure 5and Figure S7, Supporting Information).

In summary, we systematically investigated effects of thermalannealing and wet-chemical cleaning on surface morphologiesand electric properties of single-layer graphene devices sup-ported by SiO2 substrates. Although annealing at high tem-perature in vacuum can effectively remove resist residues ongraphene, it simultaneously brings graphene to close contact withcorrugated SiO2 substrates and leads to severe degradation ofelectrical performance in graphene devices. On the other hand,chloroform was shown to be an effective solvent to dissolve resistresidues on graphene and enable enhanced mobilities of gra-phene devices. This advance further allowed us to measure in realtime the electrical response of graphene devices to the adsorptionand specific fibrillation of Aβ-peptide onto clean graphenesurfaces, which opens up new opportunities for reliable inter-faces between graphene nanoelectronics and supramolecularself-assemblies.26

’ASSOCIATED CONTENT

bS Supporting Information. Description of methods andSupplementary Figures S1-S7. This material is available free ofcharge via the Internet at http://pubs.acs.org.

’AUTHOR INFORMATION

Corresponding Author*E-mail: wangch@nanoctr.cn, fangy@nanoctr.cn.

’ACKNOWLEDGMENT

C.W. acknowledges support of this work by the Foundation ofCAS (KJCX2.YW.M15). Y.F. acknowledges support by the“973” Fund (2011CB932700) and the National Natural ScienceFoundation of China (20973045).

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Figure 5. Peptide adsorption on clean graphene device. After chloro-form cleaning, a poly(dimethylsiloxane) (PDMS) chamber was incor-porated on a chip with a graphene device to confine solutions and anonleak Ag/AgCl reference electrode was included as the electrolytegate. ThenH2O,H2O, and peptide solutions were sequentially deliveredto the surface of graphene. The conductance of the graphene device wasmonitored in real time as shown by the black curve, and arrows mark thepoints when solutions were changed. Inset, AFM topographic image ofthe graphene device after peptide adsorption.

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