Top 5 Eng'r Essentials Part_I

8/2/2019 Top 5 Eng'r Essentials Part_I

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Engineering

The Top

Compliments of

Essentials


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RogeR AllAn |Contributing EDitor [email protected]

Anever-ending parade of refinements to IC pack-aging gives engineers more choices than everto meet their design requirements. With moreradical approaches lurking on the horizon, thatmix will become even richer.

Today, though, squeezing more functionsinto smaller spaces at a lower cost dominates, leading design-ers to stack more chips atop each other. Thus, were seeing therapid ascent of 3D IC packaging.

The impetus behind 3D IC technologys rise comes from theconsumer markets use of more sophisticated interconnects to

connect silicon chips and wafers. These wafers contain chipswith continually shrinking line dimensions.

To scale down semiconductor ICs, finer line drawings aremade on 300-mm wafers. Although most mass-produced ICstoday are based on 55-nm design nodes or less, these designrules will shrink to 38 nm or smaller, and then down to 27 nmby 2013, according to forecasts by market forecaster VLSIResearch Inc. (Fig. 1).

These downscaled IC designs accelerate the need for high-density, cost-effective manufacturing and packaging tech-niques, which will invariably challenge IC manufacturers tominimize the higher cost of capital equipment investments.

Many 3D applications still use traditional ball-grid-array(BGA), quad flat no-lead (QFN), lead-grid-array (LGA), andsmall-outline transistor (SOT) packages. However, more aremigrating to two main approaches: fan-out wafer-level chip-scale packaging (WLCSP) and embedded-die packaging.

Presently, fan-out WLCSP is finding homes in high-pin-count (more than 120 pins) applications that use BGAs.Embedded-die technology favors the use of lower-pin-countapplications that embed chips and discrete components intoprinted-circuit-board (PCB) laminates and use microelectro-mechanical-system (MEMS) ICs (Fig. 2).

Researchers at Texas Instruments believe that WLCSP isheading toward a standardized package configuration. It couldinclude a combination of WLCSP ICs, MEMS ICs, and pas-sive components interconnected using through silicon vias(TSVs). The TSVs bottom layer can be an active WLCSPdevice, an interposer only, or an integrated passive interposer.The top layer may be an IC, a MEMS device, or a discrete

component (Fig. 3).No matter the package type, though, as pin counts and signal

frequencies increase, the need to pre-plan the package optionbecomes more critical. For example, a wire-bonded packagewith many connections may require more power-supply buf-fers on the chip due to high levels of inductance. The type ofbump, pad, and solder ball placement also can significantlyimpact signal integrity.

TSVs: Hype Or realiTy?TSV technology is not a packaging technology solution, per

se. Its simply an important tool that allows semiconductor dieand wafers to interconnect to each other at higher levels of den-sity. In that respect, its an important step within the larger ICpackaging world. But TSVs arent the only answer to 3D pack-aging advances. They represent just one part of an unfoldingarray of materials, processing, and packaging developments.

In fact, 3D chips that employ TSV interconnects arent yetready for large volume productions. Despite making someprogress, theyre limited to mainly CMOS image sensors,some MEMS devices, and, to some degree, power amplifiers.More than 90% of IC chips are packaged using tried-and-truewire-bonding means.

Speaking at this years ConFab Conference, Mario A. Bola-nos, manager of strategic packaging research and external

collaboration at Texas Instruments, outlined a number of chal-lenges facing the use of TSVs in 3D chips. These include a

3D IC TechnologyDelivers The Total Package

Burgeoning market demands for cost-effec-tive, higher-density smaller packages banktheir hopes on a flurry of recent advancesmade in materials, processing procedures,and interconnects, as well as a greater vari-ety of packaging approaches.

Wafer fabrication on advanced technology nodes

300-mmw

afer

forecast(thousan

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1200

1000

800

600

400

200

02009 2010 2011 2012 2013

>27 nm

>27 nm but


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lack of electronic design automation (EDA) tools, the need forcost-effective manufacturing equipment and processes, insuf-ficient yield and reliability data involving thermal issues, elec-tromigration and thermo-mechanical reliability, and compoundyield losses and known-good die (KGD) data.

Unlike conventional ICs, which are built on silicon waferssome 750 m thick, 3D ICs require very thin wafers, typicallyabout 100 m thick or less. Given the fragility of such verythin wafers, the need arises for highly specialized temporarywafer bonding and de-bonding equipment to ensure the integ-rity of the wafer structure, particularly at high processing

temperatures and stresses during the etching and metalliza-tion processes. After bonding, the wafer undergoes a TSVback-side process, followed by a de-bonding step. These typi-cal steps result in higher yield levels for more cost-effectivemass production.

Currently, theres a lack of TSV standards on bonding andprocess temperatures and related reliability levels. The sameis true regarding standardization of the TSV assignment ofwafer locations. If enough IC manufacturers work on theseissues, more progress can be made on expanding the roles ofTSVs for interconnects. High process temperatures greaterthan 200C to 300C arent feasible for the economic imple-mentation of TSVs.

Ziptronix Inc., which provides intellectual property (IP)for 3D integration technology, licensed its direct-bond-inter-connect (DBI) technology to Raytheon Vision Systems. Thecompany says that its low-temperature oxide bonding DBItechnology is a cost-effective solution for 3D ICs (Fig. 4).

Nevertheless, many semiconductor IC experts view theindustry at a crossroads of having to choose 2D (planar) and 3Ddesigns. They see a threefold to fourfold increase in costs whengoing from 45-nm design nodes to 32- and 28-nm designs,considering the fabrication, design, process, and mask costs.Much needed improvements in lithography and chemicalvapor polishing, as well as dealing with stress effects issues,

make the 3D packaging challenge even more difficult. This iswhere TSV technology steps in.

Frances Alchimer S.A., a provider ofnanometric deposition films used in semi-conductor IC interconnects, has demon-strated that TSVs with aspect ratios (heightto width) of 20:1 can save IC chipmakersmore than $700 per 300-mm wafer com-pared with aspect ratios of 5:1 (see thetable). This was accomplished by reducingthe die area need for interconnection.

Alchimer modeled TSV costs and spaceconsumption using an existing 3D stackfor mobile applications, The stack includ-ed a low-power microprocessor, a NANDmemory chip, and a DRAM chip madeon a 65-nm process node. The chips areinterconnected by about 1000 TSVs, andthe processor die was calculated for aspect

ratios of 5:1, 10:1, and 20:1.IBM, along with Switzerlands colePolytechnique Fdrale de Lausanne

(EPFL) and the Swiss Federal Institute of Technology (ETH),is developing micro-cooling techniques for 3D ICs, usingTSVs, by means of microfluidic MEMS technology (Fig. 5).The collaborative effort, known as CMOSAIC, is considering a3D stack architecture of multiple cores with interconnect den-sities ranging from 100 to 10,000 connections/mm2.

The IBM/Swiss team plans to design microchannels withsingle-phase liquid and two-phase cooling systems. Nano-surfaces will pipe coolants, including water and environmen-tally friendly refrigerants, within a few millimeters of the chip

to absorb the heat and draw it away. Once the liquid leaves thecircuit in the form of steam, a condenser returns it to a liquidstate, where its pumped back to the chip for cooling.

Wire BOnding and Flip CHipWire-bonding and flip-chip interconnect technologies cer-

tainly arent sitting idle. Progress marches on for a numberof flip-chip wafer-bumping technologies, including the useof eutectic flip-chip bumping, copper pillars, and lead-freesoldering. Recent packaging developments include the use ofpackage-on-package (PoP) methods, system-in-package (SiP),no-lead (QFN) packages, and variations thereof.

Fan-out WLP/chip embedding in substrates

3D ICwithTSV

Fan-outWLP

PCB

Flip-chip

Integratedpassive devices

3D WLP

MEMS

2. Future 3D IC packaging approaches will embody techniques such as wafer-level packaging

(WLP) using through-silicon vias (TSVs) together with embedding chips into various substrates.

(courtesy of Yol Dveloppment)

3. ICs, MEMS devices, and other components will be joined by passive

components using wafer-level chip-scale packaging (WLCSP) and through-silicon vias. (courtesy of Texas Instruments)

IC, MEMS, etc.

WLCSPwith TSV

Passive

EngineeringEssentials


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At the packaging level, 3D configurations have been wellknown for many years. Using BGA packages in stacked-dieconfigurations with wire bonds is nearly a decades-old prac-tice. For example, in 2003, STMicroelectronics demonstrated astack of 10 dice using BGAs, a record at the time.

Certain 3D approaches like the PoP concept warrant specialattention when it comes to high-density and high-functionality

handheld products. Designers must carefully consider twoissues: thermal cycling and drop-test reliability performance.Both are functions of the packaging materials quality andreliability. This becomes more critical as we move from inter-connect pitches of 0.5 mm to 0.4 mm for the bottom of the PoPstructure and 0.4 mm to 0.5 mm for the top.

Samsung Electronics Ltd. has unveiled a 0.6-mm high,multi-die, eight-chip package for use in high-density memoryapplications. Designed initially for 32-Gbyte memory sizes, itfeatures half the thickness of conventional eight-chip memorystacks and delivers a 40% thinner and lighter memory solu-

tion for high-density multimedia handsets and other mobiledevices, according to the company.

Key to the packages creation is the use of 30-nm NANDflash-memory chips, each measuring just 15 m thick. Sam-sung devised an ultra-thinning technology to overcome theconventional technology limits of an IC chips resistance toexternal pressure for thicknesses under 30 m. In addition, thenew packaging technology can be adapted to other multichippackages (MCPs) configured as SiPs and PoPs.

This packaging development provides the best solutionfor combining higher density with multifunctionality in cur-rent mobile product designs, giving designers much greaterfreedom in creating attractive designs that satisfy the diversestyles and thin-focused tastes to todays consumers, says TaeGyeong Chung, vice president for Samsungs package devel-opment team.

Market developments are also shaking up the QFN packagearena. Germanys Fraunhofer IZM has developed a chip-in-polymer process that imparts shock and vibration protectionto the chip and lends itself to shorter interconnect distances toenhance the chips performance. The process starts by thinningthe chip, then adhesively bonding it to a thin substrate.

This is all overlaid with resin-coated copper (about 80 mfor the resin layer and 5 m for the copper surface). The resin iscured, and interconnect vias are laser-drilled down to the con-tact pads and plated with a metal. Then the redistribution layeron top is etched from the copper.

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4. This set of memory die uses Ziptronixs direct-bond interconnect

(DBI) low-temperature oxide-bonding process for 3D ICs. The die arebonded face down to the face-up logic wafer and thinned to about 10 m.

Electrical contact between memory and logic elements is made via etching

memory and logic bond pads, followed by an interconnect metallization

over the memory die edge. (courtesy of Ziptronix)

SiliCon ConSumptionAS A FunCtion oF tSV ASpECt rAtio

tSV asec a 5:1 10:1 20:1

tSV sze (daee de, ) 40 20 20 200 10 200

Kee- aea(2.5 daee, )

100 50 2.5

ta tSV f (2) 7.9 2 0.5

F eave iC aea 12.3% 3.10% 0.80%

Average TSV density = 16 TSVs/mm2; die size = 8 8 mm

Courtesy of Alchimer S.A.

3Dstack

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TSV

5. Future 3D IC stacks may contain processor, memory, logic, and analog

and RF circuitry, all of which are interconnected with through-silicon vias

(TSVs). Liquids using MEMS microchannels will perform the cooling. This

is part of the CMOSAIC project, which involves IBM and two Swiss part-ners. (courtesy of the cole Polytechnique Fdrale de Lausanne)


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This process has been optimized incommercial production of standard pack-ages like QFNs, without the need forspecialized equipment or other delays.The use of polymer-embedded QFNs,essentially quad packs with no leadswith the leads being replaced by pads onthe chips bottom surface, is part of theHERMES project.

The goal of HERMES, which includes

Fraunhofer and 10 other European indus-

trial and academic organizations, is to

advance the embedding of chips and

components, both active and passive, to

allow for more functional integration and higher density. The

technology is based on the use of PCB manufacturing and

assembly practice, as well as on standard available silicon dies,highlighting fine-pitch interconnection, high-power capability,

and high-frequency compatibility.

The QFN package was selected because its more common in

small, thin appliances housing microcontroller ICs. Fraunhofer

researchers believe that QFNs will take over many application

niches held by other types of packages. The embedded QFN

contains a 5- by 5-mm chip thats thinned to about 50 m. The

package itself measures 100 by 100 mm. The 84 I/Os on the

chip are at a 100-m pitch (400 m on the package).

Malaysias Unisem Berhad has unveiled a high-density lead-frame technology, the leadframe grid array (LFGA), that offersBGA-comparable densities. The company says that it offers

a cost-effective replacement for a two-layer FPGA package.Compared to a QFN package, it has shorter wire-bond lengths.In addition, it can house a 10- by 10-mm, 72-lead QFN pack-age in a body size of 5.5 mm2.

This package offers a better footprint with higher I/O den-sity and better thermal and electrical performance. It is alsothinner and, most importantly, offers a much better yield atfront-end assembly, says T.L. Li, the packages developer.

Dai Nippon Printing has successfully embedded high-perfor-

mance IC chips that are wire-bonded to a printed wiring board

(PWB) inside a multi-layer PWB, citing unique buried bumped

interconnections for its success. PWBs interconnect between arbi-

trary layers (via hole connections) with bumps made of high-elec-trical-conductivity paste, which are formed by screen printing.

Half-etching the base metal of the leadframe and making itsinner leads longer will close the distance between the chip andthe leadframe its attached to, as well as drastically reduce theamount of gold wires for connections, resulting in lower manu-facturing costs (Fig. 6). Mass production of ICs with more than700 pins inside PWBs is scheduled for this year. Both activeand passive components can be handled.

Work is underway to develop epoxy flux materials that

improve the thermal-cycling and drop-test reliability short-

comings of conventional tin solder copper (SnAgCu). Such

materials will help to advance 3D ICs using PoPs. Although PoP

manufacturing employs commonly used tin-lead (SnPb) solderalloys, which offer advantages over SnAgCu materials, theres a

need for a lead-free compound to handle large high-density 3D

PoP structures for consumer electronics products.

The Henkel Corp. Multicore LF620 lead-free solder pastesuits a broad range of packaging applications. The no-cleanhalide-free and lead-free material is formulated with a newactivator chemistry, so it exhibits extremely low voiding inCSPs via in-pad joints, good coalescence, and excellent solder-ability over a range of surface finishes.

5


Gold wire Mold resin

Land Die pad Silicon chip

Gold wire

Silicon chip Die padLand

6. Dai Nippon Printing embedded high-performance IC chips can be wire-bonded to a printed wiring

board (PWB) inside a multi-layer PWB using unique buried bumped interconnections. Half-etching

the base metal of the leadframe and lengthening its inner leads shrinks the distance between the chip

and the leadframe its attached to. It also reduces the amount of gold wires for connections. (courtesy

of Dai Nippon Printing)

Dont Be IntimidatedBy Low-Power RF System Designlouis e. FRenzel |CommuniCAtionS EDitor [email protected]

Adding wireless connectivity to any producthas never been easy. However, even whena wireless solution doesnt seem to makesense, the potential exists. The cost is rea-sonable, and you add unexpected value and

flexibility to the product. But what if youarent a wireless engineer? Dont worry, because in many

cases, the wireless chip and module companies have madesuch connectivity a snap.

SeleCTing a TeCHnOlOgyThe table lists a marvelous collection of wireless options.

These technologies are all proven and readily available in chipor module form. No license is required since most operate in


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the unlicensed spectrum. They also operate under the rules andregulations in Part 15 of U.S. CFR 47. When considering wire-less for your design, you should have a copy of Part 15 handy.You can find it at www.fcc.gov.

The table only provides the main options and enough infor-mation to get you started. For a more in-depth look, check outthe organizations and trade associations associated with eachstandard.

Some of the wireless standards have relatively complex pro-tocols to fit special applications. For example, Wi-Fi 802.11is designed for local-area-network (LAN) connections and isrelatively easy to interface to Ethernet. It also is the fastest,except for Ultra-Wideband (UWB) and the 60-GHz standard.Its widely available in chip or module form, but its complexand may consume too much power.

ZigBee is great for industrial and commercial monitoring

and control, and its mesh-networking option makes it a goodchoice if a large network of nodes must be monitored or con-trolled. Its a complex protocol that can handle some sophis-ticated operations. Its underlying base is the IEEE 802.15.4standard, which doesnt include the mesh or other features,making it a good option for less complex projects.

If youre looking for something simple, try industrial, scien-tific and medical (ISM) band products using 433- or 915-MHzchips or modules. Many products require you to invent yourown protocol. Some vendors supply the software tools forthat task. Its a good way to go, because you can optimize thedesign to your needs rather than adapt to some existing overlycomplex protocol.

For very long-haul applications that require reliability,consider a machine-to-machine (M2M) option. These cell-phone modules use available cellular network data serviceslike GRPS or EDGE in GSM networks (AT&T and T-Mobile)or 1xRTT and EV-DO in cdma2000 networks (Sprint andVerizon). You will need to do the interfacing yourself and signup with a carrier or an intermediary company that lines up andadministers cellular connections. Though more expensive, thisoption offers greater reliability and longer range.

Cypress Semiconductors proprietary WirelessUSB option

operates in the 2.4-GHz band and targets human interface

devices (HIDs) like keyboards and mice. It offers

a data rate of 62.5 kbits/s and has a range of 10

to 50 m.

The Z-Wave proprietary standard fromSigma Design Zensys, used in home auto-mation, operates on 908.42 MHz in the U.S.and 868.42 MHz in Europe. It offers a rangeof up to about 30 m with data-rate options of9600 bits/s or 40 kbits/s. Mesh capability isin the mix, too (see Wireless In The Worksatwww.electronicdesign.com, ED Online21847).

Build VS. Buy

Deciding whether to build or buy is a crucialstep when it comes to adding wireless. Its gen-

erally a matter of experience.With less experience, itsprobably better to buy existingmodules or boards. With solidhigh-frequency or RF expe-rience, consider doing thedesign on your own. Almostalways, youll start with anavailable chip. The tricky part is the layout.

When self-designing, grab any reference designs available

from your chip supplier to save time, money, and aggravation.

Primary design issues will include antenna selection, imped-

ance matching with the antenna, the transmit/receive switch, thebattery or other power, and packaging. Most modules will take

care of these elements.

Factoring in the testing time and cost is another essential

design step. Any product you design will have to be tested to

conform to the FCC Part 15 standards. Arm yourself with the

right equipment, especially the spectrum analyzer, RF power

meters, field strength meter, and electromagnetic interference/

electromagnetic compliance (EMI/EMC) test gear with anten-

nas and probes. An outside firm also could perform the testing,

but thats expensive and takes time. Factor in some rework time

if you fail the tests. Most modules are pretested, so it pretty

much comes down to the packaging and interfacing with the rest

of the product.

COnSideraTiOnS and reCOmmendaTiOnSIf longer range and reliability are top priorities, stay with

the lower frequencies915 MHz is far better than 2.4 GHz,and 433 MHz is even better. This is strictly physics. The onlydownside is antenna size, which will be considerably greater atlower frequencies. Still, you wont be sorry when you need totransmit a few kilometers or miles. Though not impossible at2.4 GHz, it will require higher power and the highest possibledirectional gain antennas.

As for data rates, think slow. Lower data rateswill typically result in a more reliable link.You can gain distance by dropping the datarate. Lower data rates also survive better inhigh-noise environments.

Your analysis of the radiowave path isessential for a solid and reliable link. So, thefirst step should be to estimate your path loss.Some basic rules of thumb will give you agood approximate figure to use. Once youknow your path loss, you can play aroundwith things like transmitter power output,antenna gains, receiver sensitivity, and cablelosses to zero in on hardware needs. To esti-

mate the path loss between the transmitterand receiver, try:

1. The FreeWave MM2-HS-T 900-

MHz radio targets embedded

military and industrial applications.

2. Analog Devices ISM band radio

chips suit home automation and

control as well as smart-meteringapplications.


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dB loss = 37 dB + 20log(f) + 20log(d)

The frequency of operation (f) is in megahertz, and therange or distance (d) is in miles. Another formula is:

dB loss = 20log(4/) + 20log(d)

Wavelength () and range or distance are both in meters. Both

formulas deliver approximately the same figures. Remember,

this is free space loss without obstructions. The loss increases

about 6 dB for each doubling of the distance.

If obstructions are involved, some corrective figures must be

added in. Average loss figures are 3 dB for walls, 2 dB for win-

dows, and 10 dB for exterior structure walls.

When finalizing a path loss, add the fade margin. Thisfudge factor helps ensure good link reliability under severe

weather, solar events, or unusual noise and interference. As aresult, transmitter power and receiver sensitivity will be suf-ficient to overcome these temporary conditions.

A fade margin figure is just a guess. Some conservativedesigners say it should be 15 dB, while others say 10 dBis acceptable. If unusual weather or other conditions arentexpected, you may get away with less, perhaps 5 dB. Addthat to your path loss and adjust everything else accordingly.

Another handy formula to help estimate your needs is theFriis formula:

PR = PTGRGT2 /(162d2)

PR is the received power in watts, PT is the transmit power inwatts, GR is the receive antenna gain, GT is the transmit anten-na gain, is the wavelength in meters, and d is the distance inmeters. The transmit and receive gains are power ratios. Thisis 1.64 for a dipole or ground plane antenna. Any directionalantenna like a Yagi or patch will have directional gain. It isusually given in dB, but it must be converted to a power ratio.The formula also indicates why lower frequency (longer wave-length) provides greater range ( = 300/fMHz).

Transmitter output power, another key figure, is usually giv-en in dBm. Some common figures are 0 dBm (1 mW), 10 dBm(10 mW), 20 dBm (100 mW), and 30 dBm (1 W). Receiversensitivity also is usually quoted in dBm. This is the smallestsignal that the receiver can resolve and demodulate. Typical

figures are in the 70- to 120-dBm range.One last thing to factor in is cable loss. In most installations,you will use coax cable to connect the transmitter and receiverto the antennas. The cable loss at UHF and microwave fre-quencies is surprisingly high. It can be several dB per foot at2.4 GHz or more. So, be sure to minimize the cable length.

Also, seek out special lower-loss cable. It costs a bit more,but coax cable with a loss of less than 1 dB per foot is avail-able if you shop around. This is especially critical when usingantennas on towers where the cable run could be long. You

low-powEr, Short-rAngE wirElESS

tEChnologiES For DAtA trAnSmiSSion

Technology FrequencyMaxiMuM

rangeMaxiMuM raTe ModulaTion Main applicaTions

Bluetooth 2.4 GHz 10 m 3 Mbits/s FHSS/GFSK Cell headsets, audio, sensor data

IR 875 nm


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8 ElEctronic DEsign


can offset the loss with a gain antenna, but its still optimal tominimize the length and use the best cable.

With all of this information, compute the final calculation:

Transmit power (dBm) + transmit antenna gain (dB) + receiveantenna gain (dB) path loss (dB) cable loss (dB) fade

margin (dB)

This figure should be greater than the receiver sensitivity. Nowplay with all of the factors to zero in on the final specificationsfor everything. Two design issues remainthe antenna and itsimpedance matching.

The antenna requires a separate discussion beyond this arti-cle. There are many sources for antennas. A wireless module

most likely will come with an antenna and/or antenna sugges-tions. The most common is quarter-wave or half-wave vertical.When building an antenna into the product, the ceramic type ispopular, as is a simple copper loop on the printed circuit board(PCB). Follow the manufacturers recommendations for thebest results.

If its a single-chip design, you may need to design theimpedance matching network between the transceiver and theantenna. Most chip companies will offer some recommenda-tions that deliver proven results. Otherwise, design your ownstandard L, T, or LC network to do the job.

One final hint about testing: Part 15 uses field strength to

indicate radiated power measured in microvolts per meter(V/m). A field strength meter makes the measurement at

3. The CC2530 SoC from Texas Instruments fits 802.15.4, ZigBee, RF4CE, and smart-energy applications. It has an 8051 microcontroller on board,

making it a true single-chip wireless solution.

DigitalAnalogMixed

RESET_N

XOSC_Q2

XOSC_Q1

P2_4

P2_3

P2_2

P2_1

P2_0

P1_7

P1_6

P1_5

P1_4

P1_3

P1_2

P1_1

P1_0

P0_7

P0_6

P0_5

P0_4

P0_3

P0_2

P0_1P0_0

Reset

32-MHzcrystal oscillator

32.768-kHzcrystal oscillator

Debuginterface

Directmemoryaccess

ADCaudio/DC8 channels

USART 1

USART 2

Timer 1 (16 bits)

Timer 2(IEEE 802.15.4 MAC timer)

Timer 3 (8 bits)

Timer 4 (8 bits)

Watchdogtimer

High-speedRC oscillator

32-kHzRC oscillator

Clock multiplexerand calibration

8051 CPUcore

AES encryptionand decryption

On-chip voltageregulator

Power-on resetbrownout

Sleep timer

Sleep-mode controller

Memoryarbitrator

IRQ control

Radio registers

CSMA/CA strobe processor

Radio data interface

DemodulatorAutomatic

gaincontrol

Modulator

Receivechain

Frequency

synthesizer Transmit

chain

RF_P RF_N

32/64/128/256-kbyte flash

8-kbyte SRAM

Flash write

I/Oc

ontro

ller

FIFOa

ndframecontro

l

VDD (2 to 3.6 V)

DCOUPL


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specified distances. The result can be converted to watts toensure the transmitter is within the rules. The following for-mula, which is a close approximation, lets you convert betweenpower and field strength:

V2/120 PG/4d2

where P is transmitter power in watts, G is the antenna gain,V is the field strength in V/m, and d is the distance in metersfrom the transmit antenna to the field strength meter antenna. Asimplified approximation at a common FCC testing distance of3 m with a transmit antenna gain of one is P 0.3 V2.

SOme example prOduCTSFreeWave Technologies has a line of reliable, high-perfor-

mance spread-spectrum and licensed radios for critical datatransmissions. The high-speed MM2-HS-T (TTL interface)

and MM2-HS-P (Ethernet interface) come ready to embed inOEM products like sensors, remote terminal units (RTUs), pro-grammable logic controllers (PLCs), and robots and unmannedvehicles. They operate in the 900-MHz band and use direct-sequence spread spectrum (DSSS).

Thanks to the radios over-the-air speed of 1.23 Mbits/s,users can send significantly more data in a shorter period oftime. The MM2-HS-T is ideal for embedded applications thatrequire high data rates, such as video and long distances (upto 60 miles). Both radios fit many industry, government, andmilitary applications where its necessary to transmit largeamounts of data, including multiple high-resolution imagesand video along with data.

The MM2-HS-T measures 50.8 by 36 by 9.6 mm and weighs14 g (Fig. 1). The MM2-HS-P shares a similarly small foot-print. Both radios offer RISC-based signal demodulation witha matched filter and a gallium-arsenide (GaAs) FET RF frontend incorporating multi-stage surface-acoustic-wave (SAW)filters. The combination delivers unmatched overload immu-nity and sensitivity.

The MM2-HS-P includes industrial-grade high-speed Eth-ernet that supports TCP, industrial-grade wireless security, andserial communications. Each unit can be used in a security net-work as a master, slave, repeater, or master/slave unit, depend-ing on its programming. FreeWaves proprietary spread-spec-trum technology prevents detection and unauthorized access,and 256-bit AES encryption is available.

The ADF7022 and ADF7023 low-power transceivers fromAnalog Devices fit well in smart-grid and other applicationsoperating on the short-range ISM band for remote data mea-surement. Smart-grid technology not only measures how muchpower is consumed, it also determines what time and price arebest to save energy, reduce costs, and increase reliability for thedelivery of electricity from utility companies to consumers. RFtransceivers are needed for the secure and robust transmissionof this information over short distances, for storing measure-ment data, and for communicating with utility computers overwireless networks.

Applications for the ADF7022 and ADF7023 include indus-trial monitoring and control, wireless networks and telemetry

systems, security systems, medical devices, and remote con-trols. Analog Devices free, dowloadable ADIsimSRD DesignStudio supports both devices.

One particular hot area for RF transceivers involves utili-ties that are building advanced metering infrastructures,including automatic meter reading, to monitor and con-trol energy usage. Analysts expect more than 150 millionsmart meters to be installed worldwide. The ADF7022 andADF7023 target these smart-grid and home/building auto-mation applications.

The ADF7022 is a highly integrated frequency-shift-keying/Gaussian frequency-shift-keying (FSK/GFSK) transceiverdesigned for operation at the three io-homecontrol channels of868.25, 868.95, and 869.85 MHz in the license-free ISM band.It fully complies with ETSI-300-200 and has enhanced digitalbaseband features specifically designed for the io-homecontrolwireless communications protocol.

As a result, the device can assume complex tasks typicallyperformed by a microprocessor, such as media access, packetmanagement/validation, and packet retrieval to and from databuffer memory. This allows the host microprocessor to remainin power-down mode. Also, it significantly lowers powerconsumption and eases both the computational and memoryrequirements of the host microprocessor.

The ADF7023 low-IF transceiver operates in the license-free ISM

bands at 433, 868, and 915 MHz. It offers a low transmit-and-receive

current, as well as data rates in 2FSK/GFSK up to 250 kbits/s. Its

power-supply range is 1.8 to 3.6 V, and it consumes less power in

both transmit and receive modes, enabling longer battery life.

Other on-chip features include an extremely low-power,

8-bit RISC communications processor; patent-pending, fullyintegrated image rejection scheme; a voltage-controlled oscil-lator (VCO); a fractional-N phase-locked loop (PLL); a 10-bitanalog-to-digital converter (ADC); digital received signal-strength indication (RSSI); temperature sensors; an automaticfrequency control (AFC) loop; and a battery-voltage monitor.

The CC2530 from Texas Instruments is a true system-on-a-chip solution (SoC) tailored for IEEE 802.15.4, ZigBee, Zig-Bee RF4CE, and Smart Energy applications. (RF4CE is theforthcoming wireless remote-control standard for consumerelectronics equipment.) Its 64-kbyte and up versions supportthe new RemoTI stack for ZigBee RF4CE, which is the indus-trys first ZigBee RF4CE-compliant protocol stack.

Larger memory sizes will allow for on-chip, over-the-airdownload to support in-system reprogramming. In addi-tion, the CC2530 combines a fully integrated, high-perfor-mance RF transceiver with an 8051 MCU, 8 kbytes of RAM,32/64/128/256 kbytes of flash memory, and other powerfulsupporting features and peripherals (Fig. 3).

The TI CC430 wireless platform consists of TI radio chips.Also, the companys MSP430 16-bit embedded controllercan implement the IETF standard 6LoWPAN, which is thesoftware that enables 802.15.4 radios to carry IPv6 packets.Thus, low-power wireless devices and networks can access theInternet. Furthermore, the platform can implement Europes

Wireless MBus technology for the remote reading of gas andelectric meters.


10/23

10 ElEctronic DEsign


Electronic communications began as digital tech-

nology with Samuel Morses invention of thetelegraph in 1845. The brief dots and dashes ofhis famous code were the binary ones and zeroesof the current through the long telegraph wires.Radio communications also started out digitally,

with Morse code producing the off and on transmission ofcontinuous-wave spark-gap pulses.

Then analog communications emerged with the telephoneand amplitude-modulation (AM) radio, which dominated fordecades. Today, analog is slowly fading away, found only inthe legacy telephone system; AM and FM radio broadcasting;amateur, CB/family and shortwave radios; and some lingeringtwo-way mobile radios. Nearly everything else, including TV,

has gone digital. Cell phones and Internet communications aredigital. Wireless networks are digital.

Though the principles are generally well known, veteranmembers of the industry may have missed out on digital com-munications schooling. Becoming familiar with the basicsbroadens ones perspective on the steady stream of new com-munications technologies, products, trends, and issues.

THe FundamenTalSAll communications systems consist of a transmitter (TX),

a receiver (RX), and a transmission medium (Fig. 1). The TXand RX simply make the information signals to be transmittedcompatible with the medium, which may involve modulation.Some systems use a form of coding to improve reliability. Inthis article, consider the information to be non-return-to-zero

(NRZ) binary data. The medium could be copper cable likeunshielded twisted pair (UTP) or coax, fiber-optic cable, orfree space for wireless. In all cases, the signal is greatly attenu-ated by the medium and noise is superimposed. Noise ratherthan attenuation usually determines if the communicationsmedium is reliable.

Communications falls into one of two categoriesbaseband

or broadband. Baseband is the transmission of data directly

over the medium itself, such as sending serial digi-

tal data over an RS-485 or I2C link. The original

10-Mbit/s Ethernet was baseband. Broadband

implies the use of modulation (and in some cases,

multiplexing) techniques. Cable TV and DSL are

probably the best examples, but cellular data is

also broadband.

Communications may also be synchronous orasynchronous. Synchronous data is clocked asin SONET fiber-optical communications, whileasynchronous methods use start and stop bits as inRS-232 and a few others.

Furthermore, communications links are simplex,

half duplex, or full duplex. Simplex links involve

one-way communications, or, simply, broadcasting.

Duplex is two-way communications. Half duplex

uses alternating TX and RX on the same channel.

Full duplex means simultaneous (or at least con-current) TX and RX, as in any telephone.

1

01 1 0 0 1 0 0 1

1 s

TimeTime

(a)

3 V

2 V

1 V

0 V11 00 10 01(b)

0

1

One bit interval

t

2. The bit time in this NRZ binary data signal determines data rate as 1/t.

3. Here, an 8-bit serial data word in NRZ format is to be transmitted (a). That same bitstream, when transmitted in a four-level PAM format, doubles data rate (b).

1. Encoding may be optional in this simplified model of a communications

system, while some systems require modulation. Noise is the main

restriction on range and reliability.

Datain

Encoding(optional)

TXMedium

(copper, fiber,radio)

Noise

RX DecodingDataout

May includemodulation

0909EE_F1

Digital Communications:The ABCs Of Ones And Zeroes

Dont be left in the analog dust.Avoid noiseand other transmission errors using thesedigital modulation schemes and error-cor-rection techniques.

louis e. FRenzel |CommuniCAtionS EDitor [email protected]


11/23



Topology is also fundamental. Point-to-point, point-to-multipoint, and multipoint-to-point are common. Networkingfeatures buses, rings, and mesh. They all dont necessarilywork for all media.

daTa raTe .VerSuS BandWidTHDigital communications sends bits seriallyone bit after anoth-

er. However, youll often find multiple serial paths being used,

such as four-pair UTP CAT 5e/6 or parallel fiber-optic cables.

Multiple-input multiple-output (MIMO) wireless also implements

two or more parallel bit streams. In any case, the basic data speed

or capacity C is the reciprocal of the bit time (t) (Fig. 2):

C = 1/t

C is the channel capacity or data rate in bits per second andt is the time for one bit interval. The symbol R for rate is also

used to indicate data speed. A signal with a bit time of 100 nshas a data rate of:

C = 1/100 109 = 10 Mbits/s

The big question is how much bandwidth (B) is needed topass a binary signal of data rate C. As it turns out, its the risetime (tR) of the bit pulse that determines the bandwidth:

B = 0. 35/tR

B is the 3-dB bandwidth in megahertz and tR is in microsec-

onds (s). This formula factors in the effect of Fourier theory. For

example, a rise time of 10 ns or 0.01 s needs a bandwidth of:

B = 0.35/0.01 = 35 MHz

A more precise measure is to use the Shannon-Hartley theo-rem. Hartley said that the least bandwidth needed for a givendata rate in a noise-free channel is just half the data rate or:

B = C/2

Or the maximum possible data rate for a given bandwidth is:

C = 2B

As an example, a 6-MHz bandwidth will allow a data rate up

to 12 Mbits/s. Hartley also said that this figure holds for two-level or binary signals. If multiple levels are transmitted, thenthe data rate can be expressed as:

C = (2B)log2MM indicates the number of multiple voltage levels or sym-

bols transmitted. Calculating the base 2 logarithm is a realpain, so use the conversion where:

log2N = (3.32)log10N

Here, log10N is just the common log of a number N. Therefore:

C = 2B(3.32)log10N

For binary or two-level transmission, the data rate for a

bandwidth of 6 MHz is as given above:

C = 2(6)(3.32)log102 = 12 Mbits/s

With four voltage levels, the theoretical maximum data ratein a 6-MHz channel is:

C = 2(6)(3.32)log104 = 24 Mbits/s

To explain this, lets consider multilevel transmissionschemes. Multiple voltage levels can be transmitted over abaseband path in which each level represents two or more bits.Assume we want to transmit the serial 8-bit byte (Fig. 3a). Alsoassume a clock of 1 Mbit/s for a bit period of 1 s. This willrequire a minimum bandwidth of:

B = C/2 = 1 Mbit/s/2 = 500 kHz

With four levels, two bits per level can be transmitted (Fig.3b). Each level is called a symbol. In this example, the fourlevels (0, 1, 2, and 3 V) transmit the same byte 11001001.This technique is called pulse amplitude modulation (PAM).The time for each level or symbol is 1 s, giving a symbolratealso called the baud rateof 1 Msymbol/s. Therefore,the baud rate is 1 Mbaud, but the actual bit rate is twice that,

or 2 Mbits/s. Note that it takes just half the time to transmit thesame amount of data.

0

90

180

270

01

(a)

0

90

180 180

270 270

10 11

00 01

(b)

0

90110

111

011

010000

001

101

100

(c)

4. Shown are phase-shift keying (PSK) constellation diagrams for binary PSK (a), quaternary PSK (b), and 8PSK (c).


12/23



What this means is that for a given

clock rate, eight bits of data can be trans-

mitted in 8 s using binary data. With

four-level PAM, twice the data, or 16

bits, can be transmitted in the same 8

s. For a given bandwidth, that trans-

lates to the higher data rate equivalent to

4 Mbits/s. Shannon later modified this

basic relationship to factor in the signal-

to-noise ratio (S/N or SNR):

C = (B)log2(1 + S/N)

or:

C = B(3.32)log10(1 + S/N)

The S/N is a power ratio and is not measured in dB. S/N alsois referred to as the carrier-to-noise ratio or C/N. C/N is usually

defined as the S/N of a modulated or broadband signal. S/N is

used at baseband or after demodulation. With an S/N of 20 dB or

100 to 1, the maximum data rate in a 6-MHz channel will be:

C = 6(3.32)log10(1 + 100) = 40 Mbits/s

With an S/N = 1 or 0 dB, the data rate drops to:

C = 6(3.32)log10(1 + 1) = 6 Mbits/s

This last example is why many engineers use the conserva-

tive rule of thumb that the data rate in a channel with noise isroughly equal to the bandwidth C = B.

If the speed through a channel with a good S/N seems to defyphysics, thats because the Shannon-Hartley formulas dontspecifically say that multiple levels or symbols can be used.Consider that:

C = B(3.32) log10(1 + S/N) = 2B(3.32) log10M

Here, M is the number of levels or symbols. Solving for M:

M = (1 + S/N)

Take a 40-Mbit/s data rate in a 6-MHzchannel, if the S/N is 100. This willrequire multiple levels or symbols:

M = (1 + 100) = 10

Theoretically, the 40-Mbit/s rate canbe achieved with 10 levels.

The levels or symbols could be repre-

sented by something other than different

voltage levels. They can be different phase

shifts or frequencies or some combination

of levels, phase shifts, and frequencies.Recall that quadrature amplitude modula-

tion (QAM) is a combination of different

voltage levels and phase shifts. QAM, the

modulation of choice to achieve high data

rates in narrow channels, is used in digital

TV as well as wireless standards like HSPA,

WiMAX, and Long-Term Evolution (LTE).

CHannel impairmenTSData experiences many impairments

during transmission, especially noise.The calculations of data rate versus band-width assume the presence of additivewhite Gaussian noise (AWGN).

Noise comes from many different sourc-

es. For instance, it emanates from thermal

agitation, which is most harmful in the front end of a receiver. The

sources are resistors and transistors, while other forms of noise

come from semiconductors. Intermodulation distortion createsnoise. Also, signals produced by mixing in nonlinear circuits cre-

ate interfering signals that we treat as noise.

Other sources of noise include signals picked up on a cable

by capacitive or inductive coupling. Impulse noise from auto

ignitions, inductive kicks from motor or relay turn on or off, and

power-line spikes are particularly harmful to digital signals. The

60-Hz hum induced by power lines is another example. Sig-

nals coupled from one pair of conductors to another within the

same cable create crosstalk noise. In a wireless link, noise can

come from the atmosphere (e.g., lightning) or even the stars.

Because noise is usually random, its frequency spectrum is

broad. Noise can be reduced by simply filtering to limit the band-

width. Bandwidth narrowing obviously will affect data rate.Its also important to point out that noise in a digital system

is treated differently from that in an analog system. The S/Nor C/N is used for analog systems, but Eb/N0 usually evalu-ates digital systems. Eb/N0 is the ratio of the energy per bit tothe spectral noise density. Its typically pronounced as E sub bdivided by N sub zero.

Energy Eb is signal power (P) multiplied by bit time texpressed in joules. Since data capacity or rate C (sometimesdesignated R) is the reciprocal of t, then Eb is P divided by R.N0 is noise power N divided by bandwidth B. Using these defi-nitions, you can see how Eb/N0 is related to S/N:

Eb/N0= S/N (B/R)

Remember, you can also express Eb/N0 and S/N in dB.

The energy per bit is a more appropri-ate measure of noise in a digital system.Thats because the signal transmitted isusually during a short period, and theenergy is averaged over that time. Typi-cally, analog signals are continuous. Eb/N0 is often determined at the receiverinput of a system using modulation. Its

a measure of the noise level and willaffect the received bit error rate (BER).

bAnDwiDth EFFiCiEnCy

moto tBwthffcc

FSK 1

bpSK 1

QpSK 2

8pSK 3

8QAm 3

16pSK 4

16QAm 4

0

90

180

270

0000

0001

00100011

01000101

01100111

1000

1001

1010

1011

11001101

11101111

5. In this constellation diagram for 16QAM, 16

unique amplitude-phase combinations transmit

data in 4-bit groups per symbol.


13/23



Different modulation methods have varying Eb/N0 values andrelated BERs.

Another common impairment is attenuation. Cable attenu-ation is a given thanks to resistive losses, filtering effects, andtransmission-line mismatches. In wireless systems, signalstrength typically follows an attenuation formula proportionalto the square of the distance between transmitter and receiver.

Finally, delay distortion is another source of impairment. Sig-nals of different frequencies are delayed by different amountsover the transmission channel, resulting in a distorted signal.

Channel impairments ultimately cause loss of signal and bittransmission errors. Noise is the most common culprit in biterrors. Dropped or changed bits introduce serious transmissionerrors that may make communications unreliable. As such, theBER is used to indicate the quality of a transmission channel.

BER, which is a direct function of S/N, is just the percentageof the number of error bits to the total transmitted bits over agiven time period. Its usually considered to be the probabilityof an error occurring in so many bits transmitted. One bit errorper 100,000 transmitted is a BER of 105. The definition of agood BER depends on the application and technology, butthe 105 to 1012 range is a common target.

errOr COdingError detection and correction techniques can help miti-

gate bit errors and improve BER. The simplest form of errordetection is to use a parity bit, a check code sum, or cyclical

redundancy check (CRC). These are added to the transmit-ted data. The receiver recreates these codes, compares them,and then identifies errors. If errors occur, an automatic repeatrequest (ARQ) message is sent back to the transmitter and thecorrupted data is retransmitted. Not all systems use ARQ, butARQ-less systems will typically employ some form of it.

Nonetheless, most modern communications systems gomuch further by using sophisticated forward error correction(FEC) techniques. Taking advantage of special mathematicalencoding, the data to be transmitted is translated into a setof extra bits, which are then added to the transmission. If biterrors occur, the receiver can detect the failed bits and actu-ally correct all or most of them. The result is a significantlyimproved BER.

Of course, the downsides are the added complexity of theencoding and the extra transmission time needed for the extrabits. This overhead is easily accommodated in more contempo-

rary IC-based communications systems.The many different types of FEC techniques available todayfall into two groups: block codes and convolutional codes. Block

codes operate on fixed groups of data bits to be transmitted, with

extra coding bits added along the way. The original data may or

may not be transmitted depending on the code type. Common

block codes include the Hamming, BCH, and Reed-Solomon

codes. Reed-Solomon is widely used, as is a newer form of

block code called the low-density parity check (LDPC).

Convolutional codes use sophisticated algorithms, like theViterbi, Golay, and turbo codes. FEC is widely used in wirelessand wired networking, cell phones, and storage media such asCDs and DVDs, hard-disk drives, and flash drives.

FEC will enhance the S/N. The BER improves with the useof FEC for a given value of S/N, an effect known as codinggain. Coding gain is defined as the difference between the S/Nvalues for the coded and uncoded data streams of a given BERtarget. For instance, if a system needs 20 dB of S/N to achievea BER of 106 without coding, but only 8 dB S/N when FEC isused, the coding gain is 20 8 = 12 dB.

mOdulaTiOnAlmost any modulation scheme may be used to transmit

digital data. But in todays more complex critical applications,the most widely used methods are some form of phase-shiftkeying (PSK) and QAM. Special modes like spread spectrumand orthogonal frequency division multiplexing (OFDM) areespecially well adopted in the wireless space.

DSP

LPF

LPF

MixersI

Q

ADC

ADC

Carrierlocal oscillator

sin

cos

Receivedsignal

DSP

MixersI

Q

DAC

DAC

Carrier

sin

cos

Transmitted

signal

6. The widely used I/Q method of modulation in a transmitter is derived

from the digital signal processor.

7. An I/Q receiver recovers data and demodulates in the digital signal

processor.

8. Direct sequence spread spectrum (DSSS) is produced using this basicarrangement.

Serialdatasignal

XORgate

Chippingsignal

Clock Codegenerator

Tomodulator


14/23



Amplitude-shift keying (ASK) and on-off keying (OOK) are

generated by turning the carrier off and on or by shifting it between

two carrier levels. Both are used for simple and less critical appli-

cations. Since theyre susceptible to noise, the range must be short

and the signal strength high to obtain a decent BER.

Frequency-shift keying (FSK), which is very good in noisy

applications, has several widely used variations. For instance, min-

imum-shift keying (MSK) and Gaussian-filtered FSK are the basis

for the GSM cell-phone system. These methods filter the binary

pulses to limit their bandwidth and thereby reduce the sideband

range. They also use coherent carriers that have no zero-crossing

glitches; the carrier is continuous. In addition, a multi-frequency

FSK system provides multiple symbols to boost data rate in a given

bandwidth. In most applications, PSK is the most widely used.

Plain-old binary phase-shift keying (BPSK) is a favorite scheme

in which the 0 and 1 bits shift the carrier phase 180. BPSK is best

illustrated in a constellation diagram (Fig. 4a). It shows an axis

where each phasor represents the amplitude of the carrier and thedirection represents the phase position of the carrier.

Quaternary, 4-ary, or quadrature PSK (QPSK) uses sine andcosine waves in four combinations to produce four differentsymbols shifted 90 apart (Fig. 4b). It doubles the data rate in agiven bandwidth but is very tolerant of noise.

Beyond QPSK is whats called M-ary PSK or M-PSK. Ituses many phases like 8PSK and 16PSK to produce eight or16 unique phase shifts of the carrier, allowing for very highdata rates in a narrow bandwidth (Fig. 4c). For instance, 8PSKallows transmission of three bits per phase symbol, theoreti-cally tripling the data rate in a given bandwidth.

The ultimate multilevel scheme, QAM, uses a mix of differ-

ent amplitudes and phase shifts to define as many as 64 to 1024or more different symbols. Thus, it reigns as the champion ofgetting high data rates in small bandwidths.

When using 16QAM, each 4-bit group is represented by aphasor of a specific amplitude and phase angle (Fig. 5). With16 possible symbols, four bits can be transmitted per baud orsymbol period. That effectively multiplies the data rate by fourfor a given bandwidth.

Today, most digital modulation and demodulation employs

digital signal processing (DSP). The data is first encoded and then

sent to the digital signal processor, whose software produces the

correct bit streams. The bit streams are encoded in an I/Q or in-

phase and quadrature format using a mixer arrangement (Fig. 6).

Subsequently, the I/Q data is translated into analog signalsby the digital-to-analog converters (DACs) and sent to the mix-ers, where its mixed with the carrier or some IF sine and cosinewaves. The resulting signals are summed to create the analogRF output. Further frequency translation may be needed. Thebottom line is that virtually any form of modulation may beproduced this way, as long as you have the right DSP code.(Forms of PSK and QAM are the most common.)

At the receiver, the antenna signal is amplified, downconvert-

ed, and sent to an I/Q demodulator (Fig. 7). The signal is mixed

with the sine and cosine waves, then filtered to create the I and

Q signals. These signals are digitized in analog-to-digital con-

verters (ADCs) and sent to a digital signal processor for the final

demodulation. Most radio architectures use this I/Q scheme andDSP. Its generally referred to as software-defined radio (SDR).

The DSP software manages the modulation, demodulation, and

other processing of the signal, including some filtering.

The spread-spectrum and OFDM broadband wide-band-width schemes are also forms of multiplexing or multipleaccess. Spread spectrum, which is employed in many cellphones, allows multiple users to share a common bandwidth.Its referred to as code division multiple access (CDMA).OFDM also uses a wide bandwidth to enable multiple users toaccess the same wide channel.

Figure 8 shows how the digitized serial voice, video, orother data is modified to produce spread spectrum. In thisscheme, direct sequence spread spectrum (DSSS), the serialdata is sent to an exclusive OR gate along with a much higherchipping signal. The chipping signal is coded so its recog-nized at the receiver. The narrow-band digital data (severalkilohertz) is then converted to a wider bandwidth signal thatoccupies a wide channel. In cell-phone cdma2000 systems,the channel bandwidth is 1.25 MHz and the chipping signalis 1.288 Mbits/s. Therefore, the data signal is spread over theentire band.

Spread spectrum can also be achieved with frequency-hop-ping spread spectrum (FHSS). In this configuration, the datais transmitted in hopping periods over different randomly

selected frequencies, spreading the information over a widespectrum. The receiver, knowing the hop pattern and rate, can10. Higher-level modulation methods like 16QAM require a better signal-to-noise ratio or higher Eb/N0.

Biterrorrate

0.1

102

103

104

105

106

107

Eb/N0 (dB)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

BPSKBPSK

DPSKDPSK

OOKOOK

FSKFSK

16QAM16QAM

9. The OFDM configuration used in IEEE 802.11a/g permits data rates of 6, 9,

12, 18, 36, 48, or 54 Mbits/s. Each subcarrier is modulated by BPSK, QPSK,

16QAM, or 64QAM, depending on the data rate.

Sub-carrierwidth/spacing

312.5 kHz

52 sub-carriers

20-MHzchannel

Frequency


15/23



reconstruct the data and demodulate it. The most commonexample of FHSS is Bluetooth wireless.

Other data signals are processed the same way and transmit-ted in the same channel. Because each data signal is uniquelyencoded by a special chipping-signal code, all of the signalsare scrambled and pseudorandom in nature. They overlay oneanother in the channel. A receiver hears only a low noise level.Special correlators and decoders in the receiver can pick outthe desired signal and demodulate it.

In OFDM, the high-speed serial data stream gets dividedinto multiple slower parallel data streams. Each stream modu-lates a very narrow sub-channel in the main channel. BPSK,QPSK, or different levels of QAM are used, depending on thedesired data rate and the applications reliability requirements.Multiple adjacent sub-channels are designed to be orthogonalto one another. Therefore, the data on one sub-channel doesntproduce inter-symbol interference with an adjacent channel.

The result is a high-speed data signal thats spread over a widerbandwidth as multiple, parallel slower streams.The number of sub-channels varies with each OFDM sys-

tem, from 52 in Wi-Fi radios to 1024 in cell-phone systemslike LTE and wireless broadband systems such as WiMAX.With so many channels, its possible to divide the sub-channelsinto groups. Each group would transmit one voice or other datasignal, allowing multiple uses to share the assigned bandwidth.Typical channel widths are 5, 10, and 20 MHz. To illustrate,the popular 802.11a/g Wi-Fi system uses an OFDM scheme totransmit data rates to 54 Mbits/s in a 20-MHz channel (Fig. 9).

All new cell-phone and wireless broadband systems useOFDM because of its high-speed capabilities and reliable com-

munications qualities. Broadband DSL is OFDM, as are mostpower-line technologies. Implementing OFDM can be difficultto implement, which is where DSP steps in.

Modulation methods vary in the amount of data they cantransmit in a given bandwidth and how much noise they canwithstand. One measure of this is the BER per given Eb/N0ratio (Fig. 10). Simpler modulation schemes like BPSK andQPSK produce a lower BER for a low Eb/N0, making themmore reliable in critical applications. However, different levelsof QAM produce higher data rates in the same bandwidth,although a higher Eb/N0 is needed for a given BER. Again, thetradeoff is data rate against BER in a given bandwidth.

SpeCTral eFFiCienCySpectral efficiency is a measure of how many bits can be trans-

mitted at a given rate over a fixed bandwidth. Its one way to com-

pare the effectiveness of modulation methods. Spectral efficiency

is stated in terms of bits per second per hertz of bandwidth, or

(bits/s)/Hz. Though the measure usually excludes any FEC cod-

ing, its sometimes useful to include FEC in a comparison.

Remember 56k dial-up modems? They achieved anamazing 56 kbits/s in a 4-kHz telephone channel, and theirspectral efficiency was 14 (bits/s)/Hz. Maximum through-put for an 802.11g Wi-Fi radio is 54 Mbits/s in a 20-MHzchannel for a spectral efficiency of 2.7 (bits/s)/Hz. A stan-dard, digital GSM cell phone does 104 kbits/s in a 200-kHzchannel, making the spectral efficiency 0.53 (bits/s)/Hz.Add EDGE modulation and that jumps to 1.93 (bits/s)/Hz. And taking it to new levels, the forthcoming LTE cellphones will have a spectral efficiency of 16.32 (bits/s)/Hzin a 20-MHz channel.

Spectral efficiency shows just how much data can becrammed into a narrow bandwidth with different modulation

methods. The table compares the relative efficiencies of dif-ferent modulation methods, where bandwidth efficiency is justdata rate divided by bandwidth or C/B.

Theres a tendencyto think of energy on the powerlines in terms of its fundamental 60- or 50-Hzfrequencythe way the voltage is supposed tobe created with the turbines and generators at thepower house. Sure, the current lags the voltageif theres a reactive load. Thats power factor,

right? But isnt it still a matter of real and reactive compo-

nents at 50 or 60 Hz? Yes and no. Unfortunately, that concep-tualization is a bit oversimplified.

In power distribution, power-factor correction (PFC) hastraditionally been understood in terms of adding (in general)capacitive reactance at points in the power distribution sys-tem to offset the effect of an inductive load. One could sayreactive load, but historically, power engineers have beenmost concerned with motors as loads when dealing withpower factor. Correction could take the form of a bank of

capacitors or a synchronous condenser (an unloaded syn-chronous motor).

Reconciling Power-Factor CorrectionStandards Leads To Solutions

Most of the world mandates control of current harmonics. North America specs 0.9power factor. Does it make a difference?

Don TuiTe| AnAlog/powEr EDitor [email protected]


16/23

More broadly, PFC can also be needed in any line-powered

apparatus that uses ac-dc power conversion. These applications

can range in scale from battery chargers for portable devices to

big-screen TVs. Cumulatively, their input rectifiers are the larg-

est contributor to mains-current harmonic distortion.

Where does that harmonic distortion come from? One com-mon misconception is that switching regulators cause harmon-ic power-factor components. Actually, theyre produced in thetypical full-bridge rectifier and its filter capacitor, aided andabetted by the impedance of the power line itself.

In the steady state, the supply draws current from the linewhen the input voltage exceeds the voltage on the filter capaci-tor. This creates a current waveform that includes all the oddharmonics of the power-line frequency (Fig. 1).

Once the voltage crosses that point, the current is only lim-ited by the source impedance of the utility line as well as by theresistance of the diode that is forward-biased and the reactance

of the capacitor that smoothes out the dc. As the power linesexhibit non-zero source impedance, the high current peakscause some clipping distortion on the peaks of the voltagesinusoid.

Harmonics get to be considered elements of power factorbecause of their relationship to the power-line frequency. AsFourier components, they cumulatively represent an out-ofphase current at the fundamental frequency. In fact, one broaddefinition of power factor is:

where THD is total harmonic distortion.

THe prOBlem WiTH pOWer FaCTOrWhatever the cause, whats actually so wrong with power

factors less than unity? Part of the problem is economic. Anoth-

er part has to do with safety. Whatever their phase relationships,

all those superposed harmonic currents create measurable I2R

losses as theyre drawn from the generator, through miles of

transmission and distribution lines, to the home or workplace.

Historically, the utility ate the expense of the losses. At leastfor domestic consumers, the utility delivered volt-amperes,the consumer paid for watts, and the volt-amperes reactive(VARs) were a net loss. In fact, old mechanical power meters

didnt even record those currents, and in any event, tariffs fordomestic consumers dont permit charging for anything butreal power.

That situation is likely to continue since fixing the tariffs is

unlikely to appeal to state legislators. In any event, resolving the

situation on an engineering level is more practical than socking it

to Joe Homeowner.

Thats the economic side of the story. In terms of safety,if Joes home is an apartment, he has another reason to care.Harmonics, notably the third, can and do result in three-phase

imbalance, with current flowing in the ground conductor in awye (Y) configuration. The wye ground conductor typicallyisnt sized to carry significant current.

PFC harmonics also cause losses and dielectric stresses incapacitors and cables, in addition to overcurrents in machineand transformer windings. For a more detailed analysis, seePFC Strategies in light of EN 61000-3-2, by Basu, et al(http://boseresearch.com/RIGA_paper_27_JULY_04.pdf).

regulaTing pFInterestingly, mains power has been subject to interference

from the beginning. The first regulatory effort to control dis-



VIN

IL

Q1

D1

C1

VOUTVOUT

Gatingsignal

(b)

Continuous conductionmode

(a)

Inductorcurrent

Peakinductorcurrent

Averageinductorcurrent

Critical conduction(transition) mode

PFCcontroller

2. Power-factor correction (PFC) in ac-dc supplies consists of using a control circuit to switch a MOSFET so it draws current through an inductor in a way

that fills in the gaps that would otherwise represent harmonics. When the PFC is operated in critical conduction or transition mode (a), the average

inductor current is relatively low, because the peak current is allowed to fall essentially to zero amps. When it is operated in continuous conductionmode (b), the average current is higher. Transition mode is easier to achieve, while continuous mode results in power factors closer to unity.

AC line

AC lineimpedance

Load withac-dc rectifierand cap as first

power-conversionstage

Voltageand

current

AC linevoltage

Time

Clipped voltage sine waveat the wall outlet

Line current drawn byrectifier capacitor filter circuit

Time

1. In ac-dc switching power supplies, the power-line frequencys current

harmonics are produced when the load draws current from the power line

during the intervals when the line voltage is higher than the voltage on

the filter capacitor. The net effect is of a load current that is out of phase

with the line voltage and contains frequency components that exhibit skin

effect on power lines, causing conduction losses, and excite eddy currentsin power-company transformers that result in further losses.


17/23


turbances to the electrical grid, the British Lighting ClausesAct of 1899, was intended to keep uncontrolled arc-lampsfrom making incandescent lamps flicker.

More recently (1978 and 1982), international standards IEC

555-2 Harmonic injection into the AC Mains and IEC 555-3

Disturbances in supply systems caused by household appliances

and similar electrical equipment - Part 3: Voltage fluctuations

were published. (Later they were updated to IEC1000 standards.)

Like those standards, the current standards come out of Europe,

but theyre nearly universal. There are related government regu-

lations for power-line harmonics in Japan, Australia, and China.

In the European Union, standard IEC/EN61000-3-2, Elec-tromagnetic compatibility (EMC) - Part 3-2 - Limits - Limitsfor harmonic current emissions (equipment input current 16A per phase), sets current limits up to the 39th harmonic forequipment with maximum power-supply specs from 75 to 600W. Its Class D requirements (the strictest) apply to personal

computers, computer monitors, and TV receivers. (Classes A,B, and C cover appliances, power tools, and lighting.)What does the standard actually say? Under IEC 61000-3-2,

the limits for Class D harmonic currents are laid down in termsof milliamps per watt consumed (Table 1).

glOBal diSHarmOnyAwkwardly, IEC61000-3-2, being a European-oriented

standard, is based on 230-V single-phase and 230/400-Vthree-phase power at the wall-plug. In consequence, the cur-rent limits have to be adjusted for 120/240-V mains voltagesin North America.

While IEC61000-3-2 sets mandatory standards for supplies

sold in the EU, there are voluntary standards for North Amer-ica. The U.S. Department of Energys Energy Star ComputerSpecification includes 80 Plus power-supply requirementsfor desktop computers (later including servers) and laptops.

80 Plus is a U.S./Canadian electric utility-funded rebate pro-gram that subsidizes the extra cost of computer power suppliesthat achieve 80% or higher efficiency at low mid-range andpeak outputs, relative to the power rating on the nameplate, andthat exhibit a power factor of at least 0.9.Within territories served by participatingutilities, the utilities pay $5 or $10 forevery desktop computer or server sold.

In 2008, the 80 Plus program wasexpanded to recognize higher-efficiencypower supplies, initially using the Olym-pic medal colors of bronze, silver, andgold, and then adding platinum (Table2). The new subcategories were meantto help expand program branding and tomake it possible to offer larger consumerrebates for participating manufacturersthat had moved ahead of the curve.

In Table 2, redundant refers to the

practice of server systems makers of oper-

ating from a 230-V ac source and using

multiple supplies to deliver power to theload. Some systems may have up to six

power supplies so if one fails, the others can absorb the failed

units share of load.

BelOW 20% lOadOne complaint about 80 Plus is that it does not set efficiency

targets for very low load levels. This may seem like a trivialobjection, but it isnt when there are large numbers of comput-ers in operations such as server farms, many of which may bein a standby or sleep mode at any given time. Ironically, theprocessors power-saving modes tend to conflict with efforts tosave power in the ac supply.

Of some further significance may be the conflict betweenspecifying requirements for the individual components ofharmonic distortion, as IEC 61000-3-2 does, and specifying asingle value, such as 0.9 for power factor, as the higher levelsof 80 Plus do.

Texas Instruments provides an interesting analysis of the

issues in a white paper, High Power Factor and High Efficien-cy You Can Have Both, by Isaac Cohen and Bing Lu (http://focus.ti.com/download/trng/docs/seminar/Topic_1_Cohen_

Lu.pdf). Early in the paper, the authors calculate the powerfactor represented by the Class D harmonic levels specifiedby IED61000-3-2, Class D. Making a few simplifications, theexpression for power factor reduces to:

Since 0.726 is significantly less than 0.9, a supply that justmeets the minimum requirement for the EU standard will failEnergy Star.

Just to make things interesting, the TI authors note thatbased on the basic definition of power factor as the ratio of theaverage power in watts absorbed by a load from a voltage orcurrent source to the product of RMS voltage appearing across

the load and the RMS current flowing init, it is theoretically possible to design asimple full-wave bridge and drive it witha square wave and have it meet the 0.9power-factor Energy Star requirementby emulating an inductive-input filterwith a large inductance value. (See thewhite paper for details.) Nonetheless,a Fourier analysis of the square waveshows that all harmonics above the 11thexceed the IEC61000-3-2 limits.

Ultimately, as the title of the papersuggests, the problem is a chimera. For-tuitously, all the commonly used active-PFC circuits draw input-current wave-forms that can easily comply [with] bothstandards, the authors say.

Like Texas Instruments, ON Semicon-ductor has addressed the issues of rec-


Ripp

lecurrentre

du

ctionnorma

lize

d

toonep

ha

seo

fPFC

1.0

0.9

0.8

0.7

0.6

0.50.4

0.3

0.2

0.1

0.0

Two phasesThree phasesFour phases

Duty cycle0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

3. The amount of ripple reduction in multi-phase

PFC schemes is a function of duty cycle. The

solid line represents a two-phase design. In a

three-phase design, the phase difference of each

phase is 360 divided by three, which is 120. Ina four-phase design, the phase difference is 90.


18/23

onciliation. In a communication available online, Commentson Draft 1 Version 2.0 Energy Star Requirements for ExternalPower Supplies (EPS) at www.energystar.gov/ia/partners/prod_development/revisions/downloads/ON_Semiconductor.

pdf, the company advised the Department of Energy that exter-nal power supplies that meet the IEC61000-3-2 typically havea power factor of 0.85 or greater when measured at 100% ofrated output power.

More specifically, at 100% of rated output power and 230-V

ac line, two-stage external power supplies with an active-PFCfront end exhibit a power factor greater than 0.9, the paperexplains. The opposite is however not true, i.e. it is entirelypossible that an external power supply can exhibit a powerfactor of 0.9 and yet will fail a given odd harmonic current andtherefore will not meet the IEC61000-3-2.

Another issue with stating a PFC requirement directly, rather

than in terms of individual harmonics, has to do with design effi-

ciency. For a single-stage PFC topology to meet the proposed

power-factor specification at 230-V ac line, ON Semiconductor

says, the necessary circuit modifications would result in a few-

percent efficiency loss and in a substantially increased cost.

For single-stage external power supplies the power factor istypically greater than 0.80. The proposed power-factor require-ment would eliminate the single-stage topology that is one ofthe most cost-effective ways of building highly efficient exter-nal power supplies such as notebook adapters with a nameplateoutput power below 150 W, ON Semiconductor says.

Note the emphasis on single-stage. It opens the door to aninteresting design question represented by TI and ON Semi. Tounderstand it, lets first look at actual PFC design approaches.

apprOaCHeS TO uniTy pOWer FaCTOrSince the discontinuous input-filter charging current creates

the low power factor in switch-mode power supplies, the cure

is to increase the rectifiers conduction angle. Solutions includepassive and active PFC and passive or active filtering.

Passive PFC involves an inductor on thepower-supply input. Passive PFC lookssimple, but isnt really practical for rea-sons that include the necessary inductance,conduction losses, and possibility of reso-nance with the output filter capacitor.

As noted above, the power-factorproblem in ac-input switch-mode powersupplies arises because current is drawnfrom the line only during parts of the ac-supply voltage waveform that rise abovethe dc voltage on the bulk storage (filter)capacitor(s). This non-symmetrical cur-rent draw introduces harmonics of the acline voltage on the line.

The basic PFC concept is fairly simple(Fig. 2). A control circuit switches a MOS-

FET to draw current through an inductorin a way that fills in the gaps that wouldotherwise represent harmonics.

The PFC controller can be designed tooperate in several modes: critical conduction mode (also calledtransition mode), and continuous conduction mode (CCM).The differences lie in how fast the MOSFET switches, which inturn determines whether the inductor current (and the energy inthe inductor) approaches zero or remains relatively high.

The terms critical and transition reflect the fact thateach time the current approaches 0 A, the inductor is at a pointwhere its energy approaches zero. Transition-mode operationcan achieve power factors of 0.9. However, it is limited to

lower power levels, typically 600 W and below. It is economi-cal, because it uses relatively few components. Applicationsinclude lighting ballasts and LED lighting, as well as con-sumer electronics.

The circuit topology for CCM is like critical conductionmode. But unlike the simpler mode, its ripple current has amuch lower peak-to-peak amplitude and does not go to 0 A.The inductor always has current flowing through it and does notdump all of its energy at each pulse-width modulation (PWM)cycle, hence the term continuous.

In this case, the average current produces a higher-qualitycomposite of the ac line current, making it possible to achievepower factors near unity. This is important at higher powerlevels as the higher currents magnify radiated and conductedelectromagnetic interference (EMI) levels that critical conduc-tion mode would have difficulty meeting.

pFC COnTrOller deSignSTI has an interesting solution for this, embodied in its

UCC28070 two-phase interleaved continuous-current modePFC controller (Fig. 4). The UCC28070 targets 300-W tomulti-kilowatt power supplies, such as what might be used intelecom rectifiers or server front ends.

The idea behind the design of the TI chip is that for higherpower levels, it is possible to parallel two PFC stages to deliver

higher power. This also has thermal-management advantages,since heat losses from the two stages are spread over a wider



+

M2

M1

D2

D1

T1

T2

L1VIN VOUT

Fromcurrent

transformer

UCC28070

12 to 21 V

To currentsense input

Tocurrentsenseinput

L2

4. Texas Instruments UCC28070 power-factor correction chip integrates two pulse-widthmodulators operating 180 out of phase. This interleaved PWM operation reduces input and

output ripple currents, and the conducted-EMI filtering is easier and less expensive.


19/23


area of the circuit board. The disadvantage of simple paralleloperation is higher input and output ripple currents.

TI says that a better alternative is to interleave the two stagesso their currents are 180 out of phase. That way, the ripplecurrents cancel. In fact, designs with more than two phases are

common (Fig. 3). In those cases, the phase angles are distrib-uted evenly. In multiphase PFC, due to the lower output ripplecurrents, the number or physical size of the passive compo-nents can be smaller than in single-phase PFC, providing cost,space, and EMI-filter complexity tradeoffs.

The application often drives PFC controller design. For

example, ON Semiconductors NCL30001 LED lighting con-troller, which is intended for 12-V and higher LED lighting

applications between 40 and 150 W, combines CCM PFC and a

flyback step-down converter (Fig. 5).

While a typical LED lighting power supply might consist of a

boost PFC stage that powers a 400-V bus followed by an isolated

dc-dc converter, the NCL30001 datasheet describes a simpler

approach that shrinks the front-end converter (ON Semi calls it

the PFC preregulator) and the dc-dc converter into a single pow-

er-processing stage with fewer components. It essentially needs

only one MOSFET, one magnetic element, one low-voltage

output rectifier, and one low-voltage output capacitor.

ON Semiconductors datasheet provides an instructivedescription of the portion of the circuit shown in Figure 5. The

output of a reference generator is a rectifiedversion of the input sine wave proportionalto the feedback (FB) and inversely propor-tional to the feedforward (VFF) values. An acerror amp forces the average current outputof the current-sense amplifier to match thereference-generator output. This output (VER-ROR) drives the PWM comparator through areference buffer, and the PWM comparatorsums VERROR and the instantaneous currentand compares the result to a 4.0-V threshold.

Suitably compensated, this provides the duty-cycle control.


AC in

VCC

DRV

VFF

FB

S

RQ

Referencegenerator

+ V-to-I

+ inverter

+

+

21.33k

21.33k

V-to-I

V-to-I

4 V

+

+

VSSKIP

tSSKIP

Start

Soft-skip ramp

Delay

+

+

VSSKIP(TLD)

Terminate

+

+

VSSKIP(sync)

Ramp comp

Clock

DC max

FB

RFB

VDD

VCC OK

Brownout

Overload

Latch

AC erroramplifier

PWMcomparator

PWM skipcomparator

AC in skipcomparator

FB skipcomparator

Transient load detectcomparator

Outputdriver

Transconductanceamplifier

+VFF

5. ON Semiconductors NCL30001 employs a variable reference generator, a low-frequency voltage-regulation error amplifier, ramp compensation, and a

current shaping network. Inputs to the reference generator include a scaled ac input signal (AC_IN) and feedforward input (VFF).

tAblE 1: En61000-3-2 ClASS DhArmoniC CurrEnt limitS(powEr = 75 to 600 w)

Hoc o ()rtv

t (a/W)absot t (a)

3 3.4 2.30

5 1.9 1.14

7 1.0 0.77

9 0.5 0.40

11 0.35 0.33

13 39 3.85/n 2.25/n

tAblE 2: 80 pluS EFFiCiEnCy lEVElS

Tst t 115-V t o-t 230-V t t

pece faed ad

20% 50% 100% 20% 50% 100%

80 ps basc 80% 80% 80% Undefined

bze 82% 85% 82% 81% 85% 81%

Sve 85% 88% 85% 85% 89% 85%

gd 87% 90% 87% 88% 92% 88%

pa 90% 92% 89% 90% 94% 91%


20/23

Why is it important to dissipate heat? For

most semiconductor applications, quickly

moving the heat away from the die and out

toward the larger system prevents highly

concentrated areas of heat on the silicon.

Typical operating temperatures for sili-con die range from 105C to 150C, depending on the applica-tion. At higher temperatures, metal diffusion is more prevalentand eventually the device can fail from shorting.

The dies reliability depends greatly upon the amount of timethats spent at the high temperatures. For very short durations,a silicon die can tolerate temperatures well above the publishedacceptable values. However, the devices reliability is compro-mised over time.

Due to this delicate balance between power needs and ther-mal limits, thermal modeling has become an essential tool forthe automotive industry. In the automotive safety industry, thecurrent drive is for smaller assemblies with lower part counts,

which forces semiconductor providers to include more func-tions with higher power consumption.

The higher temperatures generated ultimately will affect reli-ability and, in turn, automotive safety. But by optimizing thedie layout and power pulse timing early in the design cycle,designers can provide an optimized design with fewer silicontest builds, leading to a quicker development cycle time.

SemiCOnduCTOr THermal paCkagingThe automotive electronics industry uses various semicon-

ductor package types, from small, single-function transistorsto complex power packages with more than 100 leads andspecially designed heatsinking capabilities.

Semiconductor packaging serves to protect the die, provideelectrical connection between the device and external passivecomponents in the system, and manage thermal dissipation.For this discussion, well focus on the semiconductor pack-ages ability to conduct heat away from the die.

In leaded packages, the die is mounted to a metal plate calledthe die pad. This pad supports the die during fabrication, and itprovides a good thermal conductor surface. A common semi-conductor package type in the auto industry is the exposed pad,or PowerPAD-style, package (Fig. 1).

The bottom side of the die pad is exposed and soldered direct-ly to the printed-circuit board (PCB), providing a direct ther-

mal connection from the die to the PCB. The primary heat pathruns down through the exposed pad, which is then soldered to

the circuit board. The heat is then dissipated through the PCBinto the surroundings.

Exposed-pad-style packages conduct approximately 80%of the heat though the bottom of the package and into thePCB. The other 20% of the heat dissipates from the deviceleads and sides of the package. Less than 1% of the heat dis-sipates from the top of the package.

A similar leaded package is the non-exposed pad pack-age (Fig. 1, again). Here, plastic fully surrounds the die pad,providing no dire

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