TOOLKITOversampling UARTReduces RF Noise

requires no data coding. But the wirelessnature of the transmissions demandsthe use of a receiving algorithm. Thisalgorithm separates valid data fromundesirable noise. As a result, the dataneeds to be sent in packets or frames thathave a well-defined format.

Each frame should begin with a pre-amble of 1 to 2 B (for example,“10101010…”). The second field of theframe should contain the start byte,which is an identification that indicatesthe beginning of a frame. The rest ofthe frame will follow the start byte. Itshould consist of 1 B of an address (ID).It will be followed by the frame data (1to 100 B) and finally 2 B for a check-sum. The general structure of the frameis as follows:

INrecent years, wireless communica-tions have grown to encompass

applications like remote control, remotesensing, and wireless local-area networks(WLANs). The data rates of such imple-mentations vary from a few hundred toseveral million bits per second. In addi-tion, their range can be anywhere from afew to several hundred meters.Yet almostall of these wireless applications are thesame in that they provide serial, asyn-chronous digital data formats.

On the analog side, the physical chan-nels are shrouded in background noise.This noise comes from other transmitters

and instruments in the surrounding envi-ronment. Moreover, some receivers willdetect “fake data” when the transmitter isout of range. An example is a receiver thatimplements FSK modulation schemes.The “fake data” is actually signals withrandom frequency. These error challengesnecessitate a different way to implement aphysical-layer Universal AsynchronousReceiver Transmitter (UART) for thewireless communication line.

This article describes the use of anoversampling technique to transfer datafrom one microcontroller to another viaa transceiver module. The module itself

DESIGNER’S TOOLKIT

Reap The Benefits Of Programmable Logic By Implementing Wireless CommunicationsBased On An Oversampling Algorithm.

UARTVCC of CY37064

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BY ELI FLAXER

WI R E LE SS SYSTE M S D E S I G N22 O CTO BER 2004

1. This hardware-based oversampling UART receives bit-stream data from a transceiver module by a serialinput (D). It then transfers the complete byte to the microcontroller via portx.

Preamble Start Byte Address Data CRC

DESIGNER’S TOOLKIT

The transmission procedure issimple: The interrupt handlerin the microcontroller shouldsend the frame, bit by bit, at aconstant rate. This constantdata stream is known as thecommunication rate.

The receiver is on the otherend of the transmission system.The receiving routine is morecomplex than its counterparton the transmitting side. Forexample, the receiver interrupthandler may be triggered by anedge-level rise or fall. Such trig-gering might cause the inter-rupt handler to sample theinput stream in the middle ofeach bit. The result would be areduced data rate of only onesample per bit. This rate wouldproduce an output that is muchmore sensitive to noise than theoversampling approach.

When using oversampling,the receiving routine shouldsample the received bit streamat several times the bit rate.After being acquired, the sam-

We have a lock on timing…the proof is in the silicon

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D='0'

Sx <= 0Cx <= Tnx–3Bx <= 0Ax <= 0INTR <= '0'

Sx < 0.8*TnxBx <= Bx+1

IDLE S1

S2FALL

Cx <= Tns–3Sx <= 0 Bx = PreBits

Cx <= Tnx–4Sx <= 0Bx <= 0Ax <= 0Busy <= '1'

Cx > 0

Cx = 0

Cx <= Tnx–3Sx <= 0

D='1'

Cx = 0Cx > 0

Cx <= Cx–1Sx <= Sx+D

S0 GO

Cx <= Cx–1Sx <= Sx+D'

S3RISE

Bx <= Bx+1

Sx < 0.8*Tnx

FIN

Busy <= '0'

Bx = PreBits

W0

Cx <= Tnx–4Sx <= 0

S4

Cx <= Cx–1Sx <= Sx+D

DAMI

BYTE Load

Bx <= 0Ax <= Ax+1INTR <= '1'Data <= PR

Bx <= Bx+1PR <= PR(6–0) and f(S)

Bx < 8–1Ax < StrLen–1

2. This state-machine diagramshows the internal architectureof the CPLD that can be used toprovide the oversampling oftransmitted input data.

DESIGNER’S TOOLKIT[ UART IMPLEMENTATION ]

24 WI R E LE SS SYSTE M S D E S I G NO CTO BER 2004

1 -- Oversample A Wireless-UART Implementation WithVHDL2 -- Written By Eli Flaxer3 library IEEE;4 useIEEE.STD_LOGIC_1164.all;5 use IEEE.NUMERIC_STD.all;67 entity WirelessUART is8 port (Clk: in STD_LOGIC;9 D: in STD_LOGIC;10 Rst: in STD_LOGIC;11 INTR: out STD_LOGIC;12 INTA: in STD_LOGIC;13 Busy: out STD_LOGIC;14 Data: outSTD_LOGIC_VECTOR (7 downto0));15 end;1617 architectureWirelessUART_Arch ofWirelessUART is1819 constant Freq: INTEGER :=20000000; -- Clock Freq ofCPLD20 constant BPS: INTEGER :=200000; -- TransceiverCommunication Rate2122 constant Tnx: INTEGER :=Freq / BPS; -- OverSample perData Bit23 constant StrLen: INTEGER :=12; -- Byte per Frame withoutpreamble24 constant PreBits: INTEGER:= 8; -- Preamble Bits minimum82526 -- SYMBOLIC ENCODEDstate machine: UartState27 type UartState_Type is (IDLE,S0, S1, S2, S3, FALL, RISE,28 GO, S4, LOAD, DAMI, W0,BYTE, FIN);2930 subtype CunterType1 isINTEGER range 0 to StrLen+1;31 subtype CunterType2 isINTEGER range 0 to PreBits+1;32 subtype CunterType3 isINTEGER range -1 to Tnx+1;3334 -- Uart signal declarations35 signal Ax: CunterType1; --Byte Counter in the Frame36 signal Bx: CunterType2; --Bit Counter in the Byte37 signal Cx: CunterType3; --

OverSampling Index in the Bit38 signal Sx: CunterType3; --OverSampling Data in the Bit39 signal PR:STD_LOGIC_VECTOR (7 downto0); -- Package Byte4041 signal UartState:UartState_Type;42 signal UartStateNext:UartState_Type;4344 --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++45 function F1 (n: CunterType3 )return STD_LOGIC is46 begin47 if(n > Tnx/2) then48 return('1');49 else50 return('0');51 end if;52 end function F1;53 --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++54 begin55 --------------------------------------------------------------------------56 UartSignal_Update: process(Clk, Rst, UartState)57 constant TnxC: integer :=Tnx-1;58 begin59 if Rst = '1' then60 Sx <= 0;61 Cx <= Tnx-2;62 Bx <= 0;63 Ax <= 0;64 INTR <= '0';65 Busy <= '0';66 Data <= (others => '0');67 elsif (Clk'event and Clk = '1')then68 case UartState is6970 when IDLE =>71 Sx <= 0;72 Cx <= TnxC-2;73 Bx <= 0;74 Ax <= 0;75 INTR <= '0';7677 when S1 =>78 Cx <= Cx-1;79 if (D = '1') then

80 Sx <= Sx+1;81 end if;8283 when S0 =>84 Cx <= Cx-1;85 if (D = '0') then86 Sx <= Sx+1;87 end if;8889 when FALL =>90 Bx <= Bx+1;9192 when RISE =>93 Bx <= Bx+1;9495 when S2 =>96 Cx <= TnxC-2;97 Sx <= 0;9899 when S3 =>100 Cx <= TnxC-2;101 Sx <= 0;102103 when GO =>104 Cx <= TnxC-3;105 Sx <= 0;106 Bx <= 0;107 Ax <= 0;108 Busy <= '1';109110 when S4 =>111 Cx <= Cx-1;112 if (D = '1') then113 Sx <= Sx+1;114 end if;115116 when LOAD =>117 Bx <= Bx+1;118 PR <= PR(6 DOWNTO 0) &F1(Sx);119120 when BYTE =>121 Ax <= Ax+1;122 Bx <= 0;123 INTR <= '1';124 Data <= PR;125126 when W0 =>127 Cx <= TnxC-3;128 Sx <= 0;129 -- INTR <= '0';130131 when FIN =>132 Busy <= '0';133134 when others =>135 null;136 end case;137138 if INTA = '1' then139 INTR <= '0';140 end if;

141142 end if;143 end process;144 ----------------------------------------------------------------------145 Uart_State_Update:process (Clk, Rst)146 begin147 if Rst = '1' then148 UartState <= IDLE;149 elsif (Clk'event and Clk ='1') then150 UartState <=UartStateNext;151 end if;152 end process;153 --------------------------------------------------------------------------154 Uart_State_Next: process(UartState, D, Ax, Bx, Cx, Sx)155 begin156 case UartState is157158 when IDLE =>159 if D = '1' then160 UartStateNext <= S1;161 else162 UartStateNext <= IDLE;163 end if;164165 when S1 =>166 if Cx = 0 then167 UartStateNext <= FALL;168 else169 UartStateNext <= S1;170 end if;171172 when S0 =>173 if Cx = 0 then174 UartStateNext <= RISE;175 else176 UartStateNext <= S0;177 end if;178179 when FALL =>180 if (Sx < Integer((0.8 * Tnx)))then181 UartStateNext <= IDLE;182 else183 UartStateNext <= S2;184 end if;185186 when RISE =>187 if (Sx < Integer((0.8 * Tnx)))then188 UartStateNext <= IDLE;189 else190 UartStateNext <= S3;191 end if;192

DESIGNER’S TOOLKIT

ples must be weighted according to aweighting table. All of these computa-tions result in a very reliable transmis-sion link. Oversampling at a rate of 10times the bit rate with sample weighting,for example, will produce a result that isnoticeably resistant to noise.

Designers must note, however, thattiming is critical because the samplingperiod must be consistent. If one usesthe microcontroller interrupt to imple-ment an oversampling, all of the systemresources will be at the mercy of theinterrupt handler. A better methodwould be to have a dedicated chip—using programmable logic—that per-forms the task of oversampling. Thismethod won’t tie up valuable systemresources. At the same time, it willenable much higher oversampling rates(e.g., sample rates of tens of megasam-ples per second).

Consider the use of a hardware-basedoversampling UART (FIG. 1).Component U1-CY37064P44 is a pro-grammable-logic device (CPLD) fromCypress Semiconductor (www.cypress.com). This component boasts 64 macrocells. It has 44 pins that are triggered by

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193 when S2 =>194 if (Bx = PreBits) then195 UartStateNext <= GO;196 else197 UartStateNext <= S0;198 end if;199200 when S3 =>201 if (Bx = PreBits) then202 UartStateNext <= GO;203 else204 UartStateNext <= S1;205 end if;206207 when GO =>208 UartStateNext <= S4;209210 when S4 =>211 if Cx = 0 then212 UartStateNext <= LOAD;213 else214 UartStateNext <= S4;215 end if;216217 when LOAD =>218 if (Bx < 8-1) then219 UartStateNext <= DAMI;220 else

221 UartStateNext <= BYTE;222 end if;223224 when DAMI =>225 UartStateNext <= W0;226227 when BYTE =>228 if (Ax < StrLen - 1) then229 UartStateNext <= W0;230 else231 UartStateNext <= FIN;232 end if;233234 when W0 =>235 UartStateNext <= S4;236237 when FIN =>238 UartStateNext <= IDLE;239240 when others =>241 UartStateNext <= IDLE;242 --null;243 end case;244 end process;245 --------------------------------------------------------------------------246 end WirelessUART_Arch;247

DESIGNER’S TOOLKIT[ UART IMPLEMENTATION ]

a 20-MHz clock. Of course, any otherCPLD with similar capabilities alsocould be used. One example might bethe ispMACH4A from LatticeSemiconductor (www.latticesemi.com).

The designer can program the CPLDwith any industrial, parallel CPLD pro-grammer. But a preferred method is touse In-System Reprogramming (ISR). J1is a JTAG connector, which is designedfor this purpose. The designer connectsthe UltraISR or C3ISR programmingcable between J1 and PC. After loadingthe appropriate JEDfile, he or she can thenbegin programmingthe device.

In this UART cir-cuit, one serial input(D) receives the bitstream from thetransceiver module. Adata bus (DATA)transfers a completebyte to the microcon-troller. That micro-controller containsthe traditional controlports for interruptrequest (INTR): trigger the microcon-troller, interrupt acknowledge (INTA),and a busy line (BUSY).

The internal architecture of the CPLDcan be described using state-machinediagrams (FIG. 2). The state machineincludes several constants: PreBits(number of bits in the preamble); StrLen(number of bytes in the frame excludingthe preamble); and Tnx (number ofsamplings per bit). In addition, there arefour counters: Ax, Bx, Cx, and Sx. Theycount bytes, bits, oversampling index,and oversampling data, respectively. TheCPLD contains one register (PR) to

store the received bits. At IDLE state, themachine is waiting for a rising edge inthe input stream D, which is the begin-ning of the preamble.

The next six states act as a preambledetector. At states S1 and S0, themachine oversamples bits ‘1’ and ‘0’ ofthe preamble. At states FALL and RISE,the machine checks if the average sam-ple is correct. The machine checks forthe end of the preamble at states S2 andS3. The busy line is set at GO, whichmeans that real data is received.

At state S4, themachine oversam-ples and averages thedata bits. At LOAD,eight average databits are packed into 1B. An interruptrequest (INTR) issent to the microcon-troller at state W0 tocollect the byte. Atstate BYTE, themachine checks forthe end of the frame.Finally, at FIN, itclears the busy line to

indicate that the entire frame wasreceived. The DAMI state is for balanc-ing the path in the machine. If INTAoccurs at any state, the interruptacknowledge (INTR) will clear.

Several methods are commonly usedto design, synthesize, and simulate thecontent of the complex programmable-logic device. Typically, VHDL code iswritten according to the state-machineflow to synthesize and simulate thedesign. In VHDL, the designer cansearch for the best tradeoffs between theclock frequency, data transfer rate, andnumber of bytes per frame. For example,

the VHDL source file created for thisoversampling project was based on a 20-MHz clock, 200-kbps data transfer rate,12 B per frame, and a preamble of 8 b[SEE SIDEBAR). Naturally, the designercan change those values as necessary toexamine other tradeoff conditions.

A testbench is needed to verify theVHDL simulation. Given the precedingexample, the simulation would startwith high-frequency noise (500 kHz)followed by a correct preamble and 12 Bof data (a complete frame). The result-ing simulation would help to test thedesign (FIG. 3).

Here, the testbench indicated that theUART rejects high-frequency noise (or apreamble with a different frequency).The correct preamble is detected and theBUSY line is set. The 12 bytes that followthe preamble (complete frame) are 33,37, 00, 01, 02, 03, 04, 05, 06, 07, 08, and09. Although the second byte (37)includes high-frequency noise at thefourth bit, the UART rejects this noise. Itsends the corrected data to the bus. Onecan see that the UART packs eight serialbits to one parallel byte and triggers themicrocontroller by the INTR command.When a complete frame is received, theBUSY line turns to zero. The UART isthen ready to receive the next frame.

This article presents one way to imple-ment a physical layer (UART) for wire-less communications. By using an over-sampling technique, designers can followthis very approach. It should lead themto develop a subsystem that is resistant tonoise and other interference. ■

Dr. Eli Flaxer, Senior Lecturer,Electrical Engineering and Computer Science,Tel-Aviv Academic College of Engineering,61533 Tel-Aviv, Israel; e-mail: flaxer@mail.tace.ac.il, www.tace.ac.il.

26 WI R E LE SS SYSTE M S D E S I G NO CTO BER 2004

Name

Xrst

Xclk

XD

XData

XINTR

XINTA

XBusy

0 50 100 150 200 250 300 350 400 450 500 550 600

Noise

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00 33 37 00 01 02 03 04 05 06 07 08 09

3. In the results from a VHDL simulation testbench, high-frequency noise is rejected by the UART.

...THE SAMPLING PERIODMUST BE CONSISTENT.

IF ONE USES THE MICROCONTROLLER

INTERRUPT TO IMPLEMENT AN OVERSAMPLING,

ALL OF THE SYSTEMRESOURCES WILL BE

AT THE MERCY OF THEINTERRUPT HANDLER.