TMS320DM355 Evaluation Module

TMS320DM355Evaluation Module

2008 DSP Development Systems

ReferenceTechnical

TMS320DM355 Evaluation Module Technical Reference

509905-0001 Rev. E April 2008

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2008 Spectrum Digital, Inc.

Contents

1 Introduction to the DM355 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the DM355 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview of the DM355 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the DM355 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Flash, NAND Flash, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.3 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.4 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.5 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 On Chip Video Output DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.1 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.6 DM355 CPU Video Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.7 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the DM355 Evaluation Module and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 J1, NTSC/PAL Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.2 J2, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.3 J3, MSP430 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.4 J4, Composite Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.5 J5, USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.6 J6, 14 Pin External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.7 J8, ARM JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.8 J9, USB Capacitance Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.9 J10, USB ID Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.10 J11, S-Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.11 J12, ATA/CE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.12 J16, +5 Volt Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.13 J27, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.14 J28, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.15 J30, Imager Interface Connector 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.16 J31, Imager Interface Connector 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.17 P1, Microphone In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.18 P2, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.19 P3, Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.20 P4, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.2.21 P5, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.2.22 P6, Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.2.23 DC3, I/O Daughter Card Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.2.24 DC5, TH8200 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.2.25 DC6, Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.2.26 DC7, Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.2.27 U10, Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4.1 SW1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4.2 SW5, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.4.3 SW6, User Readable 4 Position DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.4.4 SW7, ARM Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.4.5 SW10 - SW14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.5 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the DM355 Evaluation ModuleB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the DM355 Evaluation Module

About This Manual

This document describes the board level operations of the DM355 Evaluation Module(EVM). The EVM is based on the Texas Instruments TMS320DM355 Processor.

The DM355 Evaluation Module is a table top card that allows engineers and softwaredevelopers to evaluate certain characteristics of the DM355 processor to determine ifthe processor meets the designers application requirements. Evaluators can createsoftware to execute on board or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The DM355 Evaluation Module will sometimes be referred to as the DM355 EVM orEVM.

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding the TMS320DM355 can be found at the following TexasInstruments website:

http://www.ti.com

Table 1: Manual History

Revision History

A Production Release

B Updated Figures

C Edited text

D Updated schematics

E Updated schematics, Silkscreens, Figures

Table 2: Board History

PWBRevision

History

A Production Release

B Updated Silk-screen

C2 0.55 mm. Production Release

D2 0.65 mm. Production Release

1-1

Chapter 1

Introduction to the DM355 EVM

Chapter One provides a description of the DM355 EVM along with the keyfeatures and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview of the DM355 EVM 1-41.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-6

Spectrum Digital, Inc

1-2 DM355 EVM Technical Reference

1.1 Key Features

The DM355 EVM is a standalone development platform that enables users toevaluate and develop applications for the TMS320DM355 processor. Schematics,logic equations and application notes are available to ease hardware development andreduce time to market.

The EVM comes with a full complement of on board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments DM355 processor with an ARM processor operating up to 216 Mhz.

• 1 video input port, supports composite or S video

• 1 composite video DAC output

• 128 Mbytes of DDR2 DRAM

• UART, 2 SD/MMC card interfaces or 1 SD/MMC and 1 CE-ATA Disk Drive Interface

• 2 Gigabytes NAND Flash

• AIC33 stereo codec

• USB2 Interface

Figure 1-1, Block Diagram DM355 EVM

16

SW6

SW7

Reset

Switches

LINE OUT

LINE IN

MIC OUT

BatteryENETRJ45

IRMSP430

JTAG J1 J7

SPIROM

HP OUT

DC3

1 2 3 4

1 2

NAND

DM9000AMAC/PHY

DC6

3.3V I/O Supply

1.8V Supply

1.2V Core Supply

PWR

AIC33Codec

McBSPsSD/MMC

SD/MMCConnectors

SD0 on Bottom

USB 2.0

USB

LEDs

McBSPs

EMIF

JTAG

20 Pin ARM JTAG

14 Pin TI JTAG

UART0

RS-232 Com

p In

Video Out

Video In

VideoDecoderTVP5146

Com

p O

ut

J30

Imag

er

J31

Imag

er

I2C Bus

Mux

MSP430

DDR2

S-V

ideo

In

DM355

DC5

DC7


1-3

• 10/100 MBS Memory Mapped Ethernet Controller

• SPI EEPROM

• IR Remote Interface, real time clock, via MSP430

• Configurable boot load options

• 8 user LEDs/4 position user DIP switch/5 user push button switches

• Single voltage power supply (+5V)

• Expansion connectors for daughter card use

• 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces

Figure 1-2, DM355 EVM



1.2 Functional Overview of the DM355 EVM

The DM355 on the EVM interfaces to on-board peripherals through the 8/16-bit wideEMIF peripheral interface pins. The DDR2 memory is connected to its own dedicated16 bit wide bus. The EMIF bus is also connected to the NAND Flash and ethernetcontroller.

On board video decoder and on chip encoder interface video streams to the DM355processor. One decoder and 1 on chip DAC channel are standard on the EVM. Onscreen display functions are implemented in software on the DM355 processor.

An on-board AIC33 codec allows the DSP to transmit and receive analog audio

signals. The I2C bus is used for the codec control interface, while the McBSP controlsthe audio stream. Signal interfacing is done through 3.5mm audio jacks that correspondto microphone input, headphone output, line input, and line output.

The EVM includes 8 user LEDs, a 4 position user DIP switch, an IR interface, a Realtime clock along with 5 user push button switches to provide the user with applicationinteraction. These interfaces are implemented via software on a MSP430 and are

accessed by reading and writing to the I2C registers.

An included +5V external power supply is used to power the board. On-board switchingvoltage regulators provide the +1.3V CPU core voltage, +3.3V for peripherals and+1.8V for DDR2 memory. The board is held in reset by the on board MSP430microcontroller until these supplies are within operating specifications.

Code Composer Studio communicates with the EVM through an external emulator viathe 14 pin external JTAG connector.

1.3 Basic Operation

The EVM is designed to work with TI’s Code Composer Studio development, orstandard GDB tool environments. Code Composer communicates with the boardthrough an external JTAG emulator. To start, follow the instructions in the Quick StartGuide to install Code Composer. This process will install all of the necessarydevelopment tools, documentation and drivers.


1-5

1.4 Memory Map

The DM355 processor has a byte addressable address space. There are somelimitations to byte addressing which are determined by peripheral interconnection to theDM355 device. Program code and data can be placed anywhere in the unified addressspace. Addresses are multiple sizes depending on hardware implementation. Refer tothe appropriate device data sheets for more details.

The memory map shows the address space of a generic DM355 processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.

The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces tothe DDR2 memory. The other EMIF has 2 separate addressable regions called chipenable spaces (CE0 & CE1). The NAND Flash and ethernet controller are mapped intothese chip enable spaces.

DM355 EVM

Address0x00000000

0x00008000

0x00010000

0x04000000

0x06000000

0x80000000

CE1

DDR

Figure 1-3, Memory Map, DM355 EVM

ARM Instruction RAM

ARM Instruction ROM

CE00x02000000

Memory Map Address Space

0x8FFFFFFF

Reserved

ARM RAM (Data)

Reserved0x00020000



Shown below is a break out of the memory spaces.

1.5 Configuration Switch Settings

The EVM has a configuration switch that allow users to control the operationalstate of the processor when it is released from reset and determine the source forprocessor booting. Switch SW7 configures the boot mode that will be used when theDSP starts executing. By default the switches are configured to NAND Flash boot.The EMIF configuration switch must be set accordingly.

* Default Setting

1.6 Power Supply

The EVM operates from a single +5V external power supply connected to the mainpower input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is convertedinto +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The+1.3V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/Obuffers and other chips on the board. The +1.8 volt supply is used for DM355 DDR2memory.

Table 1: SW7, Boot Mode Select

Pos 2 Pos 1Boot Pin

BTSEL1/BTSEL0Function

ON ON 0 0 NAND boot CE0 *

ON OFF 0 1 Not Supported

OFF ON 1 0 Boot from SD/MMC

OFF OFF 1 1 Boot from UART

Address

0x02004000

Figure 1-4, DM355 EVM Chip Enable Memory Space

0x04014000

Memory Space0x02000000

NAND Chip Select 0

NAND Chip Select 1

DM9000A ENET Controller

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe DM355 EVM.

Topic Page

2.1 EMIF Interfaces 2-22.1.1 Flash, NAND Flash, Ethernet Interface 2-22.1.2 DDR2 Memory Interface 2-22.1.3 Memory Card Interface 2-22.1.4 UART Interface 2-32.1.5 USB Interface 2-32.2 Input Video Port Interfaces 2-32.2.1 On Chip Video Output DAC 2-32.2.2 AIC33 Interface 2-42.3 Ethernet Interface 2-52.4 I2C Interface 2-52.4.1 MSP430 2-62.5 Daughter Card Interface 2-62.6 DM355 CPU/Video Clocks 2-62.7 Battery 2-7



2.1 EMIF Interfaces

A separate 16 bit EMIF with two chip enables divide up the address space and allowfor asynchronous accesses on the EVM.

2.1.1 Flash, NAND Flash, Ethernet Interface

The DM355 has 2 gigabytes of NAND Flash memory, and an ethernet interfacememory mapped into the CE0 and CE1 spaces. The NAND Flash memory is usedprimarily for boot loading and file system on the DM355 EVM. The CE0 and CE1 spaceare configured as 8 and 16 bits wide respectively on the DM355 EVM.

2.1.2 DDR2 Memory Interface

The DM355 device incorporates a dedicated 16 bit wide DDR2 memory bus. The EVMuses one gigabit 16 bit wide memories on this bus, for a total of 128 megabytes ofmemory for program, data, and video storage. The internal DDR controller uses a PLLto control the DDR memory timing. Memory refresh for DDR2 is handled automaticallyby the DM355 internal DDR controller.

2.1.3 Memory Card Interface

The EVM supports two (2) SD/MMC media card interfaces. The second SD connectoris connected in parallel to the CE-ATA disk drive connector.


2-3

2.1.4 UART Interface

The internal UART0 on the DM355 device is driven to connector P4. The UART’sinterface is routed to the RS-232 line drivers prior to being brought out to a DB-9connector, P4.

2.1.5 USB Interface

The DM355 incorporates an on chip USB II controller. This interface is brought out to amini A/B connector with its own power regulator. Two jumpers are provided to make aflexible host peripheral, and USB on the go interface.

2.2 Input Video Port Interfaces/Imager Input Ports

The DM355 EVM supports video capture via the devices internal video ports. A TexasInstruments TVP5146 is used to decode composite video or S-video inputs into thedevice. J11 is used for the S-video inputs and J2 for the composite inputs on the EVM.

The input port can also be driven by LCD imagers connected to connectors J30 and

J31. The imager or encoder is selectable via software control on I2C bus by accessingMSP430 registers.

2.2.1 On Chip Video Output DAC

The DM355 incorporates 1 composite video output DAC to interface to various videooutput standards. The DAC is filtered and driven to RCA jack, J4.



2.2.2 AIC33 Interface

The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output ofaudio signals. The codec samples analog signals on the microphone or line inputs andconverts them into digital data so it can be processed by the DSP. When the DSP isfinished with the data it uses the codec to convert the samples back into analog signalson the line output so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internal

configuration registers and one to send and receive digital audio samples. The I2C busis used as the AIC33’s control channel. The control channel is generally only usedwhen configuring the codec, it is typically idle when audio data is being transmitted,

McBSP1 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The EVM examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side.

The codec is clocked via a 27 Mhz oscillator. The internal sample rate generatorsubdivides the default system clock to generate common audio frequencies. Thesample rate is set by a codec register. The figure below shows the codec interface onthe DM355 EVM.

Figure 2-2, DM355 EVM CODEC INTERFACE

DOUTDIN

BCLKWCLK

MIC IN

LINE IN

LINE OUT

HP OUT

McBSP

I2S Format

AIC33 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT

SCLSDA

I2CControlSCL

SDAI2C Format

DRDXCLKRCLKXFSRFSX

Control Registers

ADC

DAC


2-5

2.3 Ethernet Interface

The DM355 EVM incorporates an ethernet controller chip. This interface is connectedto the DM355’s EMIF. The EVM uses an Intel DAVICOM DM9000A. The 10/100 Mbitinterface is isolated and brought out to a RJ-45 standard ethernet connector, P5. Theethernet address is stored in the ethernet controller’s SPI ROM during manufacturing.

The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellowand indicate the status of the ethernet link. The green LED, when on, indicates link andwhen blinking indicates link activity. The yellow LED, when illuminated, indicates fullduplex mode.

2.4 I2C Interface

The I2C bus on the DM355 is ideal for interfacing to the control registers of many

devices. On the DM355 EVM the I2C bus is used to configure the video decoder,

stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is alsointerfaced via the serial bus. The format of the bus is shown in the figure below.

The addresses of the on board peripherals are shown in the table below.

Table 1: I2C Memory Map

Device Address R/W Function

TVP5146 0x5D R/W Capture 1 Decoder

TLV320AIC33 0x1B R/W CODEC

MSP430 0x25 R/W LEDs, IR, RTC, User I/O

Figure 2-4, I2C Bus Format

Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop

Write Sequence

Start Slave Address R Data STOP

Read Sequence



2.4.1 MSP430

The DM355 EVM incorporates infrared remote, real time clock, and user and system bit

I/O in a MSP430 microcontroller. The I2C interface is used on the DM355 processor to

communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus.

2.5 Daughter Card Interfaces

The EVM provides expansion connectors that can be used to accept plug-in daughtercards. The daughter card allows users to build on their EVM platform to extend itscapabilities and provide customer and application specific I/O. The expansionconnectors are interfaces which include McBSP, and serial I/O expansion. The unusedEMIF signals are brought out as user GPIO signals. The video output port is broughtout to the daughter card interface along with I/O and imager interface.

2.6 DM355 CPU/Video Clocks

The DM355 EVM uses a 24 Megahertz crystal to generate the main input clock. TheDM355 has an internal PLL which can multiply the input clock to generate the internalclock. The PLL multiplier is set via software on the DM355 device.

The secondary clock is generated from a 27 Megahertz crystal. the clock domain isgenerally used for internal video clock generation.


2-7

2.7 Battery

The DM355 EVM incorporates a battery holder to provide backup power to theMSP430’s real time clock when the power is not applied to the board. The optionalbattery should be +3 volt 20 millimeter coin type Lithium single cell.

Some common part numbers for batteries which should operate in the EVM are shownin the table below.

These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,Sony, Sieko, Toshiba, Varta, and other battery manufacturers.

Table 2: Battery Part Numbers

Part Numbers

CR2032

DL2032

BR2032

CR2025

BR2025

CR2016

BR2016

DL2016



3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the DM355 EVM and itsinterfaces.

Topic Page

3.1 Board Layout 3-33.2 Connectors 3-53.2.1 J1, NTSC/PAL Select 3-63.2.2 J2, Video In 3-73.2.3 J3, MSP430 JTAG Header 3-73.2.4 J4, Composite Video Out 3-83.2.5 J5, USB Connector and Jumpers 3-83.2.6 J6, 14 Pin External JTAG Connector 3-93.2.7 J8, ARM JTAG Emulation Header 3-103.2.8 J9, USB Capacitance Select 3-103.2.9 J10, USB ID Select 3-113.2.10 J11, S-Video In 3-113.2.11 J12, ATA/CE Interface 3-123.2.12 J16, +5V Input 3-133.2.13 J27, MMC/SD Connector 3-133.2.14 J28, MMC/SD Connector 3-143.2.15 J30, Imager Interface Connector 1 3-153.2.16 J31, Imager Interface Connector 2 3-163.2.17 P1, Microphone In 3-173.2.18 P2, Headphone Out 3-183.2.19 P3, Line Out 3-183.2.20 P4, RS-232 UART 3-193.2.21 P5, Ethernet Interface 3-203.2.22 P6, Line In 3-213.2.23 DC3, I/O Daughter Card Expansion 3-223.2.24 DC5, TH8200 Daughter Card Interface 3-233.2.25 DC6, Expansion Connector 3-243.2.26 DC7, Expansion Connector 3-243.2.27 U10, Infrared Interface 3-25



Topic Page

3.3 LEDs 3-253.4 Switches 3-263.4.1 SW1, EMU0/1 Select Switch 3-263.4.2 SW5, Reset Switch 3-273.4.3 SW6, User Readable 4 Position DIP Switch 3-273.4.4 SW7, ARM Boot Mode Select 3-283.4.5 SW10 - SW14 3-283.5 Test Points 3-29


3-3

3.1 Board Layout

The DM355 EVM is a 5.0 x 6.5 inch (127 x 165 mm.) ten (10) layer printed circuit boardwhich is powered by an external +5 volt only power supply. Figure 3-1 shows the layoutof the top side of the DM355 EVM.

Figure 3-1, DM355 EVM, Interfaces Top Side

U10

J16

J1

P1

J2

P5BHT1

J5

DS14-DS21

DC5

J3 SW5

SW10

SW12

SW11

SW13

SW14

J31

J30

P6

P3

P2

J28

J8

J6

P4

DC6

DC3

SW6

J11

J4

DS5

S1

SW7

DC7

J13

J9

J10



Figure 3-2 shows the layout of the bottom side of the DM355 EVM.

Figure 3-2, DM355 EVM, Interfaces Bottom Side

J12

J27


3-5

3.2 Connectors

The EVM has numerous connectors and option jumpers to control and provideconnections to various peripherals. These connectors and jumpers are described in thefollowing sections.

Table 1: Connectors

Connector Size Function

J1 1 x 3 NTSC/PAL Video Select

J2 Video In

J3 2 x 7 MSP430 JTAG

J4 8 Composite Video Out

J5 1 x 4 Mini A/B USB Connector

J6 2 x 7 TI 14 Pin JTAG

J8 2 x 8 ARM JTAG Emulation Header

J9 2 x 1 USB Capacitor

J10 2 x 1 USB ID Jumper

J11 4 Video In

J12 12 x 1 ATA/CE Interface

J13 4 x 2 Spare Jumper Storage

J16 2 +5V In

J27 18 SD/MMC Connector

J28 18 SD/MMC Connector

J30 13 x 2 Imager Interface

J31 13 x 1 Imager Interface

P1 4 Microphone In

P2 2x5 Headphone Out

P3 4 Line Out

P4 9 RS-232 UART

P5 12 Ethernet

P6 4 Line In

DC3 15 x 2 I/O Daughter Card Expansion

DC5 25 x 2 THS8200 Daughter Card Interface

DC6 5 x 2 Expansion Connector

DC7 10 x 2 GP I/O Signals

U10 Infrared Receiver



3.2.1 J1, NTSC/PAL Select

The J1 connector is a 3 position jumper located on the top side of the board and is usedto select the type of video data the DM355 will be working with. NTSC format isexpected if the jumper is in the 1-2 position. The selection of 2-3 indicates PAL formatdata will be used. Either the NTSC (1-2 position) or PAL (2-3 position) must beselected. To reconfigure this selection, power down the EVM, change the jumper, andthen power the board back up. Do NOT change this jumper with the power on. Theimage of this jumper is shown in the figure below.

Table 2: J15, NTSC/PAL Select

Video Format Position

NTSC 1-2

PAL 2-3

J1

Figure 3-3, J1, NTSC/PAL Select

1

NTSC

PAL

J1

1

NTSC

PALPAL FormatNTSC Format

Board Edge


3-7

3.2.2 J2, Video In

J2 is an RCA jack used as a composite video input to the TVP5146 encoder. Thisconnector brings in a video signal to pin 8 on the TVP5146. Do NOT plug into thisconnector with the power on. The figure below shows this connector as viewed from thecard edge.

3.2.3 J3, MSP430 JTAG Header

The J3 MSP430 JTAG Header is located on the top side of the board and is used toprovide a programming interface to the MSP430 microcontroller. The pinout forthe J3 connector is shown in the table below. This connector is typically used for factoryuse only.

Table 3: J2, Video In, RCA Jack

Pin # Signal Name

1 Pin 8, TVP5146

2 GND

Table 4: J3, MSP430 JTAG Header

Pin # Signal Pin # Signal

1 430_TDO 2 NC

3 430_TDI 4 MSP430_3V3

5 430_TMS 6 NC

7 430_TCK 8 NC

9 GND 10 NC

11 430_RESET 12 NC

13 NC 14 NC

Figure 3-4, J2, Video In RCA Jack

Pin 2, Shield (ground)

Pin 1, Signal Input

J3

2

MSP430 EMU

1

Figure 3-5, J3, MSP430 JTAG Header

Board Edge



3.2.4 J4, Composite Video Out

Connector J4 is an RCA jack used as a composite video output from the “TVOUT”signal of the TMS320DM355. Do NOT plug into this connector with the power on. Thefigure below shows this connector as viewed from the card edge.

3.2.5 J5, USB Connector and Jumpers

Connector J5 is a mini A/B USB connector. The pinout for the J5 connector is shown inthe figure below.

* Use internal register to swap DM/DP pair. This feature was used to improve printed circuit board routing.

The EVM incorporates the ability to toggle the ID pin on the USB connector viasoftware control. The GIO2 pin on the DM355 controls this function.

For “USB ON The Go” mode remove jumper J10. This will allow the cable to configurethe ID pin on the DM355 processor.

The EVM supplies up to 500 ma of current to the USB_VBUS via a TPS61092 DC/DCconverter. This is enabled via the DM355’s DRV_VBUS pin. J9 supplies extracapacitance for host mode operations. Remove J9 for “USB On The Go” operations.Spare jumpers can be stored on connector J13.

Table 5: J4, TV Out, RCA Jack

Pin # Signal Name

1 Composite video output

2 GND

Table 6: J5, USB Connector

Pins Signal

1 USB_VBUS

2 USB_DM

3 USB_DP

4 USB_ID

5-9 USB_SHIELD

Figure 3-6, J4, TV Out, RCA Jack

Pin 2, Shield (ground)

Pin 1, Composite Signal


3-9

3.2.6 J6, 14 Pin External JTAG Connector

Connector J6 is a 2 x7 double row male header with pin 6 clipped to serve as a key.This is the standard interface used by JTAG emulators to interface to TexasInstruments DSPs. The pinout for the connector is shown in the figure below.

The signal names for each pin are shown in the table below.

* Note: EMU0/EMU1 mode must be selected to ICEPICK mode

Table 7: J6, JTAG Interface

Pin # Signal Name Pin # Signal Name

1 TMS 2 TRST-

3 TDI 4 GND

5 PD 6 no pin - key

7 TDO 8 GND

9 TCKRET 10 GND

11 TCK 12 GND

13 EMU0 14 EMU1

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-7, JTAG INTERFACE



3.2.7 J8, ARM JTAG Emulation Header

The J8 Emulation Header is located on the top side of the board and is used to providean interface to ARM compatible JTAG emulators. The pinout for this connector isshown in the table below.

* Note: EMU0/EMU1 switch must be set to ARM mode

3.2.8 J9, USB Capacitance Select

The J9 jumper is used to provide more capacitance when the USB connector is used inthe host mode. When the jumper is shorted the extra capacitance is provided. Theseopen and shorted position are shown below.

Table 8: J8, ARM JTAG Emulation Header


1 VCC_3V3 2 VCC_3V3

3 ARM_TRSTn 4 Ground

5 ARM_TDI 6 Ground

7 ARM_TMS 8 Ground

9 ARM_TCK 10 Ground

11 ARM_TCKRET 12 Ground

13 ARM_TDO 14 Ground

15 ARM_RSTn 16 Ground

17 NC 18 Ground

19 NC 20 Ground

Table 9: J9, USB Capacitance Select

Position Function

Open 6.9 uF Capacitance

Shorted 106.8 uF Capacitance

J9

Figure 3-8, J9, USB Capacitance Select

USB VBUS

Open

J9

USB VBUS

Shorted


3-11

3.2.9 J10, USB ID Select

The J10 jumper is used to allow the cable to configure the ID pin on the DM355. This isused for the “USB On The Go” mode. When the jumper is shorted, access to the ID isprovided. The open and shorted position are shown below.

3.2.10 J11, S-Video In

Connector J11 is a four pin mini din connector which interfaces to the TVP5146encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146. Do NOT plug into this connector with the power on. The figure below shows thisconnector as viewed from the card edge.

Table 10: J10, USB ID Select

Position Function

Open ID from USB connector

Shorted ID controlled from GIO2

Table 11: J11, Video In, Mini Din Connector

Pin # Signal Name

1 GND

2 GND

3 LUMA

4 Chroma

J10

Figure 3-9, J10, USB ID Select

USB ID

Open

J10

USB ID

Shorted

Pin 1 Pin 2Pin 3 Pin 4

Figure 3-10, J11, Front View, Mini Din Connector



3.2.11 J12, ATA/CE Interface

Connector J12 is a 12 x 1 flex cable connector mounted on the bottom side of theboard. The signals on this connector parallel the signals present on the connector J28which is located on the top side of the board. The signals present on connector J12 areshown in the table below. when this connector is used the corresponding SD connectorcan not be used.

Table 12: J12, ATA/CE Interface

Pin # Signal Name

1 Ground

2 SD1_DAT2

3 SD1_DAT3

4 VCC_3V3

5 SD1_CMD

6 VCC_3V3

7 SD1_CLK

8 Ground

9 SD1_DATA0

10 SD1_DATA1

11 Ground

12 NC


3-13

3.2.12 J16, +5V Input

Connector J16 is the input power connector. This connector bring in +5 volts to theEVM. This is a 2.5mm. jack. Inside of the jack is tied to through a fuse to VCC_5V.The other side is tied to ground and LED DS5. The figure below shows this connectoras viewed from the card edge.

3.2.13 J27, MMC/SD Connector

The J27 MMC/SD connector is located on the bottom side of the board and is used toprovide an interface to a MMC/SD card. The pinout for the J27 connector is shown inthe table below.

Table 13: J27, MMC/SD Connector


1 SD0_DATA3 2 SD0_CMD

3 GND 4 VCC_3V3

5 SD0_CLK 6 GND

7 SD0_DATA0 8 SD0_DATA1

9 SD0_DATA2 10 Write Protect 0

11 GND 12 Insert 0

PC Board

J16+5V

Ground

Front ViewFigure 3-11, J16, +5 Volt Input Connector



3.2.14 J28, MMC/SD Connector

The J28 MMC/SD connector is located on the top side of the board and is used toprovide an interface to a MMC/SD card. The signals present on J28 are also presenton J12. Therefore, when J28 is used the operator can not use J12 for a CE-ATA diskdrive. The pinout for the J28 connector is shown in the table below.

Table 14: J28, MMC/SD Connector


1 SD1_DATA3 2 SD1_CMD

3 GND 4 VCC_3V3

5 SD1_CLK 6 GND

7 SD1_DATA0 8 SD1_DATA1

9 SD1_DATA2 10 Write Protect 1

11 GND 12 Insert 1


3-15

3.2.15 J30, Imager Interface Connector 1

The connector J30 is a 13 x 2 double row header which is part of the imager interface.It is used with connector J31. The pinout for the J30 connector is shown in the tablebelow.

Note: When using the imager the user needs to select the video input multiplier to

imager mode via I2C control registers in the MSP430.

Table 15: J30, Imager Interface Connector 1


1 IMAGER_D4 2 IMAGER_D5





11 Ground 12 Ground

13 IMAGER_LINE_VALID 14 NC

15 NC 16 IMAGER_RESET

17 IMAGER_FRAME_VALID 18 I2C_DATA_IMG

19 I2C_SCLK_IMG 20 NC

21 IMAGER_VBUS 22 IMAGER_VBUS

23 IMAGER_PXCLK 24 Ground

25 Ground 26 Ground



3.2.16 J31, Imager Interface Connector 2

The connector J31 is a 13 x 1 single row header which is part of the imager interface. It is used with connector J30. The pinout for the J31 connector is shown in the tablebelow.

Note: When using the imager the user needs to select the video input multiplier to

imager mode via I2C control registers in the MSP430.

3.2.17 P1, Microphone In

The microphone input, P1 is a 3.5 mm. stereo jack. Both inputs are connected to themicrophone so it is monaural. The signal is connected to signals “MIC3R” and “MIC3L”of the AIC33. The signals on the plug are shown in the figure below.

Table 16: J30, Imager Interface Connector 1

Pin # Signal

1 IMAGER_D0

2 IMAGER_D1

3 NC

4 NC

5 NC

6 NC

7 NC

8 NC

9 NC

10 IMAGER_GBL_SHUTTER

11 IMAGER_TRG

12 NC

13 Ground

Microphone In

Ground

Figure 3-13, Microphone Input Jack


3-17

3.2.18 P2, Headphone Out

The P2 connector is a 3.5 mm. stereo headphone output from the TVL320AIC33 on theEVM. This connector is located on the top side of the board. A view of the connectorfrom the card edge is shown in the figure below. The signals present on this connectorare defined in the following table.

3.2.19 P3, Line Out

The audio line out connector P3, is a stereo output. The output connector is a 3.5 mmstereo jack. The signals on the mating plug are shown in the figure below.

Table 17: P2, Headphone Out Interface

Pin # AIC33 Signal

1 Ground

2 HPLOUT

3 HPROUT

4 NC

Table 18: P3, Audio Line Out Stereo Jack

Pin # AIC33 Signal

1 Ground

2 LEFT_LO+

3 RIGHT_LO+

4 NC

Figure 3-14, P2, Headphone Out Interface

Stereo Line Out

Left Line Out

Ground

Figure 3-15, Audio Line Out Stereo Jack

Right Line Out



3.2.20 P4, RS-232 UART

The P4 connector is a 9 pin make D-connector which provides a UART interface to theEVM. This connector interfaces to the MAX 3221 RS-232 line driver (U34) and islocated on the top side of the board. A view of the connector from the card edge isshown in the figure below. The signals present on this connector are defined in thefollowing table.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.

Table 19: P4, RS-232 Pinout

Pin # Signal Name

1 NC

2 DM355 UART0 Rx Data

3 DM355 UART0 Tx Data

4 NC

5 GND

6 NC

7 Pin 8

8 Pin 7

9 NC

Figure 3-16, P4, DB9 Male Connector

6789

12345


3-19

3.3.21 P5, Ethernet Interface

The P5 connector is located on the top side of the board and is used to provide anEthernet interface. P5 integrates the magnetics and standard RJ-45 connector. Thetwo tables below shoe the signals present on the magnetics interface and theconnector side.

The ethernet connector incorporates 2 LEDs which give link and transmit status fromthe ethernet controller.

Table 20: P5, Magnetics/LEDs Interface Signals


1 ENET_TXO+ 2 ENET_TXO-

3 ENET_RXI+ 4 ENET_2V5(RX Center Tap)

5 ENET_2V5(RX Center Tap) 6 ENET_RXI-

7 NC 8 GND

9 VCC_3V3(LED1+) 10 ENET_LED1(LED1-)

11 VCC_3V3(LED2+) 12 ENET_LED2(LED2-)

Table 21: P5, RJ-45 Connector


1 TX_DATA+ 2 TX_DATA-

3 RX_DATA+ 4 NC

5 NC 6 RX_DATA-

7 NC 8 NC



3.2.22 P6, Line In

Connector P6 is an stereo audio line input. The input connector is a 3.5 mm stereo jack.The signals on the mating plug are shown in the figure below.

Table 22: P6, Headphone Out Interface

Pin # AIC33 Signal

1 Ground

2 LINE2L+

3 LINE2R+

4 NC

Right Line In

Ground

Figure 3-17, P6, Audio Line In Stereo Jack

Left Line In


3-21

3.2.23 DC3, I/O Daughter Card Expansion

The DC3 connector is an I/O expansion interface for a daughter card. This is a15 x 2 pinned female surface mount connector. The pinout for the DC3 connector isshown in the table below.

The manufacturer and part number of this connector is: SAMTEC SFM-115-02-S-D-LC

A possible mating connector is: SAMTEC TFM-115-32-S-D-LC. This height is.44 inches. Your actual height may vary.

Table 23: DC3, I/O Daughter Card Expansion


1 SPI1_SDENA0 2 NC

3 SPI1_SDI 4 SPI_SDO

5 SPI1_CLK 6 DM355_TIMERIN3

7 Ground 8 Ground

9 McBSP_DR0 10 McBSP_DX0

11 McBSP_CLKR0 12 McBSP_CLKX0

13 McBSP_FSR0 14 McBSP_FSX0

15 Ground 16 Ground

17 SYS_RESETz 18 I2C_SCLK

19 UART1_TXD 20 I2C_DATA

21 UART1_RXD 22 Ground

23 Ground 24 GIO18

25 VCC_3V3 26 VCC_3V3

27 Ground 28 Ground

29 VCC_5V 30 VCC_5V



3.2.24 DC5, TH8200 Daughter Card Interface

The DC5 connector is an expansion interface for the TH8200 daughter card. This is a25 x 2 pinned female surface mount connector. The pinout for the DC5 connector isshown in the table below.



Table 24: DC5, TH8200 Daughter Card Interface


1 VDOUT_LCD_OE 2 GIO16

3 VDOUT_FIELD 4 GIO17

5 DM355_GIO6 6 DM355_GIO7

7 Ground 8 Ground

9 VDOUT_C0 10 VDOUT_C1




17 Ground 18 Ground

19 VDOUT_EXTCLK 20 CDOUT_HSYNC

21 Ground 22 Ground

23 VDOUT_VCLK 24 CDOUT_VSYNC

25 Ground 26 Ground

27 VDOUT_Y0 28 VDOUT_Y1




35 Ground 36 Ground

37 I2C_SCLK 38 DC5_RESETn

39 I2C_DATA 40 Ground

41 VCC_1V8 42 VCC_1V8

43 Ground 44 Ground

45 VCC_3V3 46 VCC_3V3

47 Ground 48 Ground

49 VCC_5V 50 VCC_5V


3-23

3.2.25 DC6, Expansion Connector

The DC6 connector is an expansion connector used to provide compatibility with theTHS8200 video daughter card. This is a 5 x 2 pinned female surface mount connector.The pinout for the DC6 connector is shown in the table below.



3.2.26 DC7, Expansion Connector

Extra EMIF signals are available as general purpose I/O in some configurations.Connector DC7 provides access to these pins. This is a 10 x 2 pinned female surfacemount connector. The pinout for the DC7 connector is shown in the table below.

Table 25: DC6, Video Output Connector


1 NC 2 NC

3 VCC_3V3 4 Ground

5 NC 6 NC

7 NC 8 NC

9 Ground 10 Ground

Table 26: DC7, Expansion Connector


1 GIO54 2 GIO67

3 GIO65 4 GIO31

5 GIO63 6 GIO64

7 Ground 8 Ground

9 GIO62 10 GIO61

11 GIO60 12 GIO59

13 GIO58 14 GIO57

15 GIO56 16 GIO032

17 Ground 18 Ground

19 VCC_3V3 20 VCC_3V3



3.2.27 U10, Infrared Interface

U10 is an infrared receiver mounted on the edge of the board. This device interfaces tothe MSP430 mircrocontroller. The view of U10 is shown from a board edge view in thefigure below.

The receiver supports interaction with an Infrared remote control included with yourEVM

3.3 LEDs

The EVM has ten (10) LEDs which are located on the top side of the board. Information regarding the LEDs are shown in the table below.

Table 27: LEDs

LED # Use Color

DS5 +5 Volts present Green

DS14 User control via MSP430 I2C Green








DS22 Boot Mode Status Green

Figure 3-18, U10, IR Interface, Card Edge View

U10

PC Card


3-25

3.4 Switches

The EVM has nine (9) switches. The function of these switches are shown in the tablebelow.

3.4.1 SW1, EMU0/1 Select Switch

SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0and EMU1 pins on the TMS320DM355 processor. A view of the switch is shown in thefigure below. The selection options with this switch are in the table below.

* is the factory shipped configuration

Table 28: Switches

Switch Function Type

SW1 EMU0/EMU1 Control 4 Position DIP

SW5 Reset Push Button/Momentary

SW6 User Readable 4 Position DIP

SW7 ARM Boot Mode Select 2 Position DIP

SW10 User Readable Push Button/Momentary





Table 29: SW1, EMU0/1 Select

State at ResetEMU1 EMU0

Function

L(0) L(0) Emulation Debug ARM JTAG Enabled

L(0) H(1) Not Defined

H(1) L(0) Not Defined

H(1) H(1) ICE PICK Mode *Both ARM & DSP JTAG Enabled

Figure 3-19, SW1, EMU0/1 Select Switch EMU0

EMU1

H L

S1

Raised NIB



3.4.2 SW5, Reset Switch

Switch SW5 is a push button reset switch that will RESET the board. The MSP430controls all reset and power monitoring logic on the EVM.

3.4.3 SW6, User Readable 4 Position DIP Switch

Switch SW6 is a 4 position DIP switch with each position being an input to the

MSP430 microcontroller and accessible to the DM355 via the I2C control registers.The table below shows what signal each position appears on.

.

Table 30: SW6, User Readable 4 Position DIP Switch

Position Signal

1 SW_DIP0

2 SW_DIP1

3 SW_DIP2

4 SW_DIP3

Figure 3-20, SW6, User Readable 4 Position DIP Switch SW6

4

Raised NIB

321

ON


3-27

3.4.4 SW7, ARM Boot Mode Select

Switch SW7 is a 2 position DIP switch used to select the ARM Boot Mode. The figureand table below show these options.

* default setting

3.4.5 SW10 - SW14

Switches S10 through SW14 are push button momentary switches that are inputs in to

the MSP430 microcontroller and accessible to the DM355 via I2C control registers onthe MSP430. The table below shows what signal each switch appears on.

Table 31: SW7, ARM Boot Mode Select

Pos 2 Pos 1 HW Code Function

ON ON 0 0 NAND boot CE0 *

ON OFF 0 1 NOR direct execute

OFF ON 1 0 Boot from SD/MMC

OFF OFF 1 1 Boot from UART

Table 32: SW10 - SW14, Processor Configuration/Boot Load Options

Switch Signal

SW10 PB_SW10

SW11 PB_SW11

SW12 PB_SW12

SW13 PB_SW13

SW14 PB_SW14

Figure 3-21, SW7, ARM Boot Mode Select

BOOT MODE

SW71 2

Raised NIBON



3.5 Test Points

The EVM has 35 test points. All test points appear on the top of the board. Thefollowing figure identifies the position of each test point. the next table list each testpoint and the signal appearing on that test point.

Figure 3-22, DM355 EVM, Test Points

TP1

TP5

TP8

TP13

TP27

TP21

TP25

TP39,TP40

TP31

TP30

TP32

TP36TP11

TP41

TP12

TP29

TP42

TP6

TP26

TP33,TP34

TP37,TP38

TP22,TP23

TP27

TP3,TP4

TP9

TP7

TP10,TP43

TP2,TP14


3-29

There are 12 power test points on the EVM. These test points provide a convenientmechanism to check the EVM’s multiple power supplies. The table below shows thevoltages for each test point and what the supply is used for.

Table 33: DM355 EVM Test Points

Test Point #

SignalTest Point

#Signal

TP2 VCC_1V8 TP29 Ground

TP3 AIC33 MFP2 TP30 Ground

TP4 AIC33 MFP3 TP31 VCC_5V

TP10 EM_ADV/GIO032 TP32 3V3_PWR_OK

TP13 VDDA_DAC TP33 VCC_3V3

TP14 EM_CLK/GIO031 TP36 1V8_PWR_OK

TP21 CORE_PWR_OK TP37 VCC_1V8

TP23 VCC_1V3 TP39 TMS320DM355 MXI2

TP25 Ground TP40 TMS320DM355 MXO2

TP26 Ground TP41 TMS320DM355 MXI1

TP27 Ground TP42 TMS320DM355 MXO1

TP28 Ground TP43 EM_A7

Table 34: Power Test Points

AccessTest Point

Voltage Shunt Power Domain

TP1 +1.8V 0.02 ohms VDDAHV3V3

TP5 +1.3V 0.02 ohms CVDD

TP6 +1.8V 0.02 ohms VDDA1V8 HSSI

TP7 +1.3V 0.02 ohms USB1V3

TP8 +3.3V 0.02 ohms USB3V3

TP9 +1.3V 0.02 ohms VDDA.PLL1 & 2

TP11 +3.3V 0.02 ohms VDD

TP12 +1.8V 0.02 ohms VDDS

TP22 +1.3V 0.02 ohms Main 1.3V

TP34 +3.3V 0.025 ohms Main 3.3V

TP38 +1.8V 0.025 ohms Main 1.8V

TP12 +1.8V 0.025 ohms DDR2 Power



A-1

Appendix A

Schematics

This appendix contains the schematics for the DM355 EVM.


A-2 DM355 EVM Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D2

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Wed

ne

sda

y, J

an

ua

ry 3

0,

20

081

26

B

DM

35

5

Eva

lua

tion

Mod

ule

TIT

LE

SH

EE

T

33

34

AA

ENGR

2REVISION STATUS OF SHEETS

111

DATE

14

12

13

DATE

ENGR-MGR

MFG

7

DWN

DATE

8

DATE

10

DATE

CHK

RLSE

APPLICATION

35

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

15

DD

DA

A

AA

D2

A

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

04/01/2007

04/01/2007

16

17

18

19

20

21

22

23

24

25

04/01/2007

04/01/2007

04/01/2007

04/01/2007

04/01/2007

AC

AA

AA

A

AA

26

27

28

29

30

AA

31

32

A

D2

AA A

DD

D

AA

A

D2

AInitial schematic ready

for layout - Alpha Release

DESCRIPTION

REV

APPROVED

DATE

04/01/07

RRP

SCHEMATIC

CONTENTS

SHEET01 - TITLE

SHEET02 - DM355 SERIAL I/O

SHEET03 - DM355 DDR2 INTERFACE

SHEET04 - DM355 EMIF

SHEET05 - DM355 USB

SHEET06 - DM355 VIDEO

SHEET07 - DM355 JTAG,CLKS,RESET

SHEET08 - DM355 POWER/GND-pins

SHEET09 - DM355 DECOUPLING CAPS

SHEET10 - DDR2 MEMORY

SHEET11 - JTAG CONNECTORS

SHEET12 - NAND FLASH, SPI EEPROM, EMIF I/O DC

SHEET13 - RS232 INTERFACE

SHEET14 - SD/MMC IF - CE ATA IF

SHEET15 - VIDEO INPUT MULTIPLEXER

SHEET16 - IMAGER INTERFACE

SHEET17 - 5146 DECODER

SHEET18 - VIDEO DAUGHTER CARD IF

SHEET19 - AIC33

SHEET20 - DM9000A ENET CONTROLLER

SHEET21 - ETHERNET CONNECTOR

SHEET22 - MSP430

SHEET23 - LEDS/SWITCHED ETC

SHEET24 - I/O DAUGHTER CARD IF

SHEET26 - CORE PWR SUPPLY,MSP430 PWR SUPPLY

SHEET27 - 3V3 AND 1V8 POWER SUPPLY

00011011B

01011101B

AUDIO CODEC - 00110(MFP1)(MFP0)

AIC33

VIDEO DECODER - 101110(I2CA)

TVP5146

MSP430

ADDRESS BINARY

DEVICE

FUNCTION

HEX

0x25

0x1B

0x5D

I2C

Address Table

ADDRESS

FUNCTION

HEX

Memory Address Table

00100011B

RTC,IR CTL, IO CTL, POWER MONITOR

CHIP SELECT

NAND FLASH CS0 R/W

NAND FLASH CS1 R/W

CE0 - NAND CS0

CE0 - NAND CS1

0x0200 0000

0x0200 4000

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

11

11

11

11

11

11

XX

FF

F

BASE

WORD

1

ARM ADDRESSING

RRP

07/01/07

BPre-production release - Beta Release

CE1 - PHY/MAC CHIP

DM9000A READ WRITE

0x0401 4000

09/01/07

RRP

CProduction release for 0.50 mm

RRP

Pre-production release for 0.65 mm

D09/28/07


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I2C

_D

AT

A

I2C

_SC

LK

McB

SP

_DX

1M

cBS

P_C

LKX

1M

cBS

P_F

SX

1M

cBS

P_

DR

1M

cBS

P_

CL

KR

1M

cBS

P_

FS

R1

McB

SP

_C

LK

S1

SD

0_D

AT

A1

SD

0_D

AT

A2

SD

0_

CL

K

SD

0_D

AT

A0

SD

0_

CM

DS

D0_

DA

TA

3

SD

1_D

AT

A1

SD

1_D

AT

A2

SD

1_

CL

K

SD

1_D

AT

A0

SD

1_

CM

DS

D1_

DA

TA

3

McB

SP

_F

SR

0M

cBS

P_

CLK

R0

McB

SP

_D

R0

McB

SP

_FS

X0

McB

SP

_CLK

X0

McB

SP

_DX

0

CP

U_

GIO

25

CP

U_

GIO

26

CP

U_

GIO

27

CP

U_

GIO

28

CP

U_

GIO

29

CP

U_

GIO

30

VC

C_

3V

3

UA

RT

0_T

XD

13

UA

RT

0_R

XD

13

McB

SP

_FS

X1

19M

cBS

P_C

LKX

11

9M

cBS

P_D

X1

19 McB

SP

_C

LKR

119

McB

SP

_C

LKS

119

McB

SP

_F

SR

119

McB

SP

_DR

119

SD

1_C

MD

14

SD

1_D

AT

A2

14

SD

1_D

AT

A0

14

SD

1_

CLK

14

SD

1_D

AT

A3

14

SD

1_D

AT

A1

14

SD

0_C

MD

14

SD

0_D

AT

A2

14

SD

0_D

AT

A0

14

SD

0_

CLK

14

SD

0_D

AT

A3

14

SD

0_D

AT

A1

14

I2C

_D

AT

A1

5,1

8,1

9,2

2,2

4

I2C

_S

CL

K1

5,1

8,1

9,2

2,2

4

DE

EP

SL

P_

EN

22

McB

SP

_DX

024

McB

SP

_CLK

X0

24M

cBS

P_F

SX

024

McB

SP

_D

R0

24M

cBS

P_C

LKR

024

McB

SP

_F

SR

024

DM

350_

GIO

718

DM

350_

GIO

618

SP

I0_S

DO

12S

PI0

_S

DI

12S

PI0

_SC

LK12

SP

I0_S

DE

NA

012

SP

I1_

SD

O24

SP

I1_

SD

I24

SP

I1_

SC

LK24

SP

I1_

SD

EN

A0

24

AT

A_C

E_

IO14

DM

350

_T

IME

RIN

324

UA

RT

1_T

XD

24

UA

RT

1_R

XD

24

EN

ET

_IN

T2

0U

SB

_ID

_T

OG

GL

E5

MS

P43

0_IN

T22

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

22

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 S

ER

IAL

I/O

RN

22

RP

AC

K4

-33

1 2 3 45678

R1

35

2.2

KR

11

52

.2K

RN

9R

PA

CK

8-3

31 2 3 4 5 6 7 8

910111213141516

RN

21

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

RN

23

RP

AC

K4

-33

1 2 3 45678

DM

355_

65M

M

U1

8-1

I2C

_SC

L / G

IO14

R14

I2C

_SD

A /

GIO

15R

13

GIO

0C

16

GIO

1E

14

GIO

2F

15

GIO

3G

15

GIO

4B

17

GIO

5D

15

GIO

6B

18

GIO

7C

17

AS

P0_

CLK

R/G

IO26

F17

AS

P0_

CLK

X/G

IO29

F18

AS

P0_

DR

/GIO

27E

18

AS

P0_

DX

/GIO

30H

15

AS

P0_

FS

R/G

IO25

F16

AS

P0_

FS

X/G

IO28

G17

AS

P1_

CLK

RD

18

AS

P1_

CLK

SD

17

AS

P1_

CLK

XD

19

AS

P1_

DR

C19

AS

P1_

DX

C18

AS

P1_

FS

RE

17

AS

P1_

FS

XE

16

MS

/SD

0_C

LKA

15

MS

_BS

/SD

0_C

MD

C14

MS

/SD

0_D

AT

0B

14M

S/S

D0_

DA

T1

D14

MS

/SD

0_D

AT

2B

13M

S/S

D0_

DA

T3

A14

SD

1_C

LK /

GIO

24C

15

SD

1_C

MD

/ G

IO23

A17

SD

1_D

0 / T

XD

2 / G

IO19

A18

SD

1_D

1 / R

XD

2 / G

IO20

B15

SD

1_D

2 / C

TS

2 / G

IO21

A16

SD

1_D

3 / R

TS

2 / G

IO22

B16

SP

I0_S

CLK

C12

SP

I0_S

DE

NA

0B

12

SP

I0_S

DI

A12

SP

I0_S

DO

B11

SP

I1_S

CLK

/ G

IO10

C13

SP

I1_S

DE

NA

/ G

IO11

E13

SP

I1_S

DI /

GIO

9A

13

SP

I1_S

DO

/ G

IO8

E12

UA

RT

0_R

XD

0U

18

UA

RT

0_T

XD

0T

18

UA

RT

1_R

XD

1/G

IO01

3R

15

UA

RT

1_T

XD

1/G

IO01

2R

17



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

DQ

3

DD

R_

ST

RB

EN

_D

EL

DD

R_

DQ

0

DD

R_

DQ

1

DD

R_

DQ

2

DD

R_

DQ

4

DD

R_

DQ

8

DD

R_

DQ

9

DD

R_

DQ

7

DD

R_

DQ

5

DD

R_

DQ

6

DD

R_

DQ

14

DD

R_

DQ

10

DD

R_

DQ

13

DD

R_

DQ

12

DD

R_

DQ

11

DD

R_

DQ

15

DD

R_

DQ

S0

DD

R_

DQ

S1

DD

R_

DQ

M0

DD

R_

DQ

M1

DD

R_

A1

3

DD

R_

A1

DD

R_

A0

DD

R_

A2

DD

R_

A3

DD

R_

A4

DD

R_

A7

DD

R_

A6

DD

R_

A5

DD

R_

A9

DD

R_

A1

0D

DR

_A

11

DD

R_

A8

DD

R_

A1

2

DD

R_

BA

0D

DR

_B

A1

DD

R_

BA

2

DD

R_

CK

E

DD

R_

CL

KP

DD

R_

CL

KN

DD

R_

CA

S

DD

R_

RA

S

DD

R_

WE

DD

R_

CS

VR

EF

_ST

LD

DR

_S

TR

BE

N

VC

C_

3V3

DD

R_

DQ

01

0

DD

R_

DQ

11

0

DD

R_

DQ

21

0

DD

R_

DQ

31

0

DD

R_

DQ

41

0

DD

R_

DQ

51

0

DD

R_

DQ

61

0

DD

R_

DQ

71

0

DD

R_

DQ

81

0

DD

R_

DQ

91

0

DD

R_

DQ

10

10

DD

R_

DQ

11

10

DD

R_

DQ

12

10

DD

R_

DQ

14

10

DD

R_

DQ

13

10

DD

R_

DQ

15

10

DD

R_

BA

01

0D

DR

_B

A1

10

DD

R_

CA

S1

0

DD

R_

CL

KP

10

DD

R_

RA

S1

0

DD

R_

WE

10

DD

R_

CL

KN

10

DD

R_

BA

21

0

DD

R_

DQ

M0

10

DD

R_

DQ

M1

10

DD

R_A

13

10

DD

R_A

10

10

DD

R_

A8

10

DD

R_

A5

10

DD

R_

DQ

S1

10

DD

R_

DQ

S0

10

DD

R_A

12

10

DD

R_

A9

10

DD

R_A

11

10

DD

R_

A7

10

DD

R_

A4

10

DD

R_

A6

10

DD

R_

A3

10

DD

R_

A2

10

DD

R_

A1

10

DD

R_

A0

10

DD

R_

CK

E1

0

DD

R_

CS

10

VR

EF

_S

TL

10

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

32

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 D

DR

IN

TE

RF

AC

E

Trace to DDR memory

for delay compensation

This net is equal to the DDR_CLKP ( or DDR_CLKN )

plus

the length of DDR_DQXX Average Trace length

TP

1 12

DM

355_

65M

M

U18

-4

DD

R_A

0V

2D

DR

_A1

V3

DD

R_A

10V

6D

DR

_A11

W7

DD

R_A

12V

7D

DR

_A13

U6

DD

R_A

2W

2D

DR

_A3

W3

DD

R_A

4V

4D

DR

_A5

W4

DD

R_A

6U

5D

DR

_A7

V5

DD

R_A

8W

5D

DR

_A9

W6

DD

R_B

A0

U8

DD

R_B

A1

U7

DD

R_B

A2

V8

DD

R_C

AS

V9

DD

R_C

KE

V10

DD

R_C

LKN

W8

DD

R_C

LKP

W9

DD

R_C

ST

8

DD

R_D

Q0

V11

DD

R_D

Q1

W11

DD

R_D

Q10

W14

DD

R_D

Q11

W15

DD

R_D

Q12

U16

DD

R_D

Q13

W16

DD

R_D

Q14

V16

DD

R_D

Q15

W17

DD

R_D

Q2

U11

DD

R_D

Q3

T11

DD

R_D

Q4

U12

DD

R_D

Q5

W12

DD

R_D

Q6

V13

DD

R_D

Q7

W13

DD

R_D

Q8

U13

DD

R_D

Q9

V14

DD

R_D

QM

0T

12

DD

R_D

QM

1U

15

DD

R_D

QS

0V

12

DD

R_D

QS

1V

15

DD

R_R

AS

T6

DD

R_G

AT

E0

W18

DD

R_G

AT

E1

V17

DD

R_Z

NT

9

DD

R_W

EW

10

DD

R_V

RE

FU

10

VS

SA

_DLL

R11

VD

DA

33D

DR

_DLL

R10

E1

NF

M2

01

2P1

3C1

05F

13

2

C1

2.2

uF

R3

0

C2

0.0

1u

FC

30

.01

uF

R1

0.0

20

R2

50

OH

M 0

.5%


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_D9

EM

_D

10E

M_

D11

EM

_D0

EM

_D

12E

M_

D13

EM

_D

14E

M_

D15

EM

_D1

EM

_D2

EM

_D3

EM

_D4

EM

_D5

EM

_D6

EM

_D7

EM

_D8

EM

_D

[15.

.0]

GIO

56

EM

_A1

EM

_A2

EM

_OE

EM

_WE

EM

_BA

1

GIO

67

EM

_A1

2

GIO

62

GIO

63

GIO

65G

IO64

GIO

31

GIO

032

GIO

57

GIO

58

GIO

59

GIO

60

GIO

62

GIO

63

GIO

64

GIO

61

GIO

65

EM

_A12

GIO

67

GIO

54

EN

ET

_CE

EM

_C

E0

VC

C_3

V3

VC

C_

3V3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3V

CC

_3V

3

EM

_D

[15

..0

]1

2,2

0

EM

_O

E1

2,2

0E

M_

WE

12

,20

EM

_C

E0

12

EM

_WA

IT12

EM

_B

A1

20

EN

ET

_C

E2

0

EM

_A

1212

EM

_A

212

EM

_A

112

GIO

03

212

GIO

54

12G

IO6

712

GIO

65

12

GIO

31

12

GIO

64

12G

IO6

312

GIO

62

12G

IO6

112

GIO

60

12G

IO5

912

GIO

58

12G

IO5

712

GIO

56

12

GIO

61

12

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

C

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

84

26

B

DM

355

E

valu

atio

n M

odul

e

DM

35

5 E

MIF

SW7 Boot Select Setting for ARM Boot Mode:

POS 2 POS 1

OFF

OFF

OFF

OFF

ON

ON

ON

ON

BOOT ROM - NAND LOAD FROM CE0

NOT AVAILABLE

BOOT ROM - LOAD FROM UART

BOOT ROM - LOAD FROM SD/MMC

1 1 0 1 NAND CFG

0 0

HW CODE

1 1

0 1

1 0

Note:

ICE PICK Mode may have an issue booting from Reset

EMU0 = 1, EMU1 = 1

use ARM Mode

EMU0 = 0, EMU1 = 0

See page 11 for more information

NAND BOOT STATUS

TP

431

RN

13

RP

AC

K4-

33

12345 6 7 8

R1

9N

O-P

OP

RN

11

RP

AC

K4-

33

12345 6 7 8

R2

2533

0

1 2

ON

SW

7

DIP

_S

WIT

CH

_2

1 234

RN

19

RP

AC

K4

-33

1 2 3 45678

DS

22

LE

D

R2

2910

K

R1

7N

O-P

OP

R1

4920

K

R1

41K

R2

3010

K

R1

5020

K

RN

14

RP

AC

K4-

33

1 2 3 45678

RN

16

RP

AC

K4-

33

1 2 3 45678

R15

1K

U1

9

SN

74LV

C1G

08

1 24

5 3

RN

18

RP

AC

K4-

33

1 2 3 45678

R15

110

K

DM

355_

65M

M

U1

8-3

EM

_A00

/ G

IO05

6M

16

EM

_A03

/ G

IO05

7N

18

EM

_A04

/ G

IO05

8P

15

EM

_A05

/ G

IO05

9R

19

EM

_A06

/ G

IO06

0P

18

EM

_A07

/ G

IO06

1P

16

EM

_A08

/ G

IO62

/ C

FG

0T

19

EM

_A09

/ G

IO63

/ C

FG

1P

17

EM

_A1

/ ALE

N17

EM

_A10

/ G

IO64

/ C

FG

2R

18

EM

_A11

/ G

IO65

/ C

FG

3R

16

EM

_A12

/ G

IO66

/ B

TS

EL0

U19

EM

_A13

/ G

IO67

/ B

TS

EL1

V19

EM

_A2

/CLE

N15

EM

_AD

V /

GIO

032

H16

EM

_BA

0 / G

IO05

4 / E

M_A

14N

19

EM

_BA

1 / G

IO05

5P

19

EM

_CE

0 / G

IO03

7J1

6

EM

_CE

1 / G

IO03

6G

19

EM

_CLK

/ G

IO03

1E

19

EM

_D00

/ G

IO03

8H

18

EM

_D01

/ G

IO03

9J1

7

EM

_D02

/ G

IO04

0H

19

EM

_D03

/ G

IO04

1J1

8

EM

_D04

/ G

IO04

2L1

5

EM

_D05

/ G

IO04

3J1

9

EM

_D06

/ G

IO04

4K

17

EM

_D07

/ G

IO04

5K

19

EM

_D08

/ G

IO04

6L1

6

EM

_D09

/ G

IO04

7K

18

EM

_D10

/ G

IO04

8L1

9

EM

_D11

/ G

IO04

9L1

7

EM

_D12

/ G

IO05

0L1

8

EM

_D13

/ G

IO05

1M

15

EM

_D14

/ G

IO05

2M

19

EM

_D15

/ G

IO05

3M

18

EM

_OE

/ G

IO03

4F

19

EM

_WA

IT /

GIO

033

G18

EM

_WE

/ G

IO03

5J1

5

R1

010

K

R1

52

10K

R9

63

3R

1210

K

RN

10

RP

AC

K4-

33

12345 6 7 8

RN

17

RP

AC

K4-

331 2 3 4

5678

RN

12

RP

AC

K4-

33

12345 6 7 8

C24

90

.1u

F

R97

10K

R1

81K

RN

15

RP

AC

K4-

331 2 3 4

5678

R1

6N

O-P

OP



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B_V

BU

S

US

B_

ID

US

B_

VB

US

_C

ON

NU

SB

_DM

US

B_

DP

US

B_

DP

US

B_

DM

US

B_

VB

US

US

B_

VB

US

_PW

R

DR

V_

VB

US

US

B_

ID

VC

C_

3V3

VC

C_

3V

3

VC

C_

5V

US

B_I

D_

TO

GG

LE

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D2

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

52

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 U

SB

NO-POP FOR TEST SPECTRUM DIGITAL TEST ONLY

DIFFERENTIAL PAIR

90 OHM DIFFERENTIAL

IMPEDANCE

SHORT AND STRAIGHT AS

POSSIBLE,

MINIMUM NUMBER OF VIAS

USE INTERNAL CONTROL REGISTER

TO FLIP DM/DP POLARITIES

DIFFERENTIAL PAIRS

PLACE THESE RESISTORS CLOSE TO DM355

SPARE JUMPERS

R1

11K

R1

9110

K

R1

90

10K

R1

13

10K

L67

BLM21PG221SN1

R1

94

0

U2

4

TP

S6

109

2R

SA

PG

ND

37

VB

AT

8

EN

AB

LE11

FB

14

OU

T1

1

LBO

12

SW

13

LBI

9

PG

ND

15

PG

ND

26

GN

D1

13

OU

T2

16

OU

T3

15S

W2

4

PWRPAD 17

NC

2S

YN

C10

J10

HE

AD

ER

2

1 2

R1

310

K

R4

40

0

DM

355_

65M

M

U1

8-7

RS

V02

K1

RS

V01

J1

RS

V04

M1

RS

V03

L1

US

B_D

PA

7

US

B_I

DD

5

US

B_R

1C

7

US

B_V

BU

SE

5

US

B_D

MA

6

US

B_D

RV

VB

US

C5

VS

S_U

SB

_RE

FC

8

S

D

G

Q1

IRL

ML6

401

R1

8810

0K+

C2

411

00u

F

R9

2

100C

159

NO

-PO

P

J5m

iniA

B

VB

US

1

D-

2

D+

3

GN

D5

ID4

S1 6

S2 7

S3 8

S4 9

L15

7.3

uH

R1

93N

O-P

OP

R1

9210

K

R2

16

10K

J35

4 H

EA

DE

R

1 2 3 4

C1

60

1u

F

J1

3

HE

AD

ER

4X

2

2 4 6 8

1 3 5 7

+C

627

100

uF

R93

100

+C

24

0

6.8

uF

R2

13N

O-P

OP

J9 HE

AD

ER

21 2

R1

891

0K

1%

R2

270

C6

18

1u

F

Q3

BS

S13

8

Q4

BS

S1

38

R2

12N

O-P

OP

L72

BLM

21P

G22

1SN

1

R2

1410

K

+C

239

10

uF


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

DA

_D

AC

VR

EF

IBIA

S

VS

SA

_DA

C

CP

U_

YO

UT

0C

PU

_Y

OU

T1

CP

U_

YO

UT

7C

PU

_Y

OU

T2

CP

U_

YO

UT

4C

PU

_Y

OU

T3

CP

U_

YO

UT

5C

PU

_Y

OU

T6

CP

U_

CO

UT

2C

PU

_C

OU

T1

CP

U_

CO

UT

0

CP

U_

CO

UT

4

CP

U_

CO

UT

5C

PU

_C

OU

T3

CP

U_

CO

UT

7C

PU

_C

OU

T6

CP

U_

CO

UT

5C

PU

_C

OU

T4

CP

U_

CO

UT

3C

PU

_C

OU

T2

CP

U_

CO

UT

1C

PU

_C

OU

T0

CP

U_

YO

UT

7C

PU

_Y

OU

T6

CP

U_

YO

UT

5C

PU

_Y

OU

T4

CP

U_

YO

UT

3C

PU

_Y

OU

T2

CP

U_

YO

UT

1C

PU

_Y

OU

T0

CP

U_

CO

UT

6

CP

U_

CO

UT

7

VC

C_

1V

8

DSP_GND

DSP_GND

DSP_GND

DSP_GNDVD

IN_

PC

LK

15

VD

IN_

C1

15V

DIN

_C

215

VD

IN_

C3

15

VD

IN_

C0

15

VD

IN_Y

015

VD

IN_Y

115

VD

IN_Y

215

VD

IN_Y

315

VD

IN_Y

415

VD

IN_Y

515

VD

IN_Y

615

VD

IN_Y

715

VD

IN_

WE

N15

VD

IN_

VD

15V

DIN

_H

D15

VD

IN_

C4

15V

DIN

_C

515

VD

IN_

C6

15V

DIN

_C

715

VD

OU

T_E

XT

CLK

18

VD

OU

T_V

CLK

18

VD

OU

T_

FIE

LD

18

VD

OU

T_

LC

D_

OE

18

VD

OU

T_

HS

YN

C18

VD

OU

T_

VS

YN

C1

8

VD

OU

T_C

01

8

VD

OU

T_

Y0

18

VD

OU

T_

Y1

18

VD

OU

T_

Y2

18

VD

OU

T_

Y3

18

VD

OU

T_

Y4

18

VD

OU

T_

Y5

18

VD

OU

T_

Y6

18

VD

OU

T_C

41

8

VD

OU

T_C

51

8V

DO

UT

_C6

18

VD

OU

T_C

71

8

VD

OU

T_C

11

8V

DO

UT

_C2

18

VD

OU

T_C

31

8

VD

OU

T_

Y7

18

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

62

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 V

IDE

O

C1

952

70p

F

R6

71

000

1%

C1

970

.01

uF

L19

3u

H

RN

32

RP

AC

K4

-33

1 2 3 45678

RN

30

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

R6

82

550

1%

C1

962

.2uF

L20

BLM

21B

050

S

R9

133

R1

47

10

70 1

%

C19

42

70pF

DM

355

_65

MM

U1

8-6

CIN

0J3

CIN

1L3

CIN

2J5

CIN

3J4

SP

I2_S

DI/C

IN4

L4

SP

I2_S

EN

/CIN

5M

3

SP

I2_S

DO

/CIN

6K

5

SP

I2_C

LK/C

IN7

N3

PW

M3B

/ C

OU

T0

F4

PW

M3A

/ C

OU

T1

F3

RT

O3/

CO

UT

2E

4R

TO

2/C

OU

T3

E3

RT

O1/

CO

UT

4D

3R

TO

0/C

OU

T5

C1

GIO

80/P

WM

1/C

OU

T6

D2

GIO

81/P

WM

0/C

OU

T7

C2

CA

M_H

DN

5C

AM

_VD

R4

GIO

83/ C

AM

_WE

NR

5G

IO69

/EX

TC

LKG

3

GIO

70 /

FIE

LDH

4

HS

YN

CF

5

IBIA

SF

2

IOU

TE

1

PC

LKT

3

TV

OU

TF

1

VC

LKH

3

VD

DA

18_D

AC

L7

VR

EF

J7

VF

BG

1

VS

SA

_DA

CL8

VS

YN

CG

5Y

IN0

P5

YIN

1P

2

YIN

2P

4

YIN

3R

3

YIN

4P

3

YIN

5M

5

YIN

6M

4

YIN

7L5

YO

UT

0B

1Y

OU

T1

A2

YO

UT

2A

3Y

OU

T3

B2

YO

UT

4B

3Y

OU

T5

B4

YO

UT

6A

4Y

OU

T7

C3

GIO

71/L

CD

_OE

H5

RN

31

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

C1

93

0.1

uF

E6

NF

M21

PC

47

4R

1C

3D

13

2

TP

13

12

C1

98

0.0

1u

F

R9

00

R1

46

0.0

20

J4 RC

A J

AC

K

1

2



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DM

350

_RE

SE

Tn

VC

C_3

V3

CP

U_E

MU

111

CP

U_E

MU

011

CP

U_

TD

O11

CP

U_

RT

CK

11

CP

U_T

CK

11

CP

U_

TD

I11

CP

U_

TM

S11

CP

U_

TR

ST

n11

GIO

1824

GIO

1718

GIO

1618

CP

U_

RE

SE

Tz

22

AR

M_R

ST

n11

DM

350

_RE

SE

Tn

22

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

72

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 J

TA

G,R

ES

ET

,CLO

CK

S

R2

04

NO

-PO

P

C2

372

7 p

F

TP39

1

C2

342

7 p

F

R3

4736

0

R2

05

NO

-PO

P

C2

352

7 p

F

Y2

24M

Hz

TP40

1

TP41

1

DM

355

_65

MM

U1

8-5

GIO

018

/ CLK

OU

T1

D12

GIO

017

/CLK

OU

T2

A11

GIO

016

/ CLK

OU

T3

C11

TC

KE

10

TD

ID

9

TD

OE

9

TM

SD

8

EM

U0

E8

EM

U1

E7

TR

ST

C9

VS

S_M

X1

C10

VS

S_M

X2

P1

MX

I1A

9

MX

I2R

1

MX

O1

B9

MX

O2

T1

RE

SE

TD

11

RT

CK

E11

U2

3

SN

74

LVC

1G

08

1 24

5 3

TP

42

1

C2

380

.1u

F

Y3

27M

Hz

C2

362

7 p

F


A-9

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

1V

3

VC

C_

1V3

CP

U_

CV

DD

CP

U_

VD

D

CP

U_

VD

D_

DD

R

CP

U_

AL

T_V

DD

VC

C_

1V

3

CP

U_

CV

DD

CP

U_

VD

D

CP

U_

VD

D_

DD

R

CP

U_

VD

D_

DD

R

CP

U_

VD

D

CP

U_

AL

T_V

DD

VC

C_

1V

8

VC

C_

1V

8

VC

C_

3V

3

VC

C_

3V

3

VC

C_

1V

3

VC

C_

1V

3

VC

C_

1V

3

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Wed

ne

sda

y, J

an

ua

ry 3

0,

20

088

26

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

5 P

OW

ER

NOT POPULATED

E4

NF

M2

1P

C4

74

R1

C3D 1

3

2

L18

BLM

21B

050S

E5

NF

M2

1P

C4

74

R1

C3D 1

3

2

TP

6 12

C1

540

.1uF

TP

12

12

C1

55

0.0

01u

F

R1

14

0C

11

2N

O-P

OP

C1

210.

01

uF

C1

25

0.0

1u

F

C1

20

0.0

1u

F

C1

474

.7u

F

E2

NF

M2

1P

C4

74

R1

C3

D1

3

2

C1

19

0.0

1uF

C1

151

.0u

F

C1

22

1.0

uF

R3

4N

O-P

OP

TP

11

12

C1

27

2.2

uF

C1

240

.01

uF

R26

0

TP

8

12

E3

NO

-PO

P1

3

2

C1

712

.2u

F

DM

355_

65M

M

U1

8-2

RS

V05

N2

CV

DD

A1

CV

DD

J11

CV

DD

J12

CV

DD

J13

CV

DD

K6

CV

DD

K11

CV

DD

K12

CV

DD

L11

CV

DD

L12

CV

DD

N6

CV

DD

R7

CV

DD

A10

CV

DD

R8

CV

DD

T17

CV

DD

W19

CV

DD

B19

CV

DD

C4

CV

DD

G6

CV

DD

G11

CV

DD

H10

CV

DD

H13

CV

DD

H17

VDDA_PLL1 G12

VDDA_PLL2 H9

VD

DD

13_U

SB

C6

VD

DA

13_U

SB

H7

VD

DA

33_U

SB

J8

VD

D_D

DR

M9

VD

D_D

DR

T14

VD

D_D

DR

P9

VD

D_D

DR

P10

VD

D_D

DR

P11

VD

D_D

DR

P12

VD

D_D

DR

P13

VD

D_D

DR

P14

VD

D_D

DR

R9

VD

D_D

DR

R12

VD

DF

9

VD

DL1

3

VD

DM

10

VD

DM

11

VD

DM

12

VD

DM

13

VD

DN

11

VD

DN

12

VD

DF

10

VD

DF

11

VD

DF

12

VD

DF

13

VD

DF

14

VD

DG

8

VD

DG

14

VD

DK

15

VS

SA

5

VS

SG

2

VS

SG

9

VS

SH

1

VS

SH

2

VS

SH

6

VS

SH

11

VS

SH

14

VS

SJ2

VS

SJ6

VS

SJ1

0

VS

SA

8

VS

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4

VS

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3

VS

SK

9

VS

SK

10

VS

SK

14

VS

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VS

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VS

SL1

0

VS

SL1

4

VS

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6V

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2

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8

VSSA_PLL1 H12VSSA_PLL2 J9

NC

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6

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1

VS

SU

2

VS

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3

VS

SU

4

VS

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9

VS

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SS

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VS

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1V

SS

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1

C1

462

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F

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170

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NO

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560

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F

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30

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0

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70 1.0

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530

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F

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45 1.0

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TP

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80.

020

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88

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050

S

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161.

0u

F

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10.

020

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18

0.0

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20

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0

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260

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TP

5 12

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00.

020

C1

894

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F

C1

570

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50

R3

60

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0

C1

87

2.2

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5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CP

U_

CV

DD

CP

U_

VD

D

CP

U_

VD

D_

DD

R

CP

U_

ALT

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D

Siz

e:

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te:

DW

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sio

n:

Sh

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of

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ge

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:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Wed

ne

sda

y, J

an

ua

ry 3

0,

20

089

26

B

DM

35

5

Eva

lua

tion

Mod

ule

DM

35

0 D

EC

OU

PLI

NG

CA

PA

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OR

S

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68

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480

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490.

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F

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43

0.0

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60

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00

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390.

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134

0.01

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C1

65

0.0

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310

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C1

510

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30

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29

0.0

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FC

13

50

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128

0.0

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F

C1

780.

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FC

173

0.01

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C2

10

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C1

360

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C1

770

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F

C1

82

0.0

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C1

74

0.0

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C1

800

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FC

18

40

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C13

20

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C1

440

.01

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C1

300

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C1

630

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F

C14

10

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C1

520

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C1

40

0.0

1uF

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50

0.0

1uF

C1

85

0.0

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C1

760

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C1

370

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C1

67

0.0

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F

C1

330

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C1

640.

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F

C1

790

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C1

380

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FC

14

20

.01

uF

C1

690

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C1

860

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C1

810.

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F

C1

750

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uF


A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

DQ

3

DD

R_

CL

KP

DD

R_

CL

KN

DD

R_

CA

SD

DR

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AS

DD

R_

CS

DD

R_

WE

DD

R_

DQ

S0

DD

R_

DQ

S1

DD

R_

DQ

M0

DD

R_

DQ

M1

DD

R_

A13

DD

R_

A1

DD

R_

A0

DD

R_

A2

DD

R_

A3

DD

R_

A4

DD

R_

A7

DD

R_

A6

DD

R_

A5

DD

R_

A9

DD

R_

A10

DD

R_

A11

DD

R_

A8

DD

R_

A12

DD

R_

BA

0D

DR

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A1

DD

R_

CK

E

DD

R_

BA

2

DD

R_

DQ

0D

DR

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DD

R_

DQ

2

DD

R_

DQ

4

DD

R_

DQ

8D

DR

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Q9

DD

R_

DQ

7

DD

R_

DQ

5D

DR

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Q6

DD

R_

DQ

14

DD

R_

DQ

10

DD

R_

DQ

13

DD

R_

DQ

12

DD

R_

DQ

11

DD

R_

DQ

15

DD

R_

VD

D

VR

EF

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L

DD

R_V

DD

DD

R_

VD

D

VC

C_

1V

8

DD

R_

DQ

03

DD

R_

DQ

13

DD

R_

DQ

23

DD

R_

DQ

33

DD

R_

DQ

43

DD

R_

DQ

53

DD

R_

DQ

63

DD

R_

DQ

73

DD

R_

DQ

83

DD

R_

DQ

93

DD

R_

DQ

103

DD

R_

DQ

113

DD

R_

DQ

123

DD

R_

DQ

143

DD

R_

DQ

133

DD

R_

DQ

153

DD

R_

CS

3D

DR

_W

E3

DD

R_

DQ

M1

3

DD

R_

CK

E3

DD

R_

CA

S3

DD

R_

RA

S3

DD

R_

CL

KN

3D

DR

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LK

P3

DD

R_

A0

3D

DR

_A

13

DD

R_

A2

3D

DR

_A

33

DD

R_

A4

3D

DR

_A

53

DD

R_

A6

3D

DR

_A

73

DD

R_

A8

3D

DR

_A

93

DD

R_

A1

03

DD

R_

A1

13

DD

R_

A1

23

DD

R_

A1

33

DD

R_

BA

03

DD

R_

BA

13

DD

R_

BA

23

DD

R_

DQ

S0

3D

DR

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QS

13

DD

R_

DQ

M0

3

VR

EF

_ST

L3

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

102

6

B

DM

35

5

Eva

lua

tion

Mod

ule

DD

R2

ME

MO

RY

C9

0.0

1u

F

R6

1K

1%

U2

MT47H64M16BT-37E

N.C

.3A

1

N.C

.4A

2

N.C

.5A

8

N.C

.6A

9

N.C

.7A

A1

N.C

.8A

A2

N.C

.9A

A8

N.C

.10

AA

9

N.C

.2D

2N

.C.1

H2

VD

DD

1

VD

DQ

F1

VD

DH

1

VD

DQ

K1

VD

DL

M1

VD

DV

1

VD

DQ

F7

VD

DQ

K7

VD

DQ

D9

VD

DQ

F9

VD

DQ

H9

VD

DQ

K9

VD

DM

9

VD

DR

9

VD

DQ

F3

VD

DQ

K3

VS

ST

1V

SS

D3

VS

SH

3V

SS

M3

VS

SU

9

VS

SQ

E2

VS

SQ

G2

VS

SQ

J2

VS

SQ

L2

VS

SQ

D7

VS

SQ

E8

VS

SQ

G8

VS

SQ

H7

VS

SQ

J8

VS

SQ

L8

VS

SD

LM

7

DQ

0K

8

DQ

1K

2

DQ

2L7

DQ

3L3

DQ

4L1

DQ

5L9

DQ

6J1

DQ

7J9

DQ

8F

8

DQ

9F

2

DQ

10G

7

DQ

11G

3

DQ

12G

1

DQ

13G

9

DQ

14E

1

DQ

15E

9

A0

R8

A1

R3

A2

R7

A3

T2

A4

T8

A5

T3

A6

T7

A7

U2

A8

U8

A9

U3

A10

R2

A11

U7

A12

V2

NC

/A13

V8

RF

U1

V3

RF

U2

V7

LDQ

SJ7

LDQ

SH

8

UD

QS

E7

UD

QS

D8

CK

M8

CK

N8

RA

SN

7

OD

TN

9

CA

SP

7

CS

P8

UD

ME

3LD

MJ3

VR

EF

M2

WE

N3

BA

0P

2

BA

1P

3

BA

2P

1

CK

EN

2

C1

10.

01u

F

TP2

1 2

C6

0.0

1u

FC

80

.01

uF

C5

2.2

uF

C1

50

.01

uF

C4

4.7

uFR

50.

020

C1

40

.01

uFC

70

.01

uF

R8

0

C1

00

.01

uF

R7

1K

1%

C1

30

.01

uF

C1

20

.01

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ARM_TCK

B_ARM_TCKRET

TI_

EM

U0

AR

M_

TD

I

AR

M_T

DO

AR

M_

TC

K

AR

M_T

RS

Tn

AR

M_T

MS

TI_

PW

R_

DE

CT

ARM_TMS

TI_

TM

S

ARM_TDO

TI_

TC

K_R

ET

ARM_TDI

TI_

TD

I

TI_

TD

O

ARM_TRSTn

TI_

TR

ST

n

AR

M_R

ST

n

TI_

TC

K

AR

M_

TC

KR

ET

TI_

EM

U1

VC

C_3

V3

VC

C_

3V3

VC

C_

3V

3

VC

C_

3V

3

AR

M_

RS

Tn

7CP

U_

TR

ST

n7

CP

U_

TM

S7

CP

U_

TD

I7

CP

U_

TD

O7

CP

U_

RT

CK

7C

PU

_T

CK

7

CP

U_

EM

U0

7

CP

U_

EM

U1

7

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

112

6

B

DM

35

5

Eva

lua

tion

Mod

ule

JTA

G I

NT

ER

FA

CE

KEY

14 PIN TI JTAG INTERFACE

20 PIN ARM JTAG INTERFACEARM_DEBUG_REQ

ARM_DEBUG_ACK

SWITCH CONTROLS JTAG TAP:

EMU1 EMU0 FUNCTION

0 0

0 1

1 0

1 1

ICE PICK MODE *

ARM MODE

RESERVED

RESERVED

* DEFAULT

R2

533

R1

05

2.2

K

R2

333

R1

111

0k

R3

92

.2K

R1

02

10K

R3

833

J8

SA

MT

EC

-TS

M-1

10-D

V

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

R2

433

R2

233

J6

TS

W-1

07-1

4-G

-D-0

06

TR

ST

2

GN

D4

nc6

GN

D8

GN

D10

GN

D12

EM

U1

14

TM

S1

TD

I3

PD

5

TD

O7

TC

KR

ET

9

TC

K11

EM

U0

13

R1

03

0

SW

1

CA

SD

20T

B

1 2 3

4 5 6

R9

810

K

R2

033

R1

042

.2K

R2

933

R1

010

R3

733


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_D0

EM

_D1

EM

_D2

EM

_D3

EM

_D

[15

..0

]

EM

_D4

EM

_D5

EM

_D6

EM

_D7

NA

ND

_A

LE

NA

ND

_C

LE

EM

_WE

NA

ND

_R

B

NA

ND

CE

NA

ND

CE

2

NA

ND

_R

E

VC

C_3

V3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

VC

C_3

V3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V3

VC

C_

3V

3

EM

_D

[15

..0

]4

,20

EM

_A1

4E

M_W

E4

,20

EM

_A2

4

EM

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E0

4

EM

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IT4

EM

_OE

4,2

0

EM

_A

124

GIO

62

4G

IO6

14

GIO

64

4

GIO

60

4G

IO5

94

GIO

58

4G

IO5

74

GIO

54

4

GIO

67

4

GIO

63

4G

IO6

54

GIO

31

4

GIO

032

4G

IO5

64

SP

I0_

SD

I2SP

I0_

SD

EN

A0

2

SP

I0_

SC

LK2

SP

I0_

SD

O2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D2

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

122

6

B

DM

35

5

Eva

lua

tion

Mod

ule

NA

ND

FLA

SH

, S

PI

EE

PR

OM

, E

MIF

I/O

DC

R22

60

R1

070

C2

470

.1u

F

C3

66

0.1

uF

R1

621

0 K

R21

10K

TP

101

C1

72

.2u

F

TP

141

A

BC

U5

1G

AU

97

TY

PE

5

12

4

5

36

C24

80

.1u

F

R1

611

0 K

DC

7

SM

T R

EC

PT

AC

LE 1

0X2

2 4 6 8 10 12 14 16 18 20

1 3 5 7 9 11 13 15 17 19

C1

80

.1u

F

R1

59

0

R9

10

K

R10

60

XU

3

SO

CK

ET

48

C1

60

.1u

F

R22

40

U3

MT2

9F16

G08

FAA

WC

:A

I/O7

44

I/O6

43

I/O5

42

I/O4

41

VC

C.1

12

I/O3

32

I/O2

31

I/O1

30

I/O0

29

VS

S.2

36

RE

8

CE

9

VC

C.2

37D

NU

/VS

S38

CLE

16

ALE

17

WE

18

WP

19

NC

.11

NC

.22

NC

.33

NC

.44

NC

.55

NC

.11

11

VS

S.1

13

R/B

2n6

R/B

n7

CE

210

NC

.14

14

NC

.15

15

NC

.20

20

NC

.21

21

NC

.22

22

NC

.23

23

NC

.24

24D

NU

.25

25D

NU

.26

26N

C.2

727

NC

.28

28

NC

.33

33N

C.3

434

NC

.35

35

NC

.39

39N

C.4

040

NC

.45

45N

C.4

646

NC

.47

47D

NU

.48

48

R30

9

10K

R1

58

0

AB C

U4

1G

AU

97

TY

PE

7

1

2

4

53

6

U6

5

AT

2564

0A

N-1

0SU

-2.7

CS

1

SI

5G

ND

4

VC

C8

HO

LD7

WP

3S

O2

SC

K6

R3

1010

K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

UA

RT

0_T

XD

UA

RT

0_R

XD

VC

C_

3V3

VC

C_

3V

3V

CC

_3

V3

GN

D_E

_RS2

32G

ND

_E_R

S232

GN

D_E

_RS2

32

GN

D_E

_RS2

32

GN

D_E

_RS2

32

GN

D_E

_RS2

32

GN

D_E

_RS2

32

UA

RT

0_T

XD

2

UA

RT

0_R

XD

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

813

26

B

DM

355

E

valu

atio

n M

odul

e

RS

232

SILKSCREEN:

UART

R1

6310

K+

C2

001

0uF

R1

64

10K

P4

DB

9-M

AL

E5 9 4 8 3 7 2 6 1

AB

C19

91

uF

C2

071

uF

C2

02

10

pF

C2

061

uF

L58

BL

M2

1PG

221S

N1D

C2

05

1uF

C20

31

0pF

C2

04

10

pF

L57

BL

M2

1PG

221S

N1D

U3

4

MA

X32

21C

PW

RG

4

T_I

N11

R_O

UT

9

VC

C15

GN

D14

V+

3

V-

7

C1+

2

C1-

4

C2+

5

C2-

6

FO

RC

EO

N12

FO

RC

EO

FF

16

R_I

N8

T_O

UT

13

EN

1IN

VA

LID

10

C20

11

0pF

C2

08

1uF

L60

1u

H

L61

1u

H

R1

65

10K


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SD

0_D

AT

A2

SD

0_

CLK

SD

0_

CM

D

SD

0_D

AT

A1

SD

1_D

AT

A2

SD

1_D

AT

A3

SD

1_

CM

D

SD

0_D

AT

A0

SD

0_D

AT

A3

SD

1_

CL

K

SD

1_D

AT

A0

SD

1_D

AT

A1

VC

C_

3V

3V

CC

_3V

3

VC

C_

3V

3V

CC

_3

V3

VC

C_

3V

3

VC

C_

3V

3V

CC

_3V

3

VC

C_

3V

3

VC

C_3

V3

VC

C_

3V

3

VC

C_

3V

3

VC

C_3

V3

VC

C_

3V3

SD

/MM

C0

.IN

S22

SD

/MM

C0

.WP

22

SD

/MM

C1

.IN

S22

SD

/MM

C1

.WP

22

SD

1_

CM

D2

SD

1_D

AT

A2

2

SD

1_D

AT

A0

2

SD

1_

CL

K2

SD

1_D

AT

A3

2

SD

1_D

AT

A1

2

SD

0_

CM

D2

SD

0_D

AT

A2

2

SD

0_D

AT

A0

2

SD

0_

CL

K2

SD

0_D

AT

A3

2

SD

0_D

AT

A1

2

AT

A_

CE

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2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

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of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

814

26

B

DM

355

E

valu

atio

n M

odul

e

SD

/MM

C C

AR

D I

NT

ER

FA

CE

CE-ATA DRIVE CONNECTOR

OPTIONAL ESD CLAMPING

OPTIONAL ESD CLAMPING

NOT POPULATED

NOT POPULATED

J12

0.5

MM

CO

NN

1 2 3 4 5 6 7 8 9 10 11 12

R1

32

51K

+C

100

10

uF

R1

2251

KR

123

51K

R1

245

1K

R1

34N

O-P

OP

R1

08

51K

R1

36

0

R1

30N

O-P

OP

R1

5451

K

R1

25N

O-P

OP

J28

MM

C/S

D_

CA

RD

DA

T3

1

CM

D2

VS

S1

3

VD

D4

CLK

5

VS

S2

6

DA

T0

7

DA

T1

8

DA

T2

9W

P10

CO

M11

INS

12

MH1 13

MH2 14

MH3 15

MH4 16

MH5 17

MH6 18

R1

20

51K

R1

21

NO

-PO

P

R1

18N

O-P

OP

U2

6

TP

DE

6000

1RS

E

IO1

1

IO2

2

IO3

3

IO4

6

IO5

7

IO6

8

VCC10 GND 5

NC

.44

NC

.99

R1

5351

K

R2

15N

O-P

OP

R1

285

1KR

133

51K

R1

19

NO

-PO

P

R1

3151

K

R1

000

C1

03

.1u

F

R1

175

1K

C2

8N

O-P

OP

R1

2651

K

R9

90

C1

01

.1u

F

U2

5

TP

DE

6000

1RS

E

IO1

1

IO2

2

IO3

3

IO4

6

IO5

7

IO6

8

VCC10 GND 5

NC

.44

NC

.99

R1

37

0

R1

0951

K

+C

10

2

10u

FR

129

51K

C2

9N

O-P

OP

R1

275

1K

J27

MM

C/S

D_

CA

RD

DA

T3

1

CM

D2

VS

S1

3

VD

D4

CLK

5

VS

S2

6

DA

T0

7

DA

T1

8

DA

T2

9W

P10

CO

M11

INS

12

MH1 13

MH2 14

MH3 15

MH4 16

MH5 17

MH6 18



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TV

P5

146_

Y4

TV

P5

146_

Y3

TV

P5

146_

Y2

TV

P5

146_

Y1

TV

P5

146_

Y0

TV

P5

146_

Y6

TV

P5

146_

Y7

TV

P5

146_

Y5

TV

P51

46_C

4T

VP

5146

_C3

TV

P51

46_C

2T

VP

5146

_C1

TV

P51

46_C

0

TV

P51

46_C

6T

VP

5146

_C7

TV

P51

46_C

5

DE

CO

DE

R_

IMA

GE

R DE

CO

DE

R_

IMA

GE

R

DE

CO

DE

R_

IMA

GE

R

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

TV

P5

146_

C6

17

TV

P5

146_

C2

17

TV

P5

146_

C3

17

TV

P51

46_

Y6

17

TV

P5

146_

C0

17

TV

P5

146_

C1

17

TV

P5

146_

C4

17

TV

P5

146_

C5

17

TV

P51

46_

Y7

17

TV

P51

46_

Y5

17

TV

P51

46_

Y3

17T

VP

514

6_Y

417

TV

P51

46_

Y2

17

TV

P51

46_

Y0

17T

VP

514

6_Y

117

TV

P5

146_

C7

17

VD

IN_

C0

6

VD

IN_Y

06

VD

IN_Y

16

VD

IN_Y

26

VD

IN_Y

36

VD

IN_Y

46

VD

IN_Y

56

VD

IN_Y

66

VD

IN_Y

76

VD

IN_

C4

6V

DIN

_C

56

VD

IN_

C6

6V

DIN

_C

76

VD

IN_

PC

LK

6

VD

IN_W

EN

6

VD

IN_

VD

6V

DIN

_HD

6

VD

IN_

C1

6V

DIN

_C

26

VD

IN_

C3

6

TV

P5

14

6H

SY

NC

17T

VP

51

46V

SY

NC

17

TV

P51

46P

CLK

17

DE

CO

DE

R_

IMA

GE

R22

IMA

GE

R_

PX

CLK

16IMA

GE

R_

LIN

E_V

AL

ID16IM

AG

ER

_F

RA

ME

_VA

LID

16IM

AG

ER

_D0

16

IMA

GE

R_D

216

IMA

GE

R_D

116

IMA

GE

R_D

316

IMA

GE

R_

D8

16IM

AG

ER

_D

916

IMA

GE

R_

D1

116

IMA

GE

R_

D1

016

IMA

GE

R_D

616

IMA

GE

R_D

516

IMA

GE

R_D

716

IMA

GE

R_D

416

IMA

GE

R_

GB

L_S

HU

TT

ER

16IM

AG

ER

_TR

G16

I2C

_D

AT

A_

541

617

I2C

_S

CLK

_54

16

17

I2C

_D

AT

A_

IMG

16I2

C_

SC

LK

_IM

G16

I2C

_D

AT

A2

,18

,19

,22

,24

I2C

_S

CL

K2

,18

,19

,22

,24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

152

6

B

DM

35

5

Eva

lua

tion

Mod

ule

VID

EO

IN

PU

T M

UL

TIP

LE

XE

R

U1

SN

74C

BT

LV32

57

1A2

1B3

2A5

2B6

3A11

3B10

4A14

4B13

GN

D8

Vcc

16

1Y4

OE

15

2Y7

3Y9

4Y12

A/B

1

R2

17

360

R3

72

47K

R4

10K

R3

7347

K

U5

3

SN

74C

BT

LV16

292

DG

GR

NC

.14

56

GND.2 19

1A2

11A

25

1B1

54

1B2

53

GND.1 8VCC.117

GND.3 38GND.4 49

NC

.13

55

2A4

3A6

4A9

5A11

6A13

7A15

8A18

9A21

10A

23

12A

27

NC

.13

NC

.25

NC

.37

NC

.410

NC

.512

NC

.614

NC

.716

NC

.820

S1

2B1

52

3B1

50

9B1

36

4B1

47

5B1

45

6B1

43

7B1

41

8B1

39

10B

134

2B2

51

3B2

48

4B2

46

5B2

44

6B2

42

7B2

40

8B2

37

11B

231

12B

229

NC

.922

NC

.10

24

NC

.11

26

NC

.12

28

11B

132

12B

130

9B2

35

10B

233

C11

0

0.1

uF

C1

58

0.1

uF

R2

18

360

U5

4

SN

74C

BT

LV16

292

DG

GR

NC

.14

56

GND.2 19

1A2

11A

25

1B1

54

1B2

53

GND.1 8VCC.117

GND.3 38GND.4 49

NC

.13

55

2A4

3A6

4A9

5A11

6A13

7A15

8A18

9A21

10A

23

12A

27

NC

.13

NC

.25

NC

.37

NC

.410

NC

.512

NC

.614

NC

.716

NC

.820

S1

2B1

52

3B1

50

9B1

36

4B1

47

5B1

45

6B1

43

7B1

41

8B1

39

10B

134

2B2

51

3B2

48

4B2

46

5B2

44

6B2

42

7B2

40

8B2

37

11B

231

12B

229

NC

.922

NC

.10

24

NC

.11

26

NC

.12

28

11B

132

12B

130

9B2

35

10B

233

R3

744

7KR

375

47K

C10

8

0.1

uF


A-17

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

IMA

GE

R_V

BU

SIM

AG

ER

_V

BU

SV

CC

_5

V

IMA

GE

R_P

XC

LK1

5

IMA

GE

R_

LIN

E_

VA

LID

15 IMA

GE

R_

FR

AM

E_

VA

LID

15IM

AG

ER

_RE

SE

T22

IMA

GE

R_

GB

L_S

HU

TT

ER

15IM

AG

ER

_TR

G15

IMA

GE

R_D

215

IMA

GE

R_D

415

IMA

GE

R_D

615

IMA

GE

R_D

815

IMA

GE

R_D

1015

IMA

GE

R_D

015

IMA

GE

R_D

315

IMA

GE

R_D

515

IMA

GE

R_D

715

IMA

GE

R_D

915

IMA

GE

R_D

115

IMA

GE

R_

D1

115

I2C

_D

AT

A_I

MG

15

I2C

_S

CL

K_

IMG

15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

816

26

B

DM

355

E

valu

atio

n M

odul

e

IMA

GE

R I

NT

ER

FA

CE

L69

BLM

41P

750S

PT

C1

90

0.0

1u

F

C1

91

0.1

uF

C1

92

10

uF

J30

HE

AD

ER

13X

2

2 4 6 8 10 12 14 16 18 20 22 24 26

1 3 5 7 9 11 13 15 17 19 21 23 25

R1

550

R1

560

R1

570

J31

HE

AD

ER

13

1 2 3 4 5 6 7 8 9 10 11 12 13



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TV

P5

146_

Y4

TV

P5

146_

Y3

TV

P5

146_

Y1

TV

P5

146_

Y0

TV

P5

146_

Y6

TV

P5

146_

Y7

TV

P5

146_

Y5

TV

P5

146_

Y2

TV

P51

46_

C4

TV

P51

46_

C3

TV

P51

46_

C2

TV

P51

46_

C1

TV

P51

46_

C0

TV

P51

46_

C6

TV

P51

46_

C7

TV

P51

46_

C5

LU

MA

3.3

VA

_D

DE

C3

.3V

D_

DD

EC

1.8

VD

_D

DE

C

3.3

VD

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VD

_D

DE

C

1.8

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C1

.8V

D_

DD

EC

1.8

VA

_D

DE

C

3.3

VD

_D

DE

C

DEC_GND DEC_GND

DEC_GND

DEC_GNDDEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GNDDEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

DEC_GND

VC

C_

3V3

VC

C_

3V3

VC

C_

1V

8

VC

C_

1V

8

3.3

VD

_D

DE

C

DEC_GND

TV

P51

46_R

ES

ET

n22

TV

P51

46_

Y7

15

TV

P5

14

6V

SY

NC

15

TV

P5

146P

CLK

15

TV

P51

46

HS

YN

C15

TV

P51

46_

Y6

15T

VP

514

6_Y

515

TV

P51

46_

Y3

15T

VP

514

6_Y

415

TV

P51

46_

Y2

15

TV

P51

46_

Y0

15T

VP

514

6_Y

115

TV

P51

46_C

715

TV

P51

46_C

615

TV

P51

46_C

215

TV

P51

46_C

315

TV

P51

46_C

015

TV

P51

46_C

115

TV

P51

46_C

415

TV

P51

46_C

515

I2C

_D

AT

A_5

416

15

I2C

_S

CL

K_5

416

15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

day,

Ma

rch

14

, 2

00

817

26

B

DM

355

E

valu

atio

n M

odu

le

TV

P5

146

VID

EO

DE

CO

DE

R

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

C6

3

0.1

uF

R7

72

2

C8

9

33

pF

C2

21

33

0pF

C8

73

30

pF

C7

2

0.1

uF

C2

19

33

0pF

R7

2

4.7

K

C9

1

0.1

uF

R1

8675

C7

7

0.1

uF

L63

2.7

uH

C7

5

0.1

uF

R8

10

C2

206

80p

F

C6

2

0.1

uF

R8

0

75

R1

87

75

L10

BLM

41P

750

SP

T1

2

C8

8

33p

F

L66

2.7

uH

C2

25

68

0pF

Y1 14

.318

18m

hz

R8

6

NO

PO

P

C2

22

.1u

F

C6

1

0.1

uF

C8

2

0.1

uF

C6

0

0.1

uF

C7

6

0.1

uF

R7

3

2K

C6

7

0.1

uF

C8

53

30pF

U9

TV

P51

46

VI_

3_B

17

VI_

3_A

16

VI_

2_B

8

VI_

2_C

9

Y8

44Y

943

Y7

45

TH

ER

MA

L81

CH3_A18GND 15

CH4_A18GND 24

CH1_A18GND 79

DGND4 56

CH1_A33GND 3

CH3_A33GND 19CH2_A33GND 6

VI_

3_C

18

VI_

4_A

23

Y2

52Y

351

Y6

46

CH4_A33GND 22

DGND2 32

DGND3 42

IOGND1 39

IOGND2 49

IOGND3 62

PLL_A18GND 77

DGND1 27

DGND5 68

A18GND_REF 13AGND 26

CH2_A18VDD11

CH3_A18VDD14

CH4_A18VDD25

CH1_A18VDD78

CH1_A33VDD4

CH2_A33VDD5

CH3_A33VDD20

CH4_A33VDD21

A18VDD_REF12

DVDD131

DVDD241

DVDD355

DVDD467

IOVDD138

IOVDD248

IOVDD361

PLL_A18VDD76

VI_

2_A

7

VI_

1_C

2

VI_

1_B

1

VI_

1_A

80

SC

L28

SD

A29

Y5

47

Y4

50

Y1

53

Y0

54

C9

57

C8

58

C7

59

C6

60

C5

63

C4

64

C3

65

C2

66

C1

69

C0

70

XT

AL1

74

XT

AL2

75

DA

TA

CLK

40

RE

SE

TB

34

PW

RD

WN

33

INT

RE

Q30

FS

S/G

PIO

35

GLC

O/1

2CA

37

HS

/CS

/GP

IO72

VS

/VB

LK/G

PIO

73

FID

/GP

IO71

AV

ID/G

PIO

36

CH2_A18GND 10

C8

66

80

pF

C7

0

0.1

uF

R79 100

K

R7

1

4.7

K

R7

8

2.2

K

C8

1

0.1

uF

C6

6

.1u

F

R7

0

2K

R7

522

C6

8

0.1

uF

L65

2.7

uH

C7

8

0.1

uF

RN

20

RP

AC

K8-

33

1 2 3 4 5 6 7 8910111213141516

C2

23

33

0pF

J2 RC

A J

AC

K

1

2

C7

3

0.1

uF

C7

1

0.1

uF

C84

.1uF

L13

BLM

41P

750S

PT

12

R6

9

NO

PO

P

R7

622

C6

4

0.1

uF

C2

24

33

0pF

R7

4

NO

PO

PL

92

.7u

H

C6

9

0.1

uF

RN

5R

PA

CK

8-3

31 2 3 4 5 6 7 8

910111213141516

L82

.7u

H

L64

2.7

uH

J11

7491

81-1

34 2

1

56

C7

4

0.1

uF

L11

BLM

41P

750S

PT

12

C2

18

.1u

F

C8

3

.1u

F

C6

5

0.1

uF

C9

00

.1u

F

L12

BLM

41P

750

SP

T1

2


A-19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

5VV

CC

_5V

VC

C_

1V

8V

CC

_1

V8

VC

C_

3V

3V

CC

_3

V3

VC

C_

3V

3

DM

350

_G

IO6

2VD

OU

T_

LCD

_O

E6

VD

OU

T_

FIE

LD

6G

IO17

7D

M35

0_G

IO7

2

DC

5_

RE

SE

Tn

22

VD

OU

T_C

06

VD

OU

T_C

16

VD

OU

T_C

26

VD

OU

T_C

36

VD

OU

T_C

46

VD

OU

T_C

56

VD

OU

T_C

66

VD

OU

T_C

76

VD

OU

T_

Y0

6V

DO

UT

_Y

26

VD

OU

T_

Y4

6V

DO

UT

_Y

66

VD

OU

T_

Y1

6V

DO

UT

_Y

36

VD

OU

T_

Y5

6V

DO

UT

_Y

76

VD

OU

T_E

XT

CLK

6V

DO

UT

_H

SY

NC

6

VD

OU

T_

VS

YN

C6

VD

OU

T_

VC

LK6

I2C

_D

AT

A2

,15

,19

,22

,24

I2C

_S

CLK

2,1

5,1

9,2

2,2

4

GIO

167 S

ize:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

182

6

B

DM

35

5

Eva

lua

tion

Mod

ule

TH

S8

20

0 D

AU

GH

TE

R C

AR

D I

NT

ER

FA

CE

VIDEO OUTPUT CONNECTOR

R1

74

0

R8

810

K

R1

76

0

R1

1210

K

R1

75

0

R1

77

0

DC

6

SM

T R

EC

EP

TA

CLE

5X

2

2 4 6 8 10

1 3 5 7 9

DC

5

SM

T R

EC

EP

TA

CLE

25X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49



VC

C_3

V3

VC

C_1

V8

VC

C_

3V

3

VC

C_3

V3

VC

C_

3V3

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

ICA

IC33

_R

ES

ET

n22

McB

SP

_FS

X1

2McB

SP

_CLK

X1

2

McB

SP

_D

X1

2McB

SP

_CL

KR

12

McB

SP

_C

LK

S1

2

McB

SP

_F

SR

12

McB

SP

_D

R1

2

I2C

_D

AT

A2

,15

,18

,22

,24

I2C

_SC

LK

2,1

5,1

8,2

2,2

4S

ize:

Da

te:

DW

G N

OR

ev

isio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

509

902

-000

1

Fri

day

, M

arch

14

, 2

008

1926

B

DM

35

5

Eva

luat

ion

Mo

dul

e

AIC

33

AU

DIO

IN

TE

RF

AC

E

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

R5

210

K

C5

1.1

uF

R4

60

P1

Mic

In

3 4 2 1

R5

720

KR5

12

0K

C5

2

.1u

F

C3

67

.1u

F

P3

Lin

e O

ut

3421

C4

7.1

uF

C4

822

0pF

U6

6 27M

hz

VC

C4

OU

T3

GN

D2

EN

1

R4

747

K

C38

.1u

F

TP

31

U8

TV

L3

20A

IC33

IZQ

E

HP

LOU

TD

1

HP

LCO

ME

1

LIN

E1R

+B

7

LIN

E1R

-B

6

LIN

E2L

+A

4

LIN

E2L

-B

5

MIC

BIA

SA

2

WC

LKF

9

DO

UT

F8

MP

F2

A8

MC

LKG

8

SE

LEC

TE

8

SD

AD

8

RIG

HT

_LO

+J6

DR

VS

S.1

E2

DR

VS

S.2

F2

GP

IO2

J8

LEF

T_L

O+

J4

LEF

T_L

O-

J5

MO

NO

_LO

-J3

DIN

E9

MIC

3RA

1

LIN

E2R

+B

4

LIN

E2R

-A

3

HP

RC

OM

F1

HP

RO

UT

G1

MIC

3LB

3

DR

VD

D.2

H1

AV

DD

_AD

CB

1

AV

SS

_AD

C.1

C2

AV

DD

_DA

CJ1

AV

SS

_DA

C.1

G2

RE

SE

TH

8

MF

P0

B8

MF

P1

B9

DV

DD

H9

DV

SS

D9

IOV

DD

C9

MIC

DE

TB

2

RIG

HT

_LO

-J7

SC

LC

8

MO

NO

_LO

+J2

GP

IO1

J9

LIN

E1L

-A

5LI

NE

1L+

A6

BC

LKG

9

MF

P3

A9

AV

SS

_AD

C.2

D2

AV

SS

_DA

C.2

H2

DR

VD

D.1

C1

R6

510

+

C5

81

0u

F,6

.3V

+

C3

21

0uF

TP

41

C5

0

.1u

FR

45

0

R4

910

K

R5

81

0

R5

4N

O-P

OP

C3

9.1

uF

C33

.1uF R

40

5.6

K

R6

01

0

C3

6.1

uF

L5B

LM2

1PG

221S

N1D

R4

433

0

C41

.1uF

R5

3N

O-P

OP

L1

BLM

21P

G22

1S

N1D

C3

5.1

uF

C4

3.1

uF

+

C3

71

0uF

R6

310

K

R5

61

0

+

C56

33

uF

,6.3

V

P6

Lin

e I

n 3 4 2 1

R5

91

0

C5

7.1

uF

C4

422

0pF

L3

BLM

21P

G2

21S

N1D

C4

2

.1u

F

R1

60

22

+

C5

91

0u

F,6

.3V

C3

4.1

uF

C4

0.1

uF

C4

5

.1u

F

C4

9.1

uF

R4

35

.6K

R6

12

0K

P2

He

ad

pho

ne O

ut

3421

+

C54

33

uF

,6.3

V

C5

52

20p

F

C46

1u

F

R5

510

K

R6

410

R6

620

K

L2B

LM21

PG

221S

N1D

L6B

LM2

1PG

221S

N1D

R4

83

30

L7B

LM2

1PG

221S

N1D

L4B

LM2

1PG

221S

N1D

R4

15

.6K

R5

02

0K

R4

25

.6K

C5

3.1

uF

R62

10


A-21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EN

ET

_D8

EN

ET

_D7

EN

ET

_D6

EN

ET

_D5

EN

ET

_D4

EN

ET

_D3

EN

ET

_D1

EN

ET

_D0

EN

ET

_D

15E

NE

T_

D14

EN

ET

_D2

EN

ET

_D9

EN

ET

_D

10

EN

ET

_D

12E

NE

T_

D13

EN

ET

_D

11

EM

_D9

EM

_D

10E

M_

D11

EM

_D0

EM

_D

12E

M_

D13

EM

_D

14E

M_

D15

EM

_D1

EM

_D2

EM

_D3

EM

_D4

EM

_D5

EM

_D6

EM

_D7

EM

_D8

EM

_D

[15

..0

]

EM

_BA

1

ENET-AGND

ENET-AGND

ENET-AGND

EN

ET

_2V

5

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

VC

C_

3V

3

EM

_D

[15

..0

]4

,12

EN

ET

_LE

D1

21E

NE

T_

LED

221

EN

ET

_RX

I-2

1E

NE

T_R

XI+

21

EN

ET

_TX

O-

21E

NE

T_T

XO

+21

EN

ET

_IN

T2

EM

_BA

14

EN

ET

_CE

4

EM

_WE

4,1

2E

M_O

E4

,12

EN

ET

_R

ES

ET

z2

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

820

26

B

DM

355

E

valu

atio

n M

odul

e

Eth

ern

et

Inte

rfa

ceENET_2V5 IS DM9000A

INTERNALLY GENERATED

POWER SUPPLY

DIFFERENTIAL PAIRS

C2

4.1

uF

Y4

25M

Hz

RN

25

RP

AC

K8-

33

1 2 3 4 5 6 7 8910111213141516

R1

974

.7K

C2

28.1

uF

C2

5.1

uF

R2

01

10K

C2

302

2 p

F

R2

0310

K

R1

99

NO

-PO

P

C2

27

.1u

FR1

95

NO

-PO

P

U2

2D

M90

00A

-QF

P48

IOR

#35

IOW

#36

CSn 37

SD

512

DVDD 42

SD 46

TEST 41

DGND15

X2 43

X1 44

SD

710

BGGND 48

BG

RE

S1

RX

I+3

RX

I-4

RX_GND 47

RX

GN

D5

TX

O+

7T

XO

-8

TX

_VD

D_2

V5

9

RX

VD

D_2

V5

2LED1 39

SD018

DGND 45

SD413SD314

VDD23

EEDI019EECK20EECS21

DV

DD

30

DG

ND

33

SD117

LED2 38

SD216

PW_RST# 40

TX

GN

D6

SD1522

SD1424

SD

1325

SD

1226

SD

1127

SD

1028

SD

929

SD

831

SD

611

CM

D32

INT

34

C2

332

2 p

F

R1

981K

C2

31.1

uF

R2

026

.8K

1%

R2

00N

O-P

OP

+C

229

10

0uF

R1

96N

O-P

OP

C2

26.1

uF

C2

32

.1u

F

U2

1

AT

93C

46-

10T

I-2.

7

CS

1

SK

2

DI

3

DO

4G

ND

5O

RG

6D

C7

VC

C8

L68

BLM

41P

G75

0SN

1L

RN

24

RP

AC

K8-

33

1 2 3 4 5 6 7 8910111213141516



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EP

HY

_L

ED

2

EP

HY

_L

ED

1

GN

D_E

_EN

ET

ENET-AGND

EN

ET

_2V

5

ENET-AGND

ENET-AGND

ENET-AGND

ENET-AGND

VC

C_

3V

3

GN

D_E

_EN

ET

EN

ET

_RX

I-20

EN

ET

_R

XI+

20

EN

ET

_LE

D1

20

EN

ET

_LE

D2

20

EN

ET

_TX

O-

20

EN

ET

_TX

O+

20

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

212

6

B

DM

35

5

Eva

lua

tion

Mod

ule

ET

HE

RN

ET

OU

TP

UT

C2

14

0.1

uF

R1

834

9.9

R1

8136

0

P5

RJ4

5 H

AL

O H

FJ1

1-2

450

E-L

21

TX

D-C

T4

NC

17

GN

D8

TX

D+

1

TX

D-

2

RX

D+

3

RX

D-

6R

XD

-CT

5

S0 14S1 13

LED

2-12

LED

2+11

LED

1-10

LED

1+9

C2

13

0.1

uF

R1

80

360

R1

854

9.9

R1

824

9.9

C2

17

0.1

uF

C2

15

10

00

pF

2kV

R1

844

9.9

C2

16

0.1

uF


A-23

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

430

_TM

S

MS

P43

0_3V

3

430_

TD

O43

0_T

DI

430_

TC

K4

30_T

DI

430_

TD

O

430_

TM

S43

0_T

CK

MS

P43

0_3V

3

MS

P43

0_R

ES

ET

z

MS

P43

0_R

ES

ET

z

ALT

_3V

3

VC

C_

3V

3

MS

P43

0_3V

3

MS

P43

0_3V

3

MS

P43

0_3

V3

VC

C_

3V3

VC

C_

1V8

VC

C_

1V3

MSP_AGND

MSP_AGND

MSP_AGND

MSP_AGND

MSP_AGND

MS

P4

30_

3V3

MS

P4

30_A

VC

C

MS

P43

0_A

VC

C

MSP_AGND

MSP_AGND

MSP_AGND

ALT

_3V

3

I2C

_D

AT

A2

,15

,18

,19,

24I2

C_S

CL

K2

,15

,18

,19,

24

LE

D0

23L

ED

123

LE

D2

23L

ED

323

LE

D4

23L

ED

523

LE

D6

23L

ED

723

ALT

_MS

P43

0_R

ES

ET

z25

EN

ET

_R

ES

ET

z20

MS

P4

30_

1V3

_EN

AB

LE25

MS

P4

30_

1V8

_EN

AB

LE26

MS

P4

30_

3V3

_EN

AB

LE26

DE

EP

SLP

_E

N2

SW

_D

IP0

23S

W_

DIP

123

SW

_D

IP2

23S

W_

DIP

323

SY

S_

RE

SE

Tz

24

PB

_RE

SE

Tn

23

SD

/MM

C1

.IN

S1

4S

D/M

MC

1.W

P1

4S

D/M

MC

0.I

NS

14

SD

/MM

C0

.WP

14

MS

P4

30_

INT

2

TV

P51

46_R

ES

ET

n17

DC

5_R

ES

ET

n1

8A

IC3

3_R

ES

ET

n19

NT

SC

_P

AL

23

PB

_S

W12

23P

B_

SW

1123

PB

_S

W10

23

PB

_S

W13

23P

B_

SW

1423

DE

CO

DE

R_I

MA

GE

R15

IMA

GE

R_

RE

SE

T16

CP

U_R

ES

ET

z7

DM

350

_RE

SE

Tn

7

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

C

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

222

6

B

DM

35

5

Eva

lua

tion

Mod

ule

MS

P4

30

& I

R I

NT

ER

FA

CE

RN

29

RP

AC

K8

-10

K

123456789 10 11 12 13 14 15 16

R2

091K

C9

7

0.1

uF

D2

BA

T1

7

+C

94

10

uF

6.3

V

D1

BA

T17

R2

0810

0

U1

5

MS

P43

0F1

55IP

W

DV

CC

.11

P2.0/ACLK 20

P2.1/TAINCLK 21X

IN8

XO

UT

9

DVSS63

P1.

0/T

AC

LK12

P2.2/CAOUT/TA0 22

RST/NMI58

P1.

1/T

A0

13

P1.

2/T

A1

14

P1.

3/T

A2

15

TCK57

TDI/TCLK55

TDO/TDI54

P2.3/CA0/TA1 23

P2.4/CA1/TA2 24

P2.5/ROSC 25

P3.0/STE0 28

P3.1/SIMO0/SDA 29

P3.2/SOMI0 30

P3.3/UCLK0/SCL 31

P3.4/UTXD0 32

P3.

5/U

RX

D0

33P

3.6

34P

3.7

35

P6.

3/A

32

P6.

4/A

43

P6.

5/A

54

P6.

6/A

6/D

AC

05

P6.

7/A

7/D

AC

1/S

VS

IN6

P6.2/A261V

RE

F+

7

AVCC64

AVSS62

P6.1/A160

P6.0/A059

TMS56

P1.

4/S

MC

LK16

VE

RE

F+

10

VR

EF

-/V

ER

EF

-11

XT2IN53

XT2OUT52

P5.5/SMCLK49

P5.7/TBOUTH.SVSOUT51

P5.6/ACLK50

P1.5/TA0 17

P1.6/TA1 18

P1.7/TA2 19

P5.

4/M

CLK

48

P2.6/ADC12C/DMAE0 26

P2.7/TA0 27

P5.

044

P5.

145

P5.

246

P5.

347

P4.

339

P4.

440

P4.

541

P4.

642

P4.

7/T

BC

LK43

P4.

0/T

B0

36P

4.1/

TB

137

P4.

2/T

B2

38

R8

9N

O-P

OP

R2

0710

0

L14

BLM

41P

750S

PT

Y6

8MH

z

14

R2

111K

C1

9N

O-P

OP

C92

.1u

F

C95

.1u

F

U1

0

TS

OP

3484

0

23 1

+C

981

0uF

6.3

V

C9

6

0.1

uF

L71

BLM

41P

750S

PT

R8

310

0

C2

2N

O-P

OP

C23

18

pF

Y5

32.7

68K

Hz 1

2

+C

104

10

uF 6

.3V

C9

9

0.1

uF

L70

BLM

41P

750

SP

T

R1

10N

O-P

OP

R22

810

KR

206

1K

J3

HE

AD

ER

7X

2

TD

O/T

DI

1N

C2

2T

DI/V

PP

3V

CC

_MS

P4

TM

S5

XO

UT

6T

CK

7T

ES

T/V

PP

8G

ND

9A

CLK

10R

ST

/NM

I11

AC

LKE

N12

NC

113

TC

LKE

N14

+C

93

10

uF 6

.3V

R8

510

0K

R2

101K

R8

210

K

R84

47K

BH

T1

BA

203

2SM

2 1

C26

18

pF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ALT

_3V

3

ALT

_3V

3

ALT

_3V

3

AL

T_3

V3

AL

T_3

V3

AL

T_3

V3

AL

T_3

V3

ALT

_3V

3

AL

T_3

V3

LE

D2

22

LE

D5

22

LE

D6

22

LE

D7

22

LE

D1

22

LE

D3

22

LE

D4

22

LE

D0

22

PB

_R

ES

ET

n22

SW

_DIP

022

SW

_DIP

122

SW

_DIP

222

PB

_SW

102

2

PB

_SW

112

2

PB

_SW

122

2

PB

_SW

132

2

NT

SC

_PA

L22

PB

_SW

142

2

SW

_DIP

322

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

232

6

B

DM

35

5

Eva

lua

tion

Mod

ule

SW

ITC

HE

S,

LE

DS

ET

C

NTSC

PAL

R16

633

0

R3

14

0

SW

10

PU

SH

BU

TT

ON

SW

AA

AB

BB

DS

21

LE

D

DS

19

LE

D

R1

70

330

R1

6733

0

DS

14

LE

D

R2

2210

K

R1

7333

0

R3

45

10K

DS

17

LE

D

SW

13

PU

SH

BU

TT

ON

SW

AA

AB

BB

R2

2110

K

R2

2310

K

R2

2010

KS

W11

PU

SH

BU

TT

ON

SW

AA

AB

BB

R3

4633

C2

42

1u

FD

S2

0

LE

D

R1

69

330

RN

26

RP

AC

K4-

1K

1 2 3 45678

C2

43

1u

F

R1

6833

0

DS

18

LE

D

DS

16

LE

D

C3

68

1u

F

R17

233

0

1 2 3 4

ON

SW

6

DIP

_S

WIT

CH

-4

1 2 3 45678

SW

5

PU

SH

BU

TT

ON

SW

AA

AB

BB

R2

1910

K

RN

27

RP

AC

K4

-10K

12345

678

C2

44

1u

F

J1 HE

AD

ER

31 2 3

C2

45

1u

F

DS

15

LE

D

SW

14

PU

SH

BU

TT

ON

SW

AA

AB

BB

R1

7133

0

SW

12

PU

SH

BU

TT

ON

SW

AA

AB

BB

C2

46

1u

F


A-25

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

McB

SP

_C

LK

R0

McB

SP

_CLK

X0

McB

SP

_FS

X0

McB

SP

_F

SR

0

McB

SP

_D

R0

McB

SP

_DX

0

VC

C_

5V

VC

C_

3V

3V

CC

_3

V3

VC

C_

1V

8

SP

I1_

SD

O2

SP

I1_

SD

I2

SP

I1_

SC

LK2S

PI1

_S

DE

NA

02

I2C

_D

AT

A2

,15,

18,1

9,2

2S

YS

_R

ES

ET

z2

2

McB

SP

_DX

02

McB

SP

_CLK

X0

2M

cBS

P_F

SX

02

McB

SP

_DR

02

McB

SP

_CLK

R0

2M

cBS

P_F

SR

02

I2C

_S

CL

K2

,15

,18,

19

,22

DM

350

_TIM

ER

IN3

2

UA

RT

1_T

XD

2U

AR

T1

_R

XD

2G

IO1

87

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

824

26

B

DM

355

E

valu

atio

n M

odul

e

I/O

DA

UG

HT

ER

CA

RD

IN

TE

RF

AC

E

DC

3

SM

T R

EC

PT

AC

LE

15X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CO

RE

_P

WR

_O

K

MS

P43

0_

1V3_

EN

AB

LE

VC

C_

5V

VC

C_

5V

AG

ND

VC

C_

5V

VC

C_

1V3

ALT

_3V

3

MS

P4

30_

1V

3_E

NA

BLE

22

ALT

_M

SP

430_

RE

SE

Tz

22

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5099

02-0

001

Fri

da

y, M

arch

14

, 2

00

825

26

B

DM

355

E

valu

atio

n M

odul

e

PO

WE

R S

UP

PL

Y M

SP

43

0_3

V3

, D

SP

CO

RE

( 1V

3)

3.3 sq in AGND,

min

thermal pad

Connect

at pin

1

EMI SUPPRESION. LOCATE NEAR EACH REGULATOR. 6

VIAS FROM PAD TO PLANE OR DIRECT TIE.

GND

Test Points

Vout = Vref * ( 1 + R1503/R1504)

Vref = 1.182 Volts

Vout = 3.6 volts

R1503 = 346K

1.4V -> 17.4K 1%

1.2V -> 28.0K 1%

1.1V -> 42.2K 1%

1.3V -> 22.1K 1%

TP

26T

P-6

0

R27

42

2.1

K 1

%

C3

22

0.1

uF

TP

21T

P-3

0C

317

330

0pF

TP

27T

P-6

0

U5

5

TP

S54

310

PW

P1

013

38-0

001

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

C31

30

.01

uF

L49

BLM

41P

750

SP

T

L62

BL

M4

1P75

0SP

T

C3

24

100

0pF

R9

51

0K

C3

19

NO

-PO

P

R1

783

48

K 1

%

C3

14

0.1

uF

TP

25T

P-6

0T

P29

TP

-60

R2

77

10

7 1

%

TP

30T

P-6

0

R27

91

0K

1%

R27

61

.65

K 1

%

C3

18

0.0

47

uF

+C

20

91

0u

F

1 2

+C

210

10

uF

1 2

C3

165

60p

F

R2

75

71

.5K

1%

C2

12

0.1

uF

1 2

C3

15

0.0

39u

F

R2

800

.02

5

+C

321

10

uF

LE

SR

L50

2.7

uH

C2

11

0.1

uF

R1

791

69

K 1

%

+C

323

10

0u

F 4

V

+C

32

5

100

uF

U2

0

TP

S7

301Q

DR

G4

IN3

OU

T5

SE

NS

E7

EN

2

IN4

GN

D1

RE

SE

T8

OU

T6

C3

20

0.1

uF

R27

8

10K

TP

23T

P-6

0

R3

49 0

TP

28T

P-6

0

TP

22T

P-6

0


A-27

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3V

3_

PW

R_O

K

1V8

_PW

R_

OK

AG

ND

VC

C_

3V3

VC

C_

5V

VC

C_

5V

VC

C_

5V

AG

ND

VC

C_1

V8

VC

C_5

V

MS

P4

30_

1V8

_EN

AB

LE

22

MS

P4

30_3

V3_

EN

AB

LE2

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5099

02-0

001

Fri

da

y, M

arc

h 1

4,

20

08

262

6

B

DM

35

5

Eva

luat

ion

Mo

dul

e

PO

WE

R S

UP

PL

Y 3

V3

, 1

V8

3.3 sq in AGND,

minthermal pad

Connect

at pin

1

Sets

Voltage



3.3V @1.5Amp Max

2.5

MM

JA

CK

3.3 sq in AGND,

min

thermal pad

Connect

at pin

1

Sets

Voltage



SILKSCREEN:

5V IN

U5

9

TP

S54

310P

WP

1013

38-0

001

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

TP

32T

P-3

0

+C

34

3

100

uF

4V

R3

02

2K

1%

L52

3.3

uH

C3

44

1000

pF

R3

01

71

.5K

1%

C3

49

0.0

39

uF

R3

16

NO

-PO

P

C3

54

0.1

uF

+C

357

10

0u

F 4

V

R3

031

07 1

%

R8

71

0K

R2

961

07 1

%

D3

SM

CJ6

A

TP

37T

P-6

0

1

+C

34

2

10

uF

LE

SR

R2

99

220

C3

410

.1u

F+

C3

45

100

uF

4V

C3

38

NO

-PO

P

C3

53

NO

-PO

P

C3

34

0.0

39

uF

+C

34

047

uF

R3

93

0

TP

33T

P-6

0

R2

94

71

.5K

1%

C33

54

70p

F

R3

06

0.0

25

U6

0

TP

S54

310P

WP

1013

38-0

001

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

C3

504

70p

F

J16

RA

SM

712

SLE

EV

ES

HU

NT

CE

NT

ER

C3

478

200

pF

R29

32

K 1

%

R4

39

0

R2

98

0.0

25

TP

31T

P-3

0

L53

BLM

41P

750S

PT

L51

BL

M4

1P75

0SP

T

C3

56

0.1

uF

TP

38T

P-6

0

DS

5

GR

EE

N

C3

32

820

0pF

C3

39

0.1

uF

R3

00

10

.2K

1%

R3

05

10

K 1

%

R3

04

10K

R2

95

10K

R2

971

0K

1%

L54

2.7

uH

C3

58

10

00p

F

R29

13

.74

K 1

%

TP34

TP-6

0

TP

36TP

-30

+C

35

51

0u

F L

ES

R

+C

346

10

0 u

F

C3

37

0.0

47

uF

+C

35

9

10

0 u

F

C3

52

0.0

47

uF

C3

33

0.1

uF

C3

48

0.1

uF

C3

36

330

0pF

R9

410

K

F1

F_

4.0

A

12

C3

51

3300

pF



B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about the DM355EVM produced by Spectrum Digital.


B-2 DM355 EVM Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE


B-3


B-4 DM355 EVM Technical Reference

Printed in U.S.A., April 2008509905-0001 Rev E

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information: Spectrum Digital:

702065

https://www.mouser.com/spectrum-digital

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