17/06/2020 Page 1

FTM Programming Model-Rev v0.0.22

The following is a specification for creating the module’s xml files.

The DSS FPGA is described in a separate section after the Control FPGA.

Ethernet Port Addresses (as defined in the connections.xml file ) are:

Control FPGA = 50001 , DSS1 FPGA = 50002 , DSS2 FPGA = 50003

A short description at the end of this document shows how the module’s Ethernet address is defined in firmware:

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Guidelines The power-up condition of all registers will be all zeros, unless otherwise stated. R/W = Read Write , R = Read Only

Control FPGA Slaves

Type Slave Function name IPBus Base Address (hex)

Address space

R Common_IdVersion 0 8

RW Module_Control 8 3

R XADC 10 12

RW Reconfigure 20 2

RW PLL_ SPI_RAM 100 64

RW FLASH_ SPI_RAM 200 512

RW L1A_Generator 400 512

RW Playback_Control 600 4

RW MGT_XCVR_Control 800 8

RW TTC_FMC 1000 8

RW FTM_Buffer_Control 1100 8

RW MGT_Error_Counters 1200 12

RW I2C_EEPROM 1300 10

RW I2C_MPODS 1310 10

RW I2C_BRIDGE 1320 10

RW I2C_ADCS 1330 10

RW TTCINFO 10000 5

RW MGT_Source_Ram 100000 16 x 8k

RW MGT_Sink_Ram 200000 16 x 8k

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Slave Register Descriptions

Each slave has one or more registers and/or memories as detailed below.

Common_IdVersion (R)

Hardware ID (+0)

bits(31- 28) = PCB Revision = 1 bits(27- 24) = PCB Version = 1 bits(23 -16) = PCB Serial number = contents of EEPROM(0) bits(15 - 0) = Module Type code = x"FD55” until proper code allocated

XmlVersion (+2)

Version(+0)

bits(31-24) = Major Version ( = 0) bits(23-16) = Minor Version ( = 0) bits(15-0) = Patch Version ( = 22)

GitSHA (+1)

bits(31-0) = GIT Hash

BuildTimeandDate (+4)

BuildDate (+0) - hexadecimal encoded binary “00mmddyyyy” BuildTime (+1) - hexadecimal encoded binary “0000hhmmss”

FirmwareVersion (+6)

Version(+0) as XML above

GitSHA (+1) as XML above

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Module_Control

Control (+0)

bit(24) = Vadj Power on. (if link set) bit(8) = PLL power down.

Pulse (+1)

bit(9) = DSS2 Reconfigure bit(8) = DSS1 Reconfigure bit(6) = PLL Synch. bit(2) = DSS2 Reset. bit(1) = DSS1 Reset. bit(0) = Module Reset

Status (+2)

bit(31) = FMC_Absent bits(15 – 12) IPMC Crate number bit(11) = DSS2 init_b bit(10) = DSS1 init_b bit(9) = PLL3 Lock. bit(8) = PLL2 Lock. bit(7) = PLL1 Lock. bit(6) = PLL0 Lock. bit(2) = DSS2 Configuration Done. bit(1) = DSS1 Configuration Done. bit(0) = Control Configuration Done = ‘1’

XADC Temperature (+0) , Temp_min(+1) , Temp_max(+2)

16 bit count. FSD = -273.0 °C to +230.7 °C (typically about 0xA000) VCC_Int (+3), … VCC_Aux (+6), … VCC_Bram (+9), …

All 3 sets of 3 VCCs above are 16 bit count with FSD = 0.0 to 3.0 V

Reconfigure

Address (+0)

bits(31-0) = Warm-boot address, but on a sector boundary. Bits(7-0) = zero.

Command (+1)

bit(0) = Configure. 1 = do-it

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Watchdog SPI

Key_lock (+0)

bits(31-2) = Key value. Value increments whenever Lock bit goes low. bit(1) = Lock bit. Set using IPBus RMW bus cycle. Starts timer. bit(0) = Timeout Error. Set if watchdog times-out and Lock stuck high

Timeout (+1)

bits(19-0) = Watchdog Timeout in ms. Default is 0.25 s. Writing a value restarts timer. A timeout reloads Default.

PLL_SPI_RAM

Select (+0)

bits(1-0) = Which PLL

Num_Words (+2)

bits(4 – 0)

Command (+3)

bit(0) = Do_it. A transition from 0 to 1 triggers transfer

Status (+4)

bit(0) = Busy

Watchdog (+10h)

Key/Lock and Timeout registers. Details given above

Outgoing (+20h..)

32 bit words x 16 deep

Incoming (+30h..)

32 bit words x 16 deep

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FLASH_SPI_RAM

Select (+0)

bits(1-0) = Which Configuration Flash. 0 = Own Flash. 1 = DSS1 , 2 = DSS2

Note this register will be depreciated so the only target is own Flash.

Num_Words (+2)

bits(4 – 0) = Number of Bytes

Command (+3)

bit(0) = Do_it. A transition from 0 to 1 triggers transfer

Status (+4)

bit(0) = Busy

Watchdog (+80h)

Key/Lock and Timeout registers. Details given above

Outgoing (+100h..)

32 bit words x 128 deep

Incoming (+180h..)

32 bit words x 128 deep Bytes are packed into a 32-bit word with MS Byte being sent / received first (Big-endian format.)

Watchdog I2C

Key_lock (+0)

bits(31-2) = Key value. Value increments whenever Lock bit goes low. bit(1) = Lock bit. Set using IPBus RMW bus cycle. Starts timer. bit(0) = Timeout Error. Set if watchdog times-out and Lock stuck high

Timeout (+1)

bits(9-0) = Watchdog Timeout in ms. Default is 0.25 s. Writing a value restarts timer. A timeout reloads Default.

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I2C Interface

Each interface has an identical register map . The following register map is a copy of the Open-Core’s .xml address map, plus the registers for Arbitration Watchdog.

ps_lo (+0)

clock division lsb

ps_hi (+1)

clock division msb

ctrl (+2)

control register

data (+3)

data read / write

cmd_stat (+4)

command / status

Watchdog (+8)

Key/Lock and Timeout registers. Details given above

Summary of individual interfaces given below I2C_EEPROM EEPROM (IC type 24LC01B) located at address 50h. (Also repeated at 51h – 57h)

I2C_MPODS Eight Transmitters are located at 28h - 2Fh, in groups of four as per associated DSS FPGA. Receivers are located at 30h - 31h.

DSS1 MiniPOD

I2C address (hex)

DSS2

MiniPOD I2C address

(hex)

OC3 28 OC1 2C

OC4 29 OC2 2D

OC9 2A OC7 2E

OC10 2B OC8 2F

OC6 30 OC5 31

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I2C_Bridge The Bridge device (IC type PCA9546A) is located at I2C address 71h. This connects to the IPMC Sensor I2C bus and to the Management I2C bus. The intended use of this is for testing the I2C devices on IPMC during initial commissioning of the board. Bridge control register:

bit(3) = Connect IPMB L bus (Not used) bit(2) = Connect IPMC Sensor bus bit(1) = Connect Management bus bit(0) = Unconnected

For example Write 0x02 to connect the Management bus, 0x00 to disconnect all. IPMC Sensor I2C bus:

Two Current and Voltage monitoring ADCs (type AD7998) at 20h - 21h Three Temperature monitoring sensors (type LM82) at 18h - 1Ah

Management I2C bus:

FRU EEPROM (type M24256) at 50h ATCA Power Brick (type ATC250) at 2Fh.

I2C_ADCS

Two Current and Voltage monitoring ADCs (type AD7998) at 20h - 21h (Only available on Production module)

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Playback_Control

This provides the local Orbit and BCRST signals. The Playback memories are synchronised to the local BCRST signal.

Frame_Count (+0)

bits(11 – 0) = Count = N. Playout N frames. Defaults to 3564 A typical use will be to program this to repeatedly cycle data through 16 frames and match the 16-word deep capture memory in an eFEX for example.

Control (+1)

bit(0) = Run . Repeated playout of N frames from first frame. bit(1) = Use_Ext_BCR. Use incoming TTC-FMC BCR (BC Reset). bit(2) = Use_Ext_ECR. Use incoming TTC-FMC ECR. bit(3) = Use_Ext_L1A. Use incoming TTC-FMC L1A.

Run signal is also passed to the DSS FPGA’s playback memory

Delay (+2)

bits(4 - 0) = BCR. Delay BCR to compensate for MGT latency when Hub1. Default is 3.

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TTC_FMC

Control (+0)

To be defined

FMC_Status (+4)

bit(3) = TTC-FMC_Lemo_in bit(2) = TTC Loss of lock bit(1) = TTC Loss of signal bit(0) = FMC_absent

BRC_Rxd (+5) only used for TTC debugging

bit(7) = BRC_b bit(6) = BRC_e bits(5-2) = BRC_d4 bits(1-0) = BRC_t2

ADD_Rxd (+6) only used for TTC debugging

bits(30-17) = ADD_b bit(16) = ADD _e bits(15-8) = ADD _s8 bits(7-0) = ADD _d8

L1A_Generator

Control (+0)

bits(7 – 0) = Num_L1As. Number of L1As in sequence.

Command (+1)

bit(0) = Run. Generate L1As. bit(2) = Repeat. Continuously Cycle. Otherwise Single-shot. bit(3) = NoWait. Otherwise sequence waits for next BCRST.

Status (+2)

bit(0) = Busy

Delay_RAM (+100h..)

32 bit words x 256 deep

A list defining the number of BC periods between L1A pulses. 0 = L1A follows in the

next BC, 1 = one BC period gap until the next L1A pulse. If Now = FALSE, the

sequence will start one BC after BCR, giving earliest possible L1A 2 BCs after BCR)

If L1A sequence duration > Orbit time, the sequence will complete. This allows for

example an L1A rate of 1 Hz to be setup, synchronously or not with BCR.

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TTCINFO

Rx_Control (+0)

bits(4 - 0) = TTC_FineTune. Delay recovered L1A,BCR & ECR by MGT clock ticks.

CRC_Errors (+1)

32 bits. Count CRC errors Cleared on write operation.

Tx_Control (+2)

bits(6 - 0) = TTC_INFO_Delay. Delays the outgoing TTC packet by N BCs. Note additional 1 BC delay, so range is 1 – 128 BCs.

Tx_Pulse (+3)

bit(0). ECR. Pulse ECR bit high for one BC.

Resets the L1ID counter feeding the TTC-INFO frame. L1ID count is incremented for each L1A generated.

bit(1). ECRID Reset.

Resets the ECRID counter feeding the TTC-INFO frame.

Tx_Status (+4) – read only

bits(23 - 0) = Current L1ID count value. bits(32 - 24) = Current ECRID count value.

Set_ECRID (+5)

bits(7 - 0) = Set ECRID count value. Note reading shows the value as written and not the current value which may have been incremented since the write operation.

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FTM_Buffer_Control

Control (+0)

bit(3) = Capture_Rx. Fill memory with MGT Receive data. bit(1) = Run_Playback. Play memory sequentially into MGTs.

Pulse (+1)

bit(0) = Sync_Frame. Synch MGT Tx frame to BC cycle.

Rx_Latency (+2)

bits(4 – 0) = Delay of RX ‘RUN’ from TX’ RUN’ in BCs (= link latency)

NValidFrames (+4) Read Only

How many complete frames of data can fit into playback memory. For information only. Set by firmware parameters.

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MGT_XCVR_Control

Quads115_116 (+0)

Quads117_118 (+8), Each bank covers two Quads containing 8 MGT channels. Structure of each bank is identical and shown below:

Control (+0)

bits(2 – 0) = MGT Loopback Mode bits. Applies to all MGTs. Default “000” Used for debugging receivers. ie “010” = Local PMA loopback. bits(6-4) = Tx Pattern Generator. Applies to all MGTs.

Default “000” = Standard operation Examples: “001” = PRBS-7, “010”= PRBS-15. See UG476.

Note: Quad 115 channel 1 is special as it communicates the TTC-INFO channel. When in hub1 slot the TTC-INFO generator is automatically connected to the MGT Tx, otherwise in a Node slot the memory is connected. The MGT receiver is connected to both the TTC-INFO receiver and the appropriate SinkRAM.

Pulse (+1)

bit(3) = MGT GTRX Reset Common to all 8 MGTs. bit(2) = MGT GTTX Reset. Common to all 8 MGTs. bit(1) = MGT RX Soft Reset Common to all 8 MGTs. bit(0) = MGT TX Soft Reset. Common to all 8 MGTs.

QuadStatus (+4)

bit(5) = QPLL1 RefLost. ie for Quad 116 bit(4) = QPLL0 RefLost. ie.for Quad 115 bit(1) = QPLL1 Locked. bit(0) = QPLL0 Locked.

TxStatus (+5),

bits(7 - 0) = Channel Reset Done. ie Quad116/3 .... Quad115/0

RxStatus (+6),

bits(7 - 0) = Channel Reset Done. ie Quad116/3 .... Quad115/0 bits(23 - 16) = Channel Byte Aligned. ie Quad116/3 …. Quad115/0

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MGT_Source_RAM

This will be mainly used when the FTM is operating in a Node slot to test links into a

Hub.

Memory is arranged into blocks with each block being connected to a different multi-

gigabit receiver or transmitter. Each block has 64k address space reserved for it, but

in the current design only 16k words are available in order to provide equally for 12

source and 12 sink connections..

The data framing is configured by the pointer control logic to send/receive a fixed

number of consecutive words per BC time-slice. Currently set for four 32bit words

per BC.

To Hub1 channels(0-5). Using Quads 117 and 118 SourceRam00 (+0)

32 bit words x 8k deep ContrlRam00 (+2000h)

4 bit words x 8k deep …

SourceRam07 (+70000h)

32 bit words x 8k deep ContrlRam07 (+72000h)

4 bit words x 8k deep The Readout channels to Hub1 are connected as follows:

Hub1 Readout channel# RAM block index Associated MGT Tx

0 06 118 /2

1 05 118 /1

2 04 118 /0

3 00 117 /0

4 02 117 /2

5 03 117 /3

Other connections

SGMII * 01 117 /1

FMC-DP1 * 07 118 /3

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To Hub2 channels(0-5). Using Quads 115 and 116

SourceRam08 (+80000h)

32 bit words x 8k deep ContrlRam08 (+82000h)

4 bit words x 8k deep … SourceRam15 (+F0000h)

32 bit words x 8k deep ContrlRam15 (+F2000h)

4 bit words x 8k deep The Readout channels to Hub2 are connected as follows:

Hub2 Readout channel# RAM block index Associated MGT Tx

0 14 116 /2

1 13 116 /1

2 12 116 /0

3 08 115 /0

4 10 115 /2

5 11 115 /3

Other connections

TTC-INFO 09 115 /1

FMC-DP0 * 15 116 /3

Note MGT Tx 115/1 is disconnected from SourceRAM(09) when the FTM is used in Hub1 slot. The MGT 115/1 sources TTC-INFO data when placed in Hub1 slot. In a Node slot, SourceRAM(09) may be used to test the TTC-INFO receiver of MGT 115/1 if this channel is placed in loopback mode. Items marked * are shown for completeness. These signals are not currently used.

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MGT_Sink_RAM This will be mainly used when the FTM is operating in a Hub slot to test links coming

from a Node slot, such as from an eFEX. Note only connected to Node slots 4 & 5

(logical numbering).

The Sink RAMs are mapped to MGTs as per the Source RAMs.

From Node slot 4 Readout channels (0-5).

SinkRam00 (+0) 32 bit words x 8k deep

… SinkRam07 (+70000h)

32 bit words x 8k deep

The Readout channels from Node4 slot are connected as follows:

Node4 Readout channel# RAM block index Associated MGT Rx

0 06 118 /2

1 05 118 /1

2 04 118 /0

3 00 117 /0

4 02 117 /2

5 03 117 /3

Other connections

SGMII * 01 117 /1

FMC-DP1 * 07 118 /3

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From Node slot 5 Readout channels (0-5). SinkRam08 (+80000h)

32 bit words x 8k deep … SinkRam15 (+F0000h)

32 bit words x 8k deep The Readout channels from Node5 slot are connected as follows:

Node5 Readout channel# RAM block index Associated MGT Rx

0 14 116 /2

1 13 116 /1

2 12 116 /0

3 08 115 /0

4 10 115 /2

5 11 115 /3

Other connections

TTC-INFO 09 115 /1

FMC-DP0 * 15 116 /3

Note the TTC-INFO channel is on MGT 115/1 Tx+Rx. When FTM used 1 Hub1, this

MGT can be placed in loopback mode and use SinkRam09 to capture outgoing TTC-

INFO.

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DSS FPGA Slaves

Type Function name IPBus Base Address (Hex)

Address space

R Common_IdVersion 0 8

RW FPGA_Control 8 3

R XADC 10 12

RW Reconfigure 20 2

RW FLASH_ SPI_RAM 200 200

RW MGT_XCVR_Control 800 32

RW DSS_Buffer_Control 1100 8

RW MGT_Error_Counter 200000 16

RW MGT_Source_RAM – 48 Blocks 400000 48 x 16k

RW MGT_Sink_RAM – 12 blocks 800000 12 x 64k

RW MGT_Ref_RAM – 12 blocks C00000 12 x 64k

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Common_IdVersion (R)

Hardware ID (+0)

bits(31 - 0) = FPGA Type code = x"00000D55”

XmlVersion (+2)

Version(+0)

bits(31-24) = Major Version ( = 0) bits(23-16) = Minor Version ( = 0) bits(15-0) = Patch Version ( = 22)

GitSHA (+1)

bits(31-0) = GIT Hash

BuildTimeandDate (+4)

BuildDate (+0) - hexadecimal encoded binary “00mmddyyyy” BuildTime (+1) - hexadecimal encoded binary “0000hhmmss”

FirmwareVersion (+6)

Version(+0) as XML above

GitSHA (+1) as XML above

.

17/06/2020 Page 20

FPGA_Control

Status (+2)

bit (0) = RUN signal from Control FPGA

XADC, Reconfigure and FLASH_SPI_RAM Registers and behaviour as per Control FPGA

DSS_Buffer_Control

Control (+0)

bit(3) = Capture_Rx. Fill memory with MGT Receive data. bit(2-1) = Tx Dummy data frame. 00 = eFEX , 01= jFEX , 10=gFEX bit(0) = Tx Dummy data frame. 0 = DATA, 1= ALIGN The playback RUN signal is received from the Control FPGA.

Pulse (+1)

bit(0) = Sync_Frame. Synch MGT Tx frame to BC cycle.

Rx_Latency (+2)

bits(4 – 0) = Delay of RX ‘RUN’ from TX’ RUN’ in BCs (= link latency)

NValidFrames (+4) Read Only

How many complete frames of data can fit into playback memory. For information only. Set by firmware parameters.

MGT_Error_Counters

Counter00 (+0) to Counter11 (+11) 32 bit counter that increments on a mismatch between incoming data and eFEX alignment pattern of 0xBC, 0x55555555, 0xAAAAAAAA, … . Error count cleared after write operation to that counter.

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MGT_XCVR_Control

Quads114_116 (+0)

Quads117_119 (+8),

Quads214_216 (+16),

Quads217_219 (+24) Each block covers three Quads containing the 12 MGT channels. Structure of each of the above is identical and shown below. Note only Quads114_116 are connected to MiniPOD receivers.

Control (+0)

bits(6 – 4) = MGT PRBS Mode bits. Common to all 12 MGTs. Default “000” = Standard operation, Examples: “001” = PRBS-7, “010”= PRBS-15. See UG476.

bit(3) = Power-up all 12 MGT Receivers. bits(2 – 0) = MGT Loopback Mode bits. Common to all MGTs. Default “000” Used for debugging receivers. ie “010” = Local PMA loopback.

Pulse (+1)

bit(3) = MGT GTRX Reset Common to all 12 MGTs. bit(2) = MGT GTTX Reset. Common to all 12 MGTs. bit(1) = MGT RX Soft Reset Common to all 12 MGTs. bit(0) = MGT TX Soft Reset. Common to all 12 MGTs.

QuadStatus (+4)

bit(6) = QPLL2 RefLost. ie for Quad 116 bit(5) = QPLL1 RefLost. ie for Quad 115 bit(4) = QPLL0 RefLost. ie.for Quad 114 bit(2) = QPLL2 Locked. bit(1) = QPLL1 Locked. bit(0) = QPLL0 Locked.

TxStatus (+5),

bits(11 - 8) = Q2Reset Done. ie. Quad 116 ch 3..0. bits(7 - 4) = Q1Reset Done. bits(3 - 0) = Q0Reset Done.

RxStatus (+6),

bits(11 - 8) = Q2Reset Done. For each MGT channel in Quad. bits(7 - 4) = Q1Reset Done. bits(3 - 0) = Q0Reset Done. bits(27 - 24) = Q2Byte Aligned. For each MGT channel in Quad. bits(23 - 20) = Q1Byte Aligned. bits(19 - 16) = Q0Byte Aligned.

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MGT_Source_RAM

Memory is arranged into 48 blocks of Dual-port RAM with each block being

connected to its own multi-gigabit transmitter. Each block has 8k words of 32 bits of

data which is played out from memory in address sequence. Consecutive words are

arranged into frames of seven 32bit words. One Frame is sent every BC giving a raw

link rate of 11.2 Gbps. The first frame will be repeated until a RUN command is

given. Should playout exceed available memory then data will be sourced from the

first frame.

A 4-bit wide Control RAM runs alongside the Source RAM to provide a mask bit for

each of the four bytes in the Source RAM. If it’s mask bit is set, the byte is

interpreted as a special control character known as a Comma which is used to

synchronise unpacking of the serial data at the receiver.

Xilinx MGTs are grouped into Quads within the chip. The FTM’s DSS Quads are

numbered 114 to 119 and 214 to 219, each with 4 channels 0 – 3.

The RAM is located in the same sequence as the channel numbering ie

MGT114/0,

MGT114/1,

MGT114/2,

MGT114/3,

MGT115/0

…

MGT219/3.

SourceRam00 (+0)

32 bit words x 8k deep ContrlRam00 (+2000h)

4 bit words x 8k deep … SourceRam47 (+2f0000h)

32 bit words x 8k deep ContrlRam47 (+2f2000h)

4 bit words x 8k deep

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MGT_Sink_RAM

Only one 12-way MiniPOD receiver is connected to each DSS. These channels are

received by Quads 114, 115 and 116. Each item below points to an instance of the

sink object which is a Spy memory as per the previous SinkRam** , a Reference

RAM and an error counter.

Sink00 (+0) Sink01 (+10000h) … Sink11 (+B0000h) Each sink instance is

SpyRAM (+0) = an 8k word RAM RefRAM (+2000h) = an 8k word RAM Error (+4000h) = an error counter which can be cleared by a write op.

17/06/2020 Page 24

A diagram of one MGT source and one MGT sink with controls is shown below:

To aid receiver alignment before data is sent, the source buffer will cycle on the first frame until a RUN command is given.

A BCReset signal will cause the buffer to return to its first frame and continue unloading from there.

Run

Data + Ctrl

Frame

sync

Local_BCR

Playback

RAM Run/BCR

MGT Tx

Data + Ctrl

Spy

RAM Loo

pb

ack

To MiniPODs

From MiniPODs

MGT Rx

Power on

Del

ay

Capture

Control FPGA

DSS FPGA – 1 channel

External_BCR

&

Reference

RAM

=

Counter

17/06/2020 Page 25

Memory to Ribbon Fibre Mapping

DSS FPGA SourceRAM

addresses

DSS0 Tx

Fibre 11 - 0

MiniPOD Ref

DSS0 Rx

Fibre 11 – 0

MiniPOD Ref

DSS1 Tx

Fibre 11 - 0

MiniPOD Ref

DSS1 Rx

Fibre 11 – 0

MiniPOD Ref

11 - 0 OC3 OC 6 OC 1 OC 5

23 - 12 OC4 OC 2

35 - 24 OC9 OC 7

47 - 36 OC10 OC 8

The individual channel connections for DSS1 is shown below.

MiniPOD Channel #

TX MGT# for OC3 (Quads

114-116)

TX MGT# for OC4 (Quads

117-119)

TX MGT# for OC9 (Quads

214-216)

TX MGT# for OC10 (Quads

217-219)

RX MGT# for OC6 (Quads

114-116)

0 114/2 117/2 214/2 217/2 114/1

1 114/0 117/1 214/0 217/1 114/2

2 114/3 117/3 214/3 217/3 114/0

3 114/1 117/0 214/1 217/0 114/3

4 115/2 118/2 215/2 218/2 115/3

5 115/1 118/1 215/0 218/0 115/1

6 115/3 118/3 215/3 218/3 115/0

7 115/0 118/0 215/1 218/1 115/2

8 116/3 119/3 216/3 219/3 116/0

9 116/0 119/0 216/0 219/0 116/3

10 116/2 119/2 216/2 219/2 116/1

11 116/1 119/1 216/1 219/1 116/2

Similarly for DSS2 which has an identical layout pattern to that of DSS1.

MiniPOD Channel #

TX MGT# for OC1 (Quads

114-116)

TX MGT# for OC2 (Quads

117-119)

TX MGT# for OC7 (Quads

214-216)

TX MGT# for OC8 (Quads

217-219)

RX MGT# for OC5 (Quads

114-116)

0 114/2 117/2 214/2 217/2 114/1

… … … … … …

11 116/1 119/1 216/1 219/1 116/2

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Use Cases

Single FTM DSS capturing own data for self-test and s/w development

For Control FPGA - Module_Control

Check Status bits (6..9) are set = PLLs 0-3 are locked

If not , pulse PLL_Synch bit 6 and re-check

For Control FPGA - Playback Control

Set Frame_Count to value N for N frames worth of data.

Produces a Local BC Reset every N BCs.

For DSS FPGA – MGT_XCVR_Control

Control register: Set bit(3) to turn on Receivers, Loopback = “010”

QuadStatus: Check QPLLs locked bits (2..0) are all high.

Load-up DSS SourceRAM memories as needed

For both DSS’s MGT_Buffer_Control – Pulse Register

Write ‘1’ to bit (0) = Synch_Frame

For Control FPGA – Playback_Control – Control register

Set bit(0) = RUN. which also propagates RUN signal into DSS’s

For DSS FPGA – MGT_Buffer_Control – Control

Set bit(3) = Capture receive data. May be turned off to freeze data.

For DSS FPGA

Check SinkRAM memory shows default SourceRAM data

ie SinkRAM00 = [bc,1,2,3,4,5,6,7,0….0]

Data may have an offset of a few BCs. This can be compensated for by

reprogramming a different latency into the DSS MGT_Buffer_Control

RxLatency register.

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Single FTM DSS playing back data into eFEX

For Control FPGA Module_Control

Check Status bits (6..9) are set = PLLs 0-3 are locked

If not , pulse PLL_Synch bit 6 and re-check

For both DSS’s MGT_XCVR_Control -> QUADSnnn_nnn

Check TxStatus bits(11..0)

if needed Pulse bit(1) MGT_TX_Reset

Load-up DSS memories as needed

For Control FPGA - Playback Control

Set Frame_Count to value N for N frames worth of data.

Produces a Local BC Reset every N BCs.

For both DSS’s MGT_Buffer_Control – Pulse Register

Write ‘1’ to bit (0) = Synch_Frame

For Control FPGA – Playback_Control – Control register

Set bit(0) = RUN. which also propagates RUN signal into DSS’s

.

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MGT Loopback Control bits

MGT PRBS Control bits

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Ethernet IP and MAC addresses

The Ethernet IP Address was originally defined from the Slot Position:

Ethernet IP Address. = 192.168.200.{shelf slot position}

for example when in hub slot 1, Address = 192.168.200.1

However, a more complicated scheme is needed for operation at CERN and at other locations such as RAL and Birmingham.

The Ethernet address scheme is evolving, but the following logic in VHDL shows the scheme currently in use:

MAC address

This is defined by the module’s serial number contained in an onboard eeprom. A block of MAC addresses has been allocated by CERN IT for the FTM to use:

mac_addr <= X"80D336003CD" & module_serial_number(3 downto 0);

This scheme will also be used in other locations such as Birmingham and RAL.

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IP Address

Uses a table of IP Addresses indexed by serial number if the Shelf Number indicates use at CERN, otherwise fall back to slot based scheme:

constant ip_addr_table: ip_addr_array := (

X"0A0B1E25", -- Sn0 = 10.11.30.37 for CERN

X"0A0B1E26", -- Sn1 = 10.11.30.38 for CERN

X"0A0B1E27", -- Sn2 = 10.11.30.39 for CERN

X"0A0B1E28", -- Sn3 = 10.11.30.40 for CERN

X"0A0B1E29", -- Sn4 = 10.11.30.41 for CERN

X"0A0B1E2A", -- Sn5 = 10.11.30.42 for CERN

X"0A0B1E2B", -- Sn6 = 10.11.30.43 for CERN

X"0A0B1E2C", -- Sn7 = 10.11.30.44 for CERN

X"0A0B1E2D", -- Sn8 = 10.11.30.45 for CERN

X"0A0B1E2E", -- Sn9 = 10.11.30.46 for CERN

others => X"0A0B1E25"

);

case ShelfNo is

when X"1" | X"2" | X"3" | X"4" => use_serial_no <= TRUE; -- Shelf at CERN

when X"5" | X"6" => use_serial_no <= FALSE; -- Shelf at RAL

when others => use_serial_no <= FALSE;

end case;

force_ipadd <= TRUE when force_mac_n = '0' and pcb_version /= "00" else FALSE; -- only use on production modules

ip_addr <= X"c0a8c801" when force_ipadd -- 192.168.200.1

else ip_addr_table(module_sn) when use_serial_no -- The sn# scheme

else X"c0a8c80" & hw_addr(3 downto 0); -- The slot scheme

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Document Revision History

Revision 1.1.5

Minor change to ID_Version Register of both FPGA types.

Added USE_TTCFMC bit to PlaybackControl to select external TTC BCR signal.

Revision 1.2.0

Updated USE_TTCFMC bits to PlaybackControl to select external BCR,ECR and

L1A signals.

L1A Generator Control/Command register bit(3) renamed “Now” -> “NoWait”.

Revision 1.3.0

ECRID counter added, with reset and read-back via IPBus register

Revision number now jumps to use the HOG build scheme numbering

Revision v0.0.8

Common ID register now uses version generics from HOG.

Added details of Ethernet IP and MAC address scheme

Revision v0.0.9

IP address can now be forced to 192.168.200.1 by use of link header

(Just for information as this is not under program control)

Revision v0.0.10 - 14

Some cosmetic changes to F/W + Hog updates

(Just for information these do not affect programming model)

Revision v0.0.15

Ethernet IP address scheme updated

Added gFEX dummy data generation with control bit.

Updated Dummy Data generator for Control FPGA. Now single IDLE word.

Revision v0.0.16 - 21

Some cosmetic changes to F/W + Hog updates

(Just for information these do not affect programming model)

Revision v0.0.22

Added a write register Set_ECRID to TTCINFO block.

Renamed Tx_L1ID register as Tx_Status.