TK3723+Data+Sheet+v0.23

TK3723 Data Sheet PreliminaryDual Turbo-EPONTM MAC Traffic Manager for OLT

Rev 0.23

Teknovus Confidential - View Under NDA Only This document contains information on a new product. Specifications and information herein are subject to change without notice.

FEATURES Two IEEE 802.3ah Ethernet-PON MAC

Controllers 2.5 Gbps and 1.25 Gbps downstream rate

options on each PON channel 1.25 Gbps upstream rate on each PON

channel Two IEEE 802.3z Gigabit Ethernet MAC

Controllers with MII, GMII and TBI interfaces Hardware-based configurable Dynamic

Bandwidth Allocation (DBA) System solution with firmware for embedded

ARM9 processor IEEE 802.3ah OAM IEEE 802.3ah Forward Error Correction on

the PON interfaces IEEE 802.1D bridging: 8K MAC Address

learning and aging on local interface IEEE 802.1p with four priority queues per

LLID IEEE 802.1Q VLAN mapping to LLID Supports 256 bidirectional (downstream and

upstream) LLIDs for each PON interface plus 128 downstream-only multicast LLIDs per PON

Per-LLID/customer downstream security using AES-128 encryption or Triple Churning (CTC) algorithms

Line-rate Layer-2/3/4 filtering and classification including IPv6 support

Bi-Directional SLA enforcement per LLID IGMP/MLD Proxy and IP Multicast Shaping Supports multiple mesh and WDM system

configurations 10/100 MII (CRAFT) or Asynchronous Bus

Management Interface 2048 queues (FIFOs) shared between

downstream and upstream direction, stored in up to 256 Megabytes of low-cost external DDRII DRAM memory

Supports Local and Remote Loop-back test Strobe pins for optical burst monitoring 32 GPIO pins IEEE 1149.1 JTAG Boundary Scan 3.3V/1.8V I/O and 1.2V Core supply 35 x 35 mm 927 HSBGA package

DESCRIPTION The TK3723 is a dual IEEE 802.3ah standard Ethernet PON (EPON) MAC controller for Optical Line Terminals (OLT). It incorporates two EPON MACs for WAN connectivity to a passive point-to-multipoint (PON) optical fiber network, and two IEEE 802.3z Gigabit Ethernet MACs as a Central Office Network Interface. Each TK3723 EPON channel provides 2.5 Gbps and 1.25 Gbps downstream rate options while maintaining a 1.25 Gbps upstream rate. The TK3723 provides service policy, security and authentication management to meet the requirements for carrier applications. An embedded ARM9 processor provides a management system for self management, auto discovery, and bandwidth provisioning. The TK3723 can be used in either a Media Converter or Line-card configuration.

The TK3723 is compatible with all Teknovus ONU chipsets.

http://www.elecfans.com/ ?????? http://www.hqpcb.com/ ??PCB


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Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT Figure 1.



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Revision History

This section records the change history of this Data Sheet.

Table 1. Revision History

Date Version Revision Description Author

August 3, 2007 0.10 - Preliminary Initial Release - Updated power consumption characteristics - Listed DDRII DRAM and SDRAM required characteristics

Jerry Wojtowicz

August 6, 2007 0.11

- Added Data Sheet progression information (back page) - Added System Organizations sections - Removed presently unsupported encryption modes - Added DDRII DRAM and SDRAM layout guidelines

Bill Burns Jerry Wojtowicz

December 17, 2007 0.12

- Updated SDRAM layout guidelines to include 16-bit wide devices - Updated supported FLASH list to include Spansion device - Updated System Organizations section with WDM modes - Added Reset and Output Clocks AC characteristics - Added DDRII DRAM AC characteristics

Jerry Wojtowicz

February 29, 2008 0.13

- Added FLASH AC characteristics - Added SDRAM AC characteristics - Added FLASH layout guidelines - Updated I/O latch-up current to be JEDEC compliant - Updated JEDEC IDCODE code - Updated DDRII DRAM AC characteristics

Jerry Wojtowicz

April 25, 2008 0.20 - Updated SDRAM AC characteristics - Updated supported FLASH list to include Intel/Numonyx device - Updated TK3723 Ordering Information for rev. B of the chip

Jerry Wojtowicz

December 12, 2008 0.21

- Updated DDRII AC characteristics - Changed GPI027 pin name to GPI27 - Updated LOC_Px_DNCOMDET pins description in GMII mode - Updated ARM_WDOUT_N / ARM_RSTOUT_N pin description - Updated power consumption characteristics

Jerry Wojtowicz

February 13, 2009 0.22

- Corrected max Tc value in Table 21 - Added Leaded package option in TK3723 Ordering Information

Jerry Wojtowicz

May 12, 2009 0.23

- Modified Reset AC characteristics - Added ARM_WDOUT_N AC characteristics - Changed Teknovus Logo - Updated DDRII, SDRAM and FLASH Interfaces PCB layout guidelines - Added EPON SerDes and Transceiver Interfaces sections - Updated supported FLASH list to include ST Micro device

Jerry Wojtowicz



Page 4 of 89 Rev 0.23 Teknovus Confidential - View Under NDA Only

Table of Contents 1 TK3723 Functional Description ..................................................................................................................................... 8

1.1 System Organizations ......................................................................................................................................... 101.1.1 Two Network-side Interfaces to Two 1.25 Gbps EPONs ........................................................................ 101.1.2 Two Network-side Interfaces Aggregated to a Single 2.5 Gbps EPON .................................................. 101.1.3 One Network-side Interface Expanded to Two 1.25 Gbps Separate EPONs ......................................... 111.1.4 Two Network-side Interfaces Expanded to Two 2.5 Gbps EPONs ......................................................... 111.1.5 Two Network-side Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs ........................................ 121.1.6 Two Network-side Interfaces Aggregated to a Single WDM EPON ........................................................ 12

1.2 IEEE 802.3ah EPON MACs ................................................................................................................................ 131.2.1 EPON SerDes Interfaces ........................................................................................................................ 131.2.2 EPON Transceivers Interfaces ............................................................................................................... 14

1.3 Dynamic Bandwidth Allocation Control (DBA) ..................................................................................................... 151.4 IEEE 802.3z Gigabit Ethernet MACs ................................................................................................................... 161.5 Lookup Engines (LUEs)....................................................................................................................................... 161.6 Packet Buffering (FIFOs) ..................................................................................................................................... 17

1.6.1 DDRII Interfaces PCB Layout Guidelines ............................................................................................... 171.7 Shapers/Schedulers ............................................................................................................................................ 181.8 ARM9 Processor Subsystem ............................................................................................................................... 18

1.8.1 FLASH Interface PCB Layout Guidelines ............................................................................................... 201.8.2 SDRAM Interface PCB Layout Guidelines .............................................................................................. 20

1.9 Host Interfaces .................................................................................................................................................... 201.10 GPIO Interface .................................................................................................................................................... 221.11 UART Interface .................................................................................................................................................... 231.12 Ethernet Serial Management Interface ................................................................................................................ 241.13 JTAG and Test Interfaces .................................................................................................................................... 24

2 TK3723 Signals Description ......................................................................................................................................... 262.1 Signals Types ...................................................................................................................................................... 262.2 Signals Names Description ................................................................................................................................. 262.3 Signals Sorted in Ball Numerical Order ............................................................................................................... 52

3 TK3723 Electrical Specifications ................................................................................................................................. 603.1 Absolute Maximum Ratings ................................................................................................................................. 603.2 Recommended Operating Conditions ................................................................................................................. 613.3 Power Supplies Current and Power .................................................................................................................... 613.4 Power Supplies Sequencing ................................................................................................................................ 623.5 DC Characteristics .............................................................................................................................................. 63

3.5.1 CMOS I/O DC Characteristic .................................................................................................................. 633.5.2 SSTL-18 I/O DC Characteristic ............................................................................................................... 63

3.6 AC Characteristics ............................................................................................................................................... 653.6.1 System Clock Timing .............................................................................................................................. 653.6.2 Local-Side MII/GMII/TBI Timing .............................................................................................................. 663.6.3 Plant-Side TBI Timing ............................................................................................................................. 693.6.4 DDRII DRAM Interfaces Timing .............................................................................................................. 713.6.5 ARM9 Interface Timing ........................................................................................................................... 733.6.6 CRAFT Port MII Timing .......................................................................................................................... 77




3.6.7 Ethernet Serial Management Timing ...................................................................................................... 783.6.8 Asynchronous Bus Timing ...................................................................................................................... 793.6.9 GPIO Timing ........................................................................................................................................... 813.6.10 Reset Timing .......................................................................................................................................... 82

4 TK3723 Mechanical Specifications ............................................................................................................................. 834.1 Package Diagram ................................................................................................................................................ 834.2 Package Thermal Specifications ......................................................................................................................... 854.3 Package Thermal Requirements ......................................................................................................................... 854.4 Heatsink Selection ............................................................................................................................................... 86

5 TK3723 Ordering Information ...................................................................................................................................... 88

List of Tables Table 1. Revision History ................................................................................................................................................. 3Table 2. JTAG Instructions............................................................................................................................................. 24Table 3. ARM9 Processor Bus Interface ........................................................................................................................ 26Table 4. Inter-Processor Asynchronous Bus Interface ................................................................................................... 29Table 5. Ethernet Serial Management Interface ............................................................................................................. 30Table 6. Management Port (CRAFT) MII Interface ........................................................................................................ 31Table 7. Local-Side PHY/SerDes MII/GMII/TBI Interface - Port 1 .................................................................................. 31Table 8. Plant-Side SerDes Interface Port 1 ............................................................................................................... 33Table 9. Ethernet PON Transceiver Interface Port 1 ................................................................................................... 36Table 10. Packet Buffer DDRII DRAM Interface Port 1 ................................................................................................. 37Table 11. Local-Side PHY/SerDes MII/GMII/TBI Interface Port 2 ................................................................................. 39Table 12. Plant-Side SerDes Interface Port 2 ............................................................................................................... 41Table 13. Ethernet PON Transceiver Interface Port 2 ................................................................................................... 45Table 14. Packet Buffer DDRII DRAM Interface Port 2 ................................................................................................. 45Table 15. JTAG and Test Interface .................................................................................................................................. 48Table 16. Reference Clocks, System Reset, PLL and GPIO Interface ............................................................................ 48Table 17. Power and Ground ........................................................................................................................................... 49Table 18. Signals Sorted in Ball Numerical Order ............................................................................................................ 52Table 19. Absolute Maximum Ratings ............................................................................................................................. 60Table 20. Recommended Operating Supply Voltages ..................................................................................................... 61Table 21. Recommended Operating Temperatures ......................................................................................................... 61Table 22. Power Consumption ......................................................................................................................................... 61Table 23. CMOS I/O DC Characteristics .......................................................................................................................... 63Table 24. SSTL-18 I/O DC Characteristics ...................................................................................................................... 63Table 25. System Clock Source Requirements ................................................................................................................ 65Table 26. Local-Side MII Input Timing (MAC Mode) ........................................................................................................ 66Table 27. Local-Side MII Output Timing (MAC Mode) ..................................................................................................... 66Table 28. Local-Side GMII Input Timing (PHY and MAC Mode) ...................................................................................... 67Table 29. Local-Side GMII Output Timing (PHY and MAC Mode) ................................................................................... 67Table 30. Local-Side TBI Input Timing (MAC Mode) ........................................................................................................ 68Table 31. Local-Side TBI Output Timing (MAC Mode) ..................................................................................................... 68Table 32. Plant-Side TBI Input Timing ............................................................................................................................. 69Table 33. Plant-Side TBI Output Timing .......................................................................................................................... 70




Table 34. DDRII DRAM Write Timing (BL=8, WL=2, AL=0, WR=2) ................................................................................. 71Table 35. DDRII DRAM Read Timing (BL=8, RL=3, AL=0, CL=3) ................................................................................... 72Table 36. FLASH Write Timing ........................................................................................................................................ 73Table 37. FLASH Read Timing ........................................................................................................................................ 74Table 38. SDRAM Write Timing (CL=3, BL=8) ................................................................................................................. 75Table 39. SDRAM Read Timing (CL=3, BL=8) ................................................................................................................ 76Table 40. CRAFT Port MII Input Timing (MAC Mode) ...................................................................................................... 77Table 41. CRAFT Port MII Output Timing (MAC Mode) ................................................................................................... 77Table 42. MDIO Serial Management Timing .................................................................................................................... 78Table 43. Asynchronous Bus Read Timing ...................................................................................................................... 79Table 44. Asynchronous Bus Write Timing ...................................................................................................................... 79Table 45. GPIO Timing .................................................................................................................................................... 81Table 46. Reset Timing .................................................................................................................................................... 82Table 47. 927-HSBGA Package Dimensions ................................................................................................................... 84Table 48. 927-HSBGA Thermal Specifications for JEDEC 4-layer PCB .......................................................................... 85Table 49. INL35001-10/1.7BU Heatsink Thermal Characteristics .................................................................................... 86

List of Figures Figure 1. Block Diagram of TK3723-Based Turbo-EPONTM Dual OLT .............................................................................. 2Figure 2. TK3723 Block Diagram ...................................................................................................................................... 9Figure 3. Two Distinct EPONs ......................................................................................................................................... 10Figure 4. Two Network Interfaces Aggregated to a Single 2.5 Gbps EPON ................................................................... 10Figure 5. One Network Interface Expanded to Two 1.25 Gbps EPONs .......................................................................... 11Figure 6. Two Network Interfaces Expanded to Two 2.5 Gbps EPONs .......................................................................... 11Figure 7. Two Network Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs .......................................................... 12Figure 8. Two Network Interfaces Aggregated to a WDM EPON with two 1.25 Gbps Downstream Flows ..................... 12Figure 9. Two Network Interfaces Aggregated to a WDM EPON with 1.25 Gbps and 2.5 Gbps Downstream Flows ..... 13Figure 10. EPON SerDes Interfaces* ................................................................................................................................ 14Figure 11. FEC and Squelch Regions for typical APD receiver......................................................................................... 15Figure 12. TK3723 DDRII Interfaces ................................................................................................................................. 17Figure 13. TK3723 Host Interfaces ................................................................................................................................... 22Figure 14. Simplified GPIO Pin Block Diagram ................................................................................................................. 23Figure 15. UART Interface Timing ..................................................................................................................................... 23Figure 16. MDIO Serial Management Read and Write Timing .......................................................................................... 24Figure 17. DEVICE IDENTITY Register Fields .................................................................................................................. 25Figure 18. System Clock Source Timing ........................................................................................................................... 65Figure 19. Local-Side MII Input Timing (MAC Mode) ........................................................................................................ 66Figure 20. Local-Side MII Output Timing (MAC Mode) ..................................................................................................... 66Figure 21. Local-Side GMII Input Timing (PHY and MAC Mode) ...................................................................................... 67Figure 22. Local-Side GMII Output Timing (PHY and MAC Mode) ................................................................................... 67Figure 23. Local-Side TBI Input Timing (MAC Mode) ........................................................................................................ 68Figure 24. Local-Side TBI Output Timing (MAC Mode) ..................................................................................................... 68Figure 25. Plant-Side TBI Input Timing ............................................................................................................................. 69Figure 26. Plant-Side TBI Output Timing .......................................................................................................................... 70Figure 27. DDRII DRAM Write with Auto-precharge Timing .............................................................................................. 71




Figure 28. DDRII DRAM Read with Auto-precharge Timing ............................................................................................. 72Figure 29. FLASH Write Timing ........................................................................................................................................ 73Figure 30. FLASH 16-bit Read Timing .............................................................................................................................. 74Figure 31. FLASH 32-bit Read Timing .............................................................................................................................. 74Figure 32. SDRAM Write with Auto-precharge Timing ...................................................................................................... 75Figure 33. SDRAM Read with Auto-precharge Timing ...................................................................................................... 76Figure 34. CRAFT Port MII Input Timing (MAC Mode) ...................................................................................................... 77Figure 35. CRAFT Port MII Output Timing (MAC Mode) ................................................................................................... 77Figure 36. MDIO Serial Management Timing .................................................................................................................... 78Figure 37. Asynchronous Bus 32-bit Data Read Timing ................................................................................................... 79Figure 38. Asynchronous Bus 16-bit Data Read Timing ................................................................................................... 79Figure 39. Asynchronous Bus 32-bit Data Write Timing .................................................................................................... 80Figure 40. Asynchronous Bus 16-bit Data Write Timing .................................................................................................... 80Figure 41. GPIO Timing .................................................................................................................................................... 81Figure 42. Reset Timing .................................................................................................................................................... 82Figure 43. 927-HSBGA Package Diagram ........................................................................................................................ 83Figure 44. Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (without Heatsink) ............. 85Figure 45. Derating Curves for 927-HSBGA Package on 4-layer JEDEC PCB for TJ=125C (with Heatsink) .................. 87Figure 46. TK3723 Ordering Information ........................................................................................................................... 88




1 TK3723 Functional Description The TK3723 provides OLT functionality to access an IEEE 802.3ah standard Ethernet Passive Optical Network (EPON). Local-side connectivity is Gigabit (or 100Mbit) Ethernet to either a switch for media-converter mode, or a PHY device for line-card mode.

The TK3723 provides dual PON-side interfaces and dual Network-side interfaces. Each EPON MAC provides 256 bi-directional LLIDs plus 128 downstream multicast LLIDs.

The EPON interfaces on the TK3723 can be configured to operate at 2.5 Gbps or 1.25 Gbps downstream rate. The upstream rate is 1.25 Gbps.

EPON security is provided on a per-LLID basis. TK3723 supports downstream AES128 CFB and Triple Churning (CTC) encryption modes.

Forward Error Correction (FEC) is supported on the EPON interface. IEEE 802.3ah FEC provides improved system performance in noisy optical environments.

Downstream data passes from the receiving interface into an Ethernet Lookup Engine module which determines the appropriate LLID based on the Layer 2 MAC Addresses, L2/L3 protocol types, IEEE 802.1p priority, and/or IEEE 802.1Q VLAN tag information. In the upstream direction, incoming frames are pre-tagged with the appropriate LLID.

In the upstream direction, an Ethernet PON MAC checks and manages the range delays for incoming frames. Timing strobes for an external burst mode transceiver can be configured. An EPON Lookup Engine modifies the frames to insert VLAN tags, learn MAC Addresses, and classify upstream traffic. Frames are then written into the queues in external SDRAM by the FIFO Controller.

The Lookup Engines may duplicate packets to multiple ports. This enables IP multicast to duplicate downstream packets to both PON interfaces.

The FIFO queues are read by the Shaper/Scheduler modules according to the provisioned Service Level Agreement (SLA). The frames are passed to a local-side Gigabit Ethernet interface, or to an EPON MAC.

The Shaper/Scheduler modules schedule downstream traffic to provisioned SLAs. The internal DBA Controllers generate GATE messages to schedule upstream traffic based on provisioned latency and bandwidth SLAs.




Figure 2. TK3723 Block Diagram




1.1 System Organizations

The TK3723 supports a variety of system organizations. This section describes seven possible configurations.

1.1.1 Two Network-side Interfaces to Two 1.25 Gbps EPONs The TK3723s dual-channel architecture allows using single OLT chip to create two completely separate EPONs.

Figure 3. Two Distinct EPONs

1.1.2 Two Network-side Interfaces Aggregated to a Single 2.5 Gbps EPON Traffic from the two network-side Ethernet ports can be combined (fully or partially) to provide enough downstream bandwidth to fill either 2.5 Gbps EPON channel.

TK3723 Dual OLT

Network (1)

Network (2)

ONU1

802.3zMAC

Channel 2

ONU2

ONU3

PON

GigabitEthernet

GigabitEthernet

802.3zMAC

Channel 1

802.3ahMAC

Channel 1

1.25Gbps Upstream

nstream2.5Gbps Dow

802.3zMAC

Channel 2

802.3ahMAC

Channel 2

1.25G Dn/1.25G Up TK3713 or TK3714/15 ONU

2.5G Dn/1.25G Up TK3714/15 ONU

Figure 4.

Two Network Interfaces Aggregated to a Single 2.5 Gbps EPON




1.1.3 One Network-side Interface Expanded to Two 1.25 Gbps Separate EPONs For configurations with a large number of subscribers but limited total bandwidth, either network-side Ethernet port can be expanded to two separate 1.25 Gbps EPON channels.

Figure 5. One Network Interface Expanded to Two 1.25 Gbps EPONs

1.1.4 Two Network-side Interfaces Expanded to Two 2.5 Gbps EPONs For configurations with a large number of subscribers and high bandwidth requirements, traffic from two network-side Ethernet ports can be copied (fully or partially) to two separate 2.5 Gbps EPON channels (mesh configuration).

Figure 6. Two Network Interfaces Expanded to Two 2.5 Gbps EPONs




1.1.5 Two Network-side Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs For configurations with a large number of subscribers with different bandwidth requirements, traffic from two network-side Ethernet ports can be copied (fully or partially) to two separate EPON channels which can have different downstream rates (mesh configuration).

Figure 7. Two Network Interfaces Expanded to 1.25 Gbps and 2.5 Gbps EPONs

1.1.6 Two Network-side Interfaces Aggregated to a Single WDM EPON For configurations with very high downstream bandwidth requirements, traffic from two network-side Ethernet ports can be copied (fully or partially) to two separate downstream flows feeding a single EPON. The two downstream flows can be transmitted at different wavelengths using WDM techniques. In this configuration only channel 1 can be receiving upstream traffic. This configuration allows (but is not limited to) using mixed speed ONUs (1.25 Gbps and 2.5 Gbps) on the same EPON.

TK3723 Dual OLT

Network (1)

Network (2) 802.3zMAC

Channel 2

GigabitEthernet

GigabitEthernet

802.3zMAC

Channel 1

802.3ahMAC

Channel 1

802.3ahMAC

Channel 2

802.3zMAC

Channel 2

ONU1

ONU2

ONU3

WDM PON

1.25Gbps Upstream

1.25Gbps Downstream

WDM Splitter

1490nm Dn1310nm Up

1550nm Dn

1.25Gbps Downstream

Figure 8.


2.5G Dn/1.25G Up TK3714/15 ONU

Two Network Interfaces Aggregated to a WDM EPON with two 1.25 Gbps Downstream

Flows




TK3723 Dual OLT

Network (1)

Network (2) 802.3zMAC

Channel 2

ONU1

ONU2

ONU3

WDM PON

GigabitEthernet

GigabitEthernet

1.25Gbps Upstream

1.25Gbps Downstream802.3zMAC

Channel 1

802.3ahMAC

Channel 1

2.5Gbps Downstream802.3zMAC

Channel 2

802.3ahMAC

Channel 2

WDM Splitter

1490nm Dn1310nm Up

1550nm Dn


2.5G Dn/1.25G Up TK3714/15 ONU

Figure 9. Two Network Interfaces Aggregated to a WDM EPON with 1.25 Gbps and 2.5 Gbps

Downstream Flows

1.2 IEEE 802.3ah EPON MACs

The two IEEE 802.3ah EPON MACs send downstream data to the PON and receive upstream data from the PON. Each of the EPON MACs may operate at 2.5 Gbps or 1.25 Gbps downstream rate. The upstream rate is 1.25 Gbps.

The EPON MACs each support 256 LLIDs for bidirectional traffic, plus an additional 128 LLIDs for downstream-only multicast traffic.

EPON security is provided on a per-LLID basis. TK3723 supports downstream AES128 CFB and Triple Churning (CTC) encryption modes.

Forward Error Correction (FEC) is provided on the EPON interface on a per-LLID basis. IEEE 802.3ah FEC provides improved system performance in noisy optical environments.

The EPON MACs collect statistics (per-LLID) to support RMON Level 2 requirements.

1.2.1 EPON SerDes Interfaces The EPON MACs connect to EPON SerDes devices via Ten-Bit interfaces (TBI) at 1.25 Gbps, or via 16..20-bit wide interfaces (2xTBI) at 2.5 Gbps.

The following SerDes devices were verified to function properly in EPON and Turbo-EPONTM applications:

Texas Instruments: o TLK2541 (2.5 Gbps or 1.25 Gbps, Teknovus recommended) o TLK1221 (bidirectional 1.25 Gbps only; low-cost) o TLK1211 (bidirectional 1.25 Gbps only) o TLK2201B (bidirectional 1.25 Gbps only)

AMCC: o S2060A/QSC (bidirectional 1.25 Gbps only, End-of-Life).

TK3723 allows two ways to provide reference clocks to the SerDes devices (see Figure 10). For SerDes devices that have only one input clock (e.g. TLK1211, TLK1221, TLK2201B, S2060A/QSC) which serves as both the PLA_Px_DND bus clock and the SerDes Tx reference clock source, an externally distributed 125MHz clock source is recommended (see section 3.6.3 Plant-Side TBI Output Timing for detailed AC characteristics).




Figure 10. EPON SerDes Interfaces*

* any SerDes can be connected to either OLT channel.

PLA_Px_DNCLK signals are not recommended to be used as reference clock sources to the SerDes.

For SerDes devices that have two input clocks (e.g. TLK2541), the TK3723 PLA_Px_DNCLK signals can be used to clock-in the PLA_Px_DND buses, while externally distributed clean 125MHz clocks are recommended to be used as SerDes reference sources.

1.2.2 EPON Transceivers Interfaces The EPON SerDes connects to optical transceivers devices via differential serial interfaces. Since the upstream 1.25 Gbps flows are of the burst nature it is recommended that the interface between the Optical Transceiver Rx output and the SerDes Rx input is DC coupled, i.e. does not use AC coupling capacitors. This approach will allow minimizing SerDes synchronization time which will maximize PON performance.

1.2.2.1 Squelch Function and FEC

Typical optical transceivers perform a squelch function. This function eliminates optical noise from entering the system when no optical signal is present. Optical noise may cause SerDes receive clocks to operate out of their intended frequency range, and prevent them from locking when a valid signal returns. Optical noise may also result in invalid characters being received into the MAC interface.

The squelch function in a typical transceiver module asserts a loss of signal when the input optical signal drops below a defined optical power threshold. The loss of signal pin is then connected to an output enable pin at the post amp which disables the output signal when no signal is present. This blocks the noise between bursts from reaching the SerDes.

Squelch may limit the performance of FEC. Some transceivers have been observed to squelch the output at optical powers in the range where FEC is beneficial. Squelch can therefore limit the performance of FEC if its receive threshold is not set to the correct level.




within operating range

outside operating range - above saturation level

Optical Power [dBm]

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

Receiver not FEC-ready Receiver FEC-ready

outside operating range below noise level

SD hysteresis

SD hysteresisFEC Gain

(SD function must prevent entering this region)

Figure 11. FEC and Squelch Regions for typical APD receiver

The FEC coding is effective on bit error rates (BER) down to 1E-4. The loss of signal level should be set to an optical power level that corresponds to a BER of 1E-4. This is typically adjusted through a resistor setting connected to the post amp.

The timing of the squelch circuit is important as well. The threshold should be adjusted such that the squelch is activated at the end of an upstream burst prior to noise being output.

Teknovus does not recommend disabling the squelch function, even when FEC is used. The optical noise between burst at BER rates higher than 1E-4 has been shown to result in packet loss and deregistration on the PON.

1.3 Dynamic Bandwidth Allocation Control (DBA)

The Dynamic Bandwidth Allocation (DBA) modules schedule upstream traffic on the PON (see Figure 2.

DBA schedules two major types of traffic:

Solicited Shaped, scheduled grants which dynamically respond to the amount of upstream data reported by ONUs, and to the amount of space available in the destination queue

TDM High priority, unsolicited, fixed-period grants used to transport traffic requiring low latency.




For Solicited traffic, DBA contains a Shaper/Scheduler that supports two Shaping elements and two Scheduling elements per LLID for true minimum- and maximum-rate PON scheduling. The Shaper enforces rate and burst size parameters for each LLID, and the Scheduler ensures that the PON bandwidth is divided into the desired proportions. The Shaper supports rates between 256 Kbps and 1 Gbps. The Scheduler is a hierarchical weighted round-robin (HWRR) design, with 8 priority levels and drop-down reservations between priority levels.

A Polling engine in DBA supports Solicited granting. The polling engine allows the user to configure regular report-only grants to each solicited LLID. These grants alert DBA to the presence of ONU data that must be sent upstream. The polling interval is programmable to allow tradeoffs between latency and bandwidth overhead.

A TDM grant engine in DBA generates high-priority grants at regular intervals. The TDM engine supports 64 channels of TDM grants. Each channel can be assigned to an LLID and is programmable for grant length and grant interval.

EPON uses a nominal PON loop time of 250us. The TK3723 DBA supports loop times between 150us and 750us.

1.4 IEEE 802.3z Gigabit Ethernet MACs

The two IEEE 802.3z Gigabit Ethernet MACs make up the Network-side interface of the TK3723. They support full duplex operation at 100 or 1000 Mbps, auto-negotiation and 802.3x Flow Control.

The Gigabit MACs connect to external 100/1000 Mbps Ethernet PHY devices via GMII or TBI.

The Gigabit MACs collect statistics to support RMON Level 2 requirements.

1.5 Lookup Engines (LUEs)

The Lookup Engines (LUEs) are used to modify frames and switch frames between queues, LLIDs, and VLANs. The LUEs support static bridging, learning bridging, and VLAN bridging architectures. A total of 16K MAC addresses are supported.

When configured for static bridging in the downstream direction, MAC addresses can be mapped to the 256 possible LLIDs. Additional packet fields, such as IP DiffServ and protocol, can be used to separate traffic into different LLIDs or queues. In this configuration, the Ethernet LUE would be configured only to parse OAM traffic to the ARM processor.

When configured for learning bridging, the downstream EPON LUEs look up a frames Destination Address (DA) in the MAC Address table. They then set a destination for the frame. Along with lookups on other fields, the destination lookup results in determining a queue and an LLID for the frame. In upstream bridging mode, the LUEs search for an SA. If the SA is not found, it is added to the MAC address table. The new Address allows downstream frames (with a DA matching the recently learned SA) to be forwarded to the appropriate LLID. Address aging times can be provisioned through the Host Interface. They can take on values of the form 2^N * 8.75ms for N from 0 to 15, and are accurate to within 12.5% of the provisioned value.

When configured for VLAN bridging, the downstream EPON Lookup Engines map the VLAN tag to an LLID and a downstream queue. The VLAN tag is removed from the packet before being queued for the downstream. The upstream engine maps the upstream LLID to a VLAN tag. The LLID is removed and the appropriate VLAN tag is inserted.

The Lookup Engines process all frames at full line rate, including continuous minimum-sized frames. The LUE tables are stored in dedicated internal SRAM.




1.6 Packet Buffering (FIFOs)

External DDRII DRAM memory is used for packet buffering (FIFOs). The TK3723 supports 2048 packet FIFOs, 512 to each of the four FIFO destinations (2 EPON interfaces, 2 Gigabit Ethernet interfaces). Each FIFO has a programmable size up to 1 MB, with a granularity of 4 KB.

Packets are stored in two banks of DDRII DRAM memory. Each port (channel) uses two 512 Mbit, 16-bit-wide DDRII DRAM chips to implement a 32-bit wide, 128 MB memory array. DDRII DRAM memories are clocked at 125MHz. Both DDRII DRAM memory chips forming a single 32-bit wide data bus must have identical AC characteristics. Each DDRII DRAM memory chip must support following features/parameters:

32M x 16-bit capacity (512Mb, 2 per port) Operating Frequency = 125MHz (DDR) Burst Type = Sequential Burst Length = 8 CAS Latency (CL) = 3 Write Recovery (WR) = 2 Additive CAS Latency (AL) = 0 On-Die Termination (ODT) = 75 tAC = +/-800ps tRCD = 16ns tRP = 16ns tRC = 60ns tRFC = 105ns Refresh Rate = 7.8125us (8192 refresh cycles every 64ms; commercial).

1.6.1 DDRII Interfaces PCB Layout Guidelines

TK3723

Cha

nnel

2

Cha

nnel

1

VTT = 0.9V

DDR2_P1_A[12..0]/BA[2..0]

DDRII(port 1, chip 0)

DDR2_P1_DQ1_[15..0]

DDR2_P1_CLK0_P/N

DDR2_P1_RAS/CAS/CS/WE_N

VTT

50(4x)

VTT

50(2x)

DDRII(port 1, chip 1) DDR2_P1_CLK1_P/N

DDR2_P1_DQ0_[15..0]

VTT

50(2x)

DDR2_P1_ODT/CKE

DDR2_P1_U/LDQS0_P/N

DDR2_P1_U/LDQS1_P/N

must be 40mm longer than DDR2_P1_CLK1_P/N


DDR2_P2_A[12..0]/BA[2..0]

DDRII(port 2, chip 0)

DDR2_P2_DQ1_[15..0]

DDR2_P2_CLK0_P/N

DDR2_P2_RAS/CAS/CS/WE_N

VTT

50(4x)

VTT

50(2x)

DDRII(port 2, chip 1)DDR2_P2_CLK1_P/N

DDR2_P2_DQ0_[15..0]

VTT

50(2x)

DDR2_P2_ODT/CKE

DDR2_P2_U/LDQS0_P/N

DDR2_P2_U/LDQS1_P/N



VTT

50(16x)

VTT

50(16x)

separate bias resistors for CLK signals

separate bias resistors for CLK signals

differential pairs (Zdiff = 80)single-ended signals (Zo = 50)

4.7K(2x)

4.7K(2x)

Figure 12. TK3723 DDRII Interfaces

Following are PCB layout guidelines for DDRII interfaces (applicable to each port x independently):

Single-ended DDR2_Px_DQ0/1_[15..0] data signals should be matched in length to +/-5mm and be shorter than 50mm (per port i.e. to both memory chips)

Differential DDR2_Px_CLK0/1_P/N signal should be matched within the differential pair to +/-1mm, and should be matched in length with DDR2_Px_DQ0/1_[15..0] (max 50mm; +/-5mm)




All DDR2_Px_U/LDQS0/1_P/N strobe signals should be matched within the differential pair to +/-1mm and must be longer by 40mm than corresponding DDR2_Px_CLK0/1_P/N clock signals pairs (see Table 34 for AC timing details)

DDR2_Px_A[12..0], DDR2_Px_BA[1..0], DDR2_Px_CS_N, DDR2_Px_WE_N, DDR2_Px_RAS_N, DDR2_Px_CAS_N, DDR2_Px_L/UDM0/1 signals should be matched in length to +/-5mm and be shorter than 75mm

All DDRII signals must be impedance controlled. Single-ended signals must have impedance of 50 (+/-10%), and differential signals 80 (+/-10%). Differential signals are recommended to be loosely coupled to prevent excessive impedance variations due to PCB manufacturing variability

Use biasing/termination and decoupling methods as implemented on Teknovus TK3723 evaluation boards.

1.7 Shapers/Schedulers

The Shaper/Scheduler blocks schedule traffic as follows:

Downstream from the FIFO queues to the EPON MACs (EPON Shapers/Schedulers) Upstream from the FIFO queues to the Network-side Gigabit Ethernet MACs (Ethernet

Shapers/Schedulers).

Each Shaper/Scheduler supports two Shaping elements and two Scheduling elements per FIFO queue, for true minimum and maximum-rate scheduling.

The Shaper enforces rate and burst-size parameters for each FIFO. Rates are configurable per-queue between 256 Kbps and 1 Gbps. Burst sizes are set in 1 KB increments between 1 KB and 256 KB.

The Scheduler ensures that the channel bandwidth is divided into the desired proportions. The Scheduler is a hierarchical weighted round-robin (HWRR) design, with 8 priority levels and drop-down reservations between priority levels. Scheduling weights have a range of 1 to 255.

In addition to the per-Queue shaper/scheduler function, the Shaper/Scheduler blocks contain per-Priority and Aggregate shapers. The per-Priority shaper allows shaping control of all FIFOs assigned to a given Priority level. The Aggregate shaper allows shaping of the final, summed output of each Shaper/Scheduler block.

1.8 ARM9 Processor Subsystem

The ARM9 processor is responsible for running Teknovus OLT firmware. The ARM9 processor subsystem consists of an embedded ARM946E processor running at 125MHz, plus:

8KB Data Cache 8KB Instruction Cache Memory Controller (interface to external 32-bit wide SDRAM and 16-bit wide FLASH) Watchdog timer Four general-purpose timers UART.




The ARM9 processor requires external FLASH (static memory) and SDRAM (dynamic memory) connected via the 32-bit wide memory interface. It requires 32 MB (8M x 32-bits, or 2 x 8M x 16-bits) of SDRAM memory and 8 MB (4M x 16-bits) of FLASH memory.

Teknovus firmware and the OLT configuration data are stored in the FLASH. At boot time the ARM9 copies its firmware program and OLT configuration data from the FLASH and stores in the SDRAM. After boot the ARM9 runs its program using the SDRAM memory.

The SDRAM memory is clocked at 125MHz and must have access time of less than 5.5ns with CAS Latency of 3 (CL=3). PC133 compliant SDRAM memory can work in this application.

The SDRAM memory must support following features/parameters:

256Mb capacity (8M x 32-bit, or 2 x (8M x 16-bit)) Operating Frequency = 125MHz Burst Type = Sequential Burst Length = 8 CAS Latency (CL) = 3 Write Recovery (WR) = 2 tAC = 5.5ns tRAS = 56ns tRCD = 24ns tRP = 24ns tRC = 72ns tRFC = 72ns Refresh Rate = 7.8125us (8192 refresh cycles every 64ms).

The following 256 Mb SDRAM memories are suitable for TK3723 ARM9 application:

ISSI: o IS42S32800B-(6)/(7)B(A)(L)(I) o IS45S32800B-7B(L)(A)(1)

Hynix: o HY5V52A(L)F(P)-(6)/(H) o HY5V52E(L)M(P)-(6)/(H) o HY5V52AEMP-(6)/(H)

Micron: o MT48LC8M32B2(F)/(B)5-6.

32-bit wide SDRAM memories are recommended in this application. Using two 16-bit wide SDRAM devices is possible, but requires careful PCB layout and SDRAM selection (see Section 1.8.2 for more details). Both 16-bit wide SDRAM memory chips forming a single 32-bit wide data bus must have identical AC characteristics.

The firmware requires the use of FLASH memory which supports either an AMD or Intel command set for erasing and programming. The FLASH must have the following features:

4M x 16-bit capacity (64 Mb) 64KB or 128KB sector size (128KB sector size requires CFI-compatible command set) AMD or Intel style programming commands Read Access time of 84 ns or faster.

The following 64 Mb FLASH memories are confirmed to work properly and are currently supported by Teknovus firmware:

MX29LV640DB (Macronix)




S29JL064H (Spansion) (TE)/(JS)/(RC)28F640J3D (Intel/Numonyx) M29W640GB (ST Micro) [TBD].

MC_A[0] of the ARM9 processor address bus needs to connect to the Word address of the Flash memory i.e. MC_A[0] is a Word address (not Byte select).

1.8.1 FLASH Interface PCB Layout Guidelines Following are PCB layout guidelines for ARM9 FLASH memory:

All FLASH signals should be matched in length to +/-10mm and be shorter than 75mm MC_STC_SYNCOUT output must be connected via 33 series termination resistor to the

MC_STC_SYNCIN input with a trace of total length matching FLASH other signals length to +/-10mm All FLASH signals must be impedance controlled and have impedance of 50 (+/-10%) Use termination and decoupling methods as implemented on Teknovus TK3723 evaluation boards.

1.8.2 SDRAM Interface PCB Layout Guidelines Following are PCB layout guidelines for ARM9 SDRAM memory:

MC_DYN_CLK signal must be shorter than 50mm and be loaded with less than 15pF total (including TK3723 load)

MC_DYN_SYNCOUT output must be connected via 33 series termination resistor to the MC_DYN_SYNCIN input with a trace of total length equal or longer by no more than 25mm than MC_DYN_CLK signal

All other SDRAM signals should be matched in length to +/-10mm and be shorter than 75mm All SDRAM signals must be impedance controlled and have impedance of 50 (+/-10%) Use termination and decoupling methods as implemented on Teknovus TK3723 evaluation boards.

With a careful PCB layout and the SDRAM selection, it is possible to use 2 16-bit wide SDRAM memories in this application. Since in such configuration the MC_DYN_CLK signal must be shared between two SDRAM devices, and the total capacitive loading on this signal is still limited to 15pF, the MC_DYN_CLK trace length must be controlled to allow following capacitance:

CTRACE 15pF - CPACKAGE - 2*(CCLK)

where:

CTRACE is total MC_DYN_CLK trace capacitance (must be calculated; usually about 2.5~3.5pF/inch) CPACKAGE is TK3723 pin package capacitance = 2.0pF CCLK is SDRAM memory clock input pin capacitance (from SDRAM vendors data sheet; usually about

3~4pF).

To help limit the CTRACE capacitance, installing the 2 SDRAMs on opposite sides of the PCB should be considered.

1.9 Host Interfaces

Two physical interfaces can be used by the host system to communicate with the TK3723 ARM9 processor:




MII-based 10/100 Mbps Ethernet CRAFT port connected internally to the management FIFO. This port provides a message-based interface to pass management, control and statistics information. The 10/100 Ethernet port can layer the management and statistics interface on UDP/IP, TCP/IP or Ethernet Layer 2.

Asynchronous Parallel Bus internally connected to the management FIFO. This interface is meant for interfacing a generic external host processor. The host processor may reside on the line-card with the TK3723, or it may reside beyond a backplane interface on a separate controller card.

Additionally, for system development and debug purposes, a hyper-terminal can be connected to the ARM9 via the UART interface for Command Line Interface (CLI) access.

Both Ethernet-based and asynchronous parallel bus-based management interfaces are common backplane architectures. Both are supported by the TK3723. However, since both interfaces share the same buffer RAM memory, only one interface can be used at a time.

The mailbox interface is accessed through the Asynchronous Bus Interface and the 10/100 Ethernet CRAFT Port. It provides two different physical layers to carry the same messages to the firmware. The Asynchronous Bus requires less processing, since it does not go through a UDP/IP stack. Overhead requirements are insignificant, since bandwidth requirements are fairly low.

The Asynchronous Parallel Bus Interface allows an external host to access the ARM9 processor. This 16-bit wide, mailbox-based interface is memory-mapped. It allows single-word and double-word read/write cycles.

The 16-bit Asynchronous Bus interface is of little endian format; AB_D[0] is the least significant bit of the data bus. As a 16-bit interface, AB_A[0] addresses the even/odd word (16-bits). It is the least significant bit of the address bus. Byte access is not supported. The interface provides 11 bits of addressing. Hence, 4 Kbytes (2K x 16-bits) of address space is provided.

To connect the Asynchronous Bus to a Motorola PowerPC processors 60x bus (e.g. MPC8270VR), the following interconnect is recommended:

AB_A[10:0] 60x_A[20:30] AB_D[15:0] 60x_D[0:15].

Note: AB_A[0] and 60x_A[31] bits are LSB, and AB_D[15] and 60x_D[0] bits are MSB.

The mailbox interface allows the host and the TK3723 processor to enqueue management messages for the peer processor. There are two queues in the mailbox. One queue is for messages from the Host to the ARM9 processor. The other queue is for messages from the ARM to the Host. For each message, an interrupt is generated for the destination processor. This interrupt indicates the presence of a message which needs to be processed. Figure 11 shows the internal blocks of the TK3723 and the external Host interface.




FIFOManager

TK3723 chip

Host System

InterruptController

32

TK3723Core

ARM 9Processor

AMBA-AHB

16

16

32

Asynchronous Bus

MemoryController

MII(CRAFT)

Figure 13. TK3723 Host Interfaces

1.10 GPIO Interface

32 GPIO pins are provided in the TK3723. These are programmable via the TK3723 Host Interface Software. These pins can be programmed as inputs or outputs. Refer to Figure 12.

Note: Teknovus does not recommend sinking or sourcing more than 8mA on any GPIO pin.




Figure 14. Simplified GPIO Pin Block Diagram

1.11 UART Interface

The TK3723 provides one UART interface. The UART enables debugging, and provides command line access to the Host Interface Software. The baud rate is generated from the 125.00MHz reference oscillator. An external RS-232 buffer, such as the Maxim MAX3222E, can be used to connect to a standard RS-232 connector. The Teknovus Host Interface software default line settings are as follows. Refer to Figure 13. .

Baud Rate 9600 No-Parity 8 bit Data 1 Stop bit

The first pin, UART_DOUT, refers to UART transmit data (output) from the TK3723. The second pin, UART_DIN, refers to UART receive data (input) to the TK3723. The UART interface is asynchronous; it does not include any clock.

Figure 15. UART Interface Timing




1.12 Ethernet Serial Management Interface

The Ethernet serial management interface (MDIO) consists of a data interface, basic register set, and a serial management interface to the register set. This interface is used to control and configure multiple PHY devices, gather status and error information, and determine the type and capabilities of the attached PHY devices.

Figure 16. MDIO Serial Management Read and Write Timing

1.13 JTAG and Test Interfaces

A standard five-port JTAG interface is provided for in-circuit testing. During normal TK3723 operation JTAG is not functional and all JTAG pins except TRST_N should be pulled high. The TRST_N pin should be pulled low during normal OLT operation. Please contact Teknovus for programming details.

The TK3723 implements a 4-bit instruction register that supports IEEE 1149.1 mandatory instructions BYPASS, EXTEST and SAMPLE/PRELOAD. In addition, IDCODE and CLAMP instructions are supported. Teknovus also supports reading the chip identity and the manufacturers identity using the JTAG interface. The following table shows the supported instructions and their operation codes.

Table 2. JTAG Instructions

Code Instruction Selected Register

Result

0000 EXTEST BSR Outputs cells apply their values to ports. Input cells sample values on ports

0100 IDCODE DEVICE IDENTITY

Captures 32-bit Identity with following fields:

Bits Field Decimal Hex

0 Default Value 1 0x1 1:11 Teknovus Identity 515 0x203 12:27 Part Number 3723 0x0E8B 28:31 Part Version 2 0x0010

0010 SAMPLE/ PRELOAD BSR Sets up the boundary scan cells to either sample values moving in or out of devices, or preload known values in Boundary Scan cells prior to next operation to be performed.

0011 CLAMP BSR + BYPASS First preset values in output cells are taken to output ports, then BYPASS register is selected between TDI and TDO pins.




Code Instruction Selected Result Register

1111 BYPASS BYPASS TDO gets value of TDI on clock, all logic is bypassed.

Figure 15. shows the DEVICE IDENTITY register fields. Bit 0 of the 32-bit register is always 1.

Part Number0x0E8B (3723)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 10 1 10 1 1 1 11 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 1

Teknovus JEDEC Identity 0x203

Version0x0010

Figure 17. DEVICE IDENTITY Register Fields




2 TK3723 Signals Description

2.1 Signals Types

Signal Type Type Description

I* CMOS Input

O* CMOS Output

I/O* CMOS Input/Output

OD* CMOS Open-Drain Output

O18 SSTL-18 Output

I/O18 SSTL-18 Input/Output

P Power

AP Analog Power

NC No Connect

* All CMOS signals contain internal pull-up resistors. Internal pull-up resistor values range between 39K-85K.

2.2 Signals Names Description

Table 3. ARM9 Processor Bus Interface

Ball Signal Name Type Signal Description

B4 ARM_TCK I ARM JTAG Test Clock Input. Leave unconnected (NC) for normal operation

D6 ARM_TMS I ARM JTAG Test Mode Select Input. Leave unconnected (NC) for normal operation

E7 ARM_TDI I ARM JTAG Test Data Input. Leave unconnected (NC) for normal operation

E6 ARM_TDO O ARM JTAG Test Data Output

C4 ARM_TRSTN I ARM JTAG Test Reset Input (active low). Pull-down with 1K-4.7Kohm resistor to disable JTAG functionality

C6 EXT_PROC_N I External Processor Enable (active low). Pull up for normal operation

AH4 ARM_TM_N I ARM Processor Test Mode Select (active low). Pull up for normal operation

D7 UART_DIN I ARM Processor UART Serial Data Input

E8 UART_DOUT O ARM Processor UART Serial Data Output

AF6 ARM_WDOUT_N OD ARM Processor Watchdog Timer Output (open-drain, active low). Pull-up with 1K-4.7Kohms resistor and connect to either the RST_N input directly, or to the board RESET chip input that produces RST_N signal

B5 ARM_INT_N I/O This is a dual function pin (EXT_PROC_N dependant):

Internal ARM9 Processor Interrupt Input (active low) External Processor Interrupt Output (active low)





AK1 ARM_RST_N I ARM Processor Reset Input (active low). Pull up for normal operation

AJ2 MC_D31 I/O Memory Controller Data [31]

AG4 MC_D30 I/O Memory Controller Data [30]

AE6 MC_D29 I/O Memory Controller Data [29]

AF5 MC_D28 I/O Memory Controller Data [28]

AJ1 MC_D27 I/O Memory Controller Data [27]

AH2 MC_D26 I/O Memory Controller Data [26]




AD6 MC_D22 I/O Memory Controller Data [22]

AH1 MC_D21 I/O Memory Controller Data [21]









AC5 MC_D12 I/O Memory Controller Data [12]





AB5 MC_D7 I/O Memory Controller Data [7]






AA5 MC_D1 I/O Memory Controller Data [1]






AC1 MC_A26 I/O Memory Controller Address [26]

AA4 MC_A25 I/O Memory Controller Address [25]

AB2 MC_A24 I/O Memory Controller Address [24]

AB1 MC_A23 I/O Memory Controller Address [23]

Y5 MC_A22 I/O Memory Controller Address [22]





W5 MC_A17 I/O Memory Controller Address [17]







AG5 MC_DYN_A10 I/O Memory Controller Dynamic Address [10] / Auto-Precharge Control

V5 MC_STC_A10 I/O Memory Controller Static Address [10]

V4 MC_A9 I/O Memory Controller Address [9]




U5 MC_A5 I/O Memory Controller Address [5]





T2 MC_A0 I/O Memory Controller Address [0]. This is the FLASH memory Word address (not Byte select), and the SDRAM Byte select.

T5 MC_STC_SYNCOUT O Memory Controller Static Sync Output. Connect to MC_STC_SYNCIN via 33 resistor

T3 MC_STC_SYNCIN I Memory Controller Static Sync Input

E5 MC_STC_CLK O Memory Controller Static Clock Output

P5 MC_STC_CS3_N O Memory Controller Static Chip [3] Select (active low)





N1 MC_STC_CS2_N O Memory Controller Static Chip [2] Select (active low)

N2 MC_STC_CS1_N I TK3723 Chip Select (active low). Leave unconnected (NC) for normal operation

N3 MC_STC_CS0_N O Memory Controller Static Chip [0] Select (active low). This is the internal ARM9 boot memory (FLASH) Chip Select (required)

R5 MC_STC_WE_N I/O Memory Controller Static Write Enable (active low)

R2 MC_STC_OE_N I/O Memory Controller Static Output Enable (active low)

L2 MC_STC_BSEL3_N O Memory Controller Static Byte [3] Select (active low)

M5 MC_STC_BSEL2_N O Memory Controller Static Byte [2] Select (active low)

K1 MC_STC_BSEL1_N O Memory Controller Static Byte [1] Select (active low)

K2 MC_STC_BSEL0_N O Memory Controller Static Byte [0] Select (active low)

J1 MC_DYN_SYNCOUT* O Memory Controller Dynamic Sync Output. Connect to MC_DYN_SYNCIN via 33 resistor

L4 MC_DYN_SYNCIN* I Memory Controller Dynamic Sync Input

AJ3 MC_DYN_CLK* O Memory Controller Dynamic Clock Output

M2 MC_DYN_CLKEN O Memory Controller Dynamic Clock Enable

P1 MC_DYN_CS3_N O Memory Controller Dynamic Chip [3] Select (active low)



P4 MC_DYN_CS0_N O Memory Controller Dynamic Chip [0] Select (active low). This is the internal ARM9 program memory (SDRAM) Chips Select (required)

R4 MC_DYN_WE_N I/O Memory Controller Dynamic Write Enable (active low)

N4 MC_DYN_RAS_N O Memory Controller Dynamic Row Address Select (active low)

M1 MC_DYN_CAS_N O Memory Controller Dynamic Column Address Select (active low)

T1 MC_DYN_BA1 O Memory Controller Dynamic Bank Address Select [1]

R1 MC_DYN_BA0 O Memory Controller Dynamic Bank Address Select [0]

N5 MC_DYN_DQM3 O Memory Controller Dynamic Data Mask [3] for R/W Access

M3 MC_DYN_DQM2 O Memory Controller Dynamic Data Mask [2] for R/W Access

L1 MC_DYN_DQM1 O Memory Controller Dynamic Data Mask [1] for R/W Access

M4 MC_DYN_DQM0 O Memory Controller Dynamic Data Mask [0] for R/W Access

* Refer to Section 1.8.2 for length restrictions for these signals.

Table 4. Inter-Processor Asynchronous Bus Interface


AL31 AB_CS_N I* Asynchronous Bus Chip Select (active low)





AK30 AB_WE_N I Asynchronous Bus Write Enable (active low)

AL32 AB_OE_N I Asynchronous Bus Output Enable (Read Enable) (active low)

AJ29 AB_INT_N O Asynchronous Bus Interrupt (active low)

AM32 AB_A10 I Asynchronous Bus Address [10]

AK29 AB_A9 I Asynchronous Bus Address [9]

AL30 AB_A8 I Asynchronous Bus Address [8]


AN32 AB_A6 I Asynchronous Bus Address [6]



AN31 AB_A3 I Asynchronous Bus Address [3]




AJ33 AB_D15 I/O Asynchronous Bus Data [15]

AK34 AB_D14 I/O Asynchronous Bus Data [14]

AF29 AB_D13 I/O Asynchronous Bus Data [13]

AG30 AB_D12 I/O Asynchronous Bus Data [12]

AH31 AB_D11 I/O Asynchronous Bus Data [11]



AL34 AB_D8 I/O Asynchronous Bus Data [8]

AG29 AB_D7 I/O Asynchronous Bus Data [7]




AL33 AB_D3 I/O Asynchronous Bus Data [3]




* Pull up when not used.

Table 5. Ethernet Serial Management Interface





AK11 MDIO_DATA I/O Management Serial Data I/O. I/O data for PHY(s) registers access

AN9 MDIO_CLK O Management Serial Data Clock. Clock for PHY(s) registers access

Table 6. Management Port (CRAFT) MII Interface


AP5 MII_RXD0 I Receive Data [0] from PHY

AN6 MII_RXD1 I Receive Data [1] from PHY

AM7 MII_RXD2 I Receive Data [2] from PHY

AK9 MII_RXD3 I Receive Data [3] from PHY

AK8 MII_RXDV I Receive Data Valid from PHY

AL7 MII_RXER I Receive Error from PHY

AP6 MII_RXCLK I* 25MHz/2.5MHz Receive Clock from PHY

AN7 MII_TXD0 O Transmit Data [0] to PHY

AM8 MII_TXD1 O Transmit Data [1] to PHY

AK10 MII_TXD2 O Transmit Data [2] to PHY

AN8 MII_TXD3 O Transmit Data [3] to PHY

AM9 MII_TXEN O Transmit Data Enable to PHY

AL10 MII_TXER O Transmit Error to PHY

AL8 MII_TXCLK I* 25MHz/2.5MHz Transmit Clock from PHY

* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other MII pins unconnected (NC).

Table 7. Local-Side PHY/SerDes MII/GMII/TBI Interface - Port 1

Note: Data flows are named Downstream (DN) or Upstream (UP), relative to the EPON fiber.


AK2 LOC_P1_DNRBC0 I* This is a triple function pin:

MII: 25.0MHz Receive Clock. Generated by PHY to clock-in LOC_P1_DND[3:0], LOC_P1_DNER, and LOC_P1_DNEN

GMII: 125MHz Receive Clock. Generated by PHY to clock-in LOC_P1_DND[7:0], LOC_P1_DNER, and LOC_P1_DNEN

TBI: 62.5MHz Receive RBC0 Clock. Generated by SerDes to clock-in LOC_P1_DND[9:0] (odd code)

AL2 LOC_P1_DNRBC1 I* This is a triple function pin:

MII: 25.0MHz Transmit Clock. Generated by PHY to clock-out LOC_P1_UPD[3:0], LOC_P1_UPER, and LOC_P1_UPDV

TBI: 62.5MHz Receive RBC1 Clock. Generated by SerDes to clock-in LOC_P1_DND[9:0] (even code)

GMII: unused; pull down with 1K- 4.7Kohm resistor





AM2 LOC_P1_DNER / LOC_P1_DND9

I This is a dual function pin:

GMII/MII: Downstream Receive Data Error TBI: Downstream Receive Data [9]

AJ6 LOC_P1_DNEN / LOC_P1_DND8

I This is a dual function pin:

GMII/MII: Downstream Receive Data Enable TBI: Downstream Receive Data [8]

AK5 LOC_P1_DND7 I This is a dual function pin:

TBI/GMII: Downstream Receive Data [7] MII: unused; leave unconnected (NC)

AH6 LOC_P1_DND6 I This is a dual function pin:


AJ5 LOC_P1_DND5 I This is a dual function pin:


AK4 LOC_P1_DND4 I This is a dual function pin:


AJ4 LOC_P1_DND3 I MII/GMII/TBI: Downstream Receive Data [3]

AG6 LOC_P1_DND2 I MII/GMII/TBI: Downstream Receive Data [2]

AH5 LOC_P1_DND1 I MII/GMII/TBI: Downstream Receive Data [1]

AK3 LOC_P1_DND0 I MII/GMII/TBI: Downstream Receive Data [0]

AL4 LOC_P1_DNCOMDET I This is a dual function pin:

TBI (MAC mode): Downstream Receive Comma Character Detect MII/GMII: unused; leave unconnected (NC)

AM3 LOC_P1_UPCLK O This is a triple function pin:

GMII: 125MHz Transmit Clock. Used by Gigabit PHY for clocking-in LOC_P1_UPD[7:0], LOC_P1_UPER, and LOC_P1_UPEN

TBI: 125MHz Transmit/Reference Clock. Used by SerDes for clocking-in LOC_P1_UPD[9:0]

MII: unused; leave unconnected (NC) AM6 LOC_P1_UPER /

LOC_P1_UPD9 O This is a dual function pin:

GMII/MII: Upstream Data Error TBI: Upstream Transmit Data [9]

AN5 LOC_P1_UPDV / LOC_P1_UPD8

O This is a dual function pin:

GMII/MII: Upstream Transmit Data Valid TBI: Upstream Transmit Data [8]

AP4 LOC_P1_UPD7 O This is a dual function pin:

TBI/GMII: Upstream Transmit Data [7] MII: unused; leave unconnected (NC)

AK7 LOC_P1_UPD6 O This is a dual function pin:






AL6 LOC_P1_UPD5 O This is a dual function pin:


AN4 LOC_P1_UPD4 O This is a dual function pin:


AN3 LOC_P1_UPD3 O MII/GMII/TBI: Upstream Transmit Data [3]

AM4 LOC_P1_UPD2 O MII/GMII/TBI: Upstream Transmit Data [2]

AL5 LOC_P1_UPD1 O MII/GMII/TBI: Upstream Transmit Data [1]

AK6 LOC_P1_UPD0 O MII/GMII/TBI: Upstream Transmit Data [0]

* When not used, pull down both clock inputs with the 1K-4.7Kohm resistors, and leave all other LOC_P1 pins unconnected (NC).

Table 8. Plant-Side SerDes Interface Port 1


AC32 PLA_P1_UPD9 I TBI Receive Data [9] from Plant-Side SerDes

AB30 PLA_P1_UPD8 I TBI Receive Data [8] from Plant-Side SerDes

AD33 PLA_P1_UPD7 I TBI Receive Data [7] from Plant-Side SerDes


AE34 PLA_P1_UPD5 I TBI Receive Data [5] from Plant-Side SerDes


AF34 PLA_P1_UPD3 I TBI Receive Data [3] from Plant-Side SerDes


AD31 PLA_P1_UPD1 I TBI Receive Data [1] from Plant-Side SerDes


AD34 PLA_P1_UPRBC0 I* 125MHz/62.5MHz TBI Receive Clock from Plant-Side SerDes

AB31 PLA_P1_UPRBC1 I* 62.5MHz TBI Receive Clock from Plant-Side SerDes

AC33 PLA_P1_UPSIGDET I Signal Detect from Plant-Side SerDes (optional; not used in EPON application), leave unconnected (NC) if not used

V31 PLA_P1_DND19 O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: unused; leave unconnected (NC) 20 bit mode (2xTBI): upper-order 10B code bit [9] to Plant-Side SerDes

In 1.25 Gbps mode this is a dual function pin:

8+1 bit mode: unused; leave unconnected (NC) 10 bit mode (TBI): duplicate PLA_P1_DND9 signal





V30 PLA_P1_DND18 O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: unused; leave unconnected (NC) 20 bit mode (2xTBI): upper-order 10B code bit [8] to Plant-Side SerDes


8+1 bit mode: unused; leave unconnected (NC) 10 bit mode (TBI): duplicate PLA_P1_DND8 signal

W34 PLA_P1_DND17 / PLA_P1_KMSB

O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: K-code indicator for upper-order byte (PLA_P1_DND[15..8]) to Plant-Side SerDes

20 bit mode (2xTBI): upper-order 10B code bit [7] to Plant-Side SerDes In 1.25 Gbps mode this is a dual function pin:

8+1 bit mode: duplicate PLA_P1_DND16 signal 10 bit mode (TBI): duplicate PLA_P1_DND7 signal

W33 PLA_P1_DND16 / PLA_P1_KLSB

O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: K-code indicator for lower-order byte (PLA_P1_DND[7..0]) to Plant-Side SerDes

20 bit mode (2xTBI): upper-order 10B code bit [6] to Plant-Side SerDes In 1.25 Gbps mode this is a dual function pin:

8+1 bit mode: K-code indicator for lower-order byte (PLA_P1_DND[7..0]) to Plant-Side SerDes

10 bit mode (TBI): duplicate PLA_P1_DND6 signal W32 PLA_P1_DND15 O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: upper-order data/K-code byte bit [7] to Plant-Side SerDes 20 bit mode (2xTBI): upper-order 10B code bit [5] to Plant-Side SerDes



W31 PLA_P1_DND14 O In 2.5 Gbps mode this is a dual function pin:




Y34 PLA_P1_DND13 O In 2.5 Gbps mode this is a dual function pin:




W30 PLA_P1_DND12 O In 2.5 Gbps mode this is a dual function pin:












AA34 PLA_P1_DND10 O In 2.5 Gbps mode this is a dual function pin:





16+2 bit mode: upper-order data/K-code byte bit [1] to Plant-Side SerDes 20 bit mode (2xTBI): lower-order 10B code bit [9] to Plant-Side SerDes

In 1.25Gbsp mode this is a dual function pin:

8+1 bit mode: duplicate PLA_P1_DND1 signal 10 bit mode (TBI): 10B code bit [9] to Plant-Side SerDes

AA33 PLA_P1_DND8 O In 2.5 Gbps mode this is a dual function pin:

16+2 bit mode: upper-order data/K-code byte bit [0] to Plant-Side SerDes 20 bit mode (2xTBI): lower-order 10B code bit [8] to Plant-Side SerDes


8+1 bit mode: duplicate PLA_P1_DND0 signal 10 bit mode (TBI): 10B code bit [8] to Plant-Side SerDes


16+2 bit mode: lower-order data/K-code byte bit [7] to Plant-Side SerDes 20 bit mode (2xTBI): lower-order 10B code bit [7] to Plant-Side SerDes

In 1.25Gbsp mode this is a dual fun

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