Tiva C Series TM4C1297NCZAD Microcontroller Data Sheet · 2014. 2. 25. · 9 MicroDirectMemoryAccess(μDMA).....667 9.1 BlockDiagram.....668 9.2 FunctionalDescription.....668

Tiva™ TM4C1297NCZAD Microcontroller

DATA SHEET

Copyr ight © 2007-2013Texas Instruments Incorporated

DS-TM4C1297NCZAD-15638.2711SPMS435

TEXAS INSTRUMENTS-ADVANCE INFORMATION

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December 12, 20132Texas Instruments-Advance Information

http://www.ti.com/tm4chttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 43About This Document .................................................................................................................... 44Audience .............................................................................................................................................. 44About This Manual ................................................................................................................................ 44Related Documents ............................................................................................................................... 44Documentation Conventions .................................................................................................................. 45

1 Architectural Overview .......................................................................................... 471.1 Tiva™ C Series Overview .............................................................................................. 471.2 TM4C1297NCZAD Microcontroller Overview .................................................................. 481.3 TM4C1297NCZAD Microcontroller Features ................................................................... 511.3.1 ARM Cortex-M4F Processor Core .................................................................................. 511.3.2 On-Chip Memory ........................................................................................................... 531.3.3 External Peripheral Interface ......................................................................................... 551.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 571.3.5 Serial Communications Peripherals ................................................................................ 571.3.6 System Integration ........................................................................................................ 621.3.7 Advanced Motion Control ............................................................................................... 691.3.8 Analog .......................................................................................................................... 711.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 731.3.10 Packaging and Temperature .......................................................................................... 741.4 TM4C1297NCZAD Microcontroller Hardware Details ....................................................... 741.5 Kits .............................................................................................................................. 741.6 Support Information ....................................................................................................... 74

2 The Cortex-M4F Processor ................................................................................... 752.1 Block Diagram .............................................................................................................. 762.2 Overview ...................................................................................................................... 772.2.1 System-Level Interface .................................................................................................. 772.2.2 Integrated Configurable Debug ...................................................................................... 772.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 782.2.4 Cortex-M4F System Component Details ......................................................................... 782.3 Programming Model ...................................................................................................... 792.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 792.3.2 Stacks .......................................................................................................................... 802.3.3 Register Map ................................................................................................................ 802.3.4 Register Descriptions .................................................................................................... 822.3.5 Exceptions and Interrupts .............................................................................................. 982.3.6 Data Types ................................................................................................................... 982.4 Memory Model .............................................................................................................. 982.4.1 Memory Regions, Types and Attributes ......................................................................... 1022.4.2 Memory System Ordering of Memory Accesses ............................................................ 1022.4.3 Behavior of Memory Accesses ..................................................................................... 1022.4.4 Software Ordering of Memory Accesses ....................................................................... 1032.4.5 Bit-Banding ................................................................................................................. 1042.4.6 Data Storage .............................................................................................................. 1062.4.7 Synchronization Primitives ........................................................................................... 107

3December 12, 2013Texas Instruments-Advance Information


2.5 Exception Model ......................................................................................................... 1082.5.1 Exception States ......................................................................................................... 1092.5.2 Exception Types .......................................................................................................... 1092.5.3 Exception Handlers ..................................................................................................... 1142.5.4 Vector Table ................................................................................................................ 1142.5.5 Exception Priorities ...................................................................................................... 1152.5.6 Interrupt Priority Grouping ............................................................................................ 1162.5.7 Exception Entry and Return ......................................................................................... 1162.6 Fault Handling ............................................................................................................. 1192.6.1 Fault Types ................................................................................................................. 1202.6.2 Fault Escalation and Hard Faults .................................................................................. 1202.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1212.6.4 Lockup ....................................................................................................................... 1212.7 Power Management .................................................................................................... 1222.7.1 Entering Sleep Modes ................................................................................................. 1222.7.2 Wake Up from Sleep Mode .......................................................................................... 1222.8 Instruction Set Summary .............................................................................................. 123

3 Cortex-M4 Peripherals ......................................................................................... 1303.1 Functional Description ................................................................................................. 1303.1.1 System Timer (SysTick) ............................................................................................... 1313.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1323.1.3 System Control Block (SCB) ........................................................................................ 1333.1.4 Memory Protection Unit (MPU) ..................................................................................... 1333.1.5 Floating-Point Unit (FPU) ............................................................................................. 1383.2 Register Map .............................................................................................................. 1423.3 System Timer (SysTick) Register Descriptions .............................................................. 1453.4 NVIC Register Descriptions .......................................................................................... 1493.5 System Control Block (SCB) Register Descriptions ........................................................ 1593.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1883.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 197

4 JTAG Interface ...................................................................................................... 2034.1 Block Diagram ............................................................................................................ 2044.2 Signal Description ....................................................................................................... 2044.3 Functional Description ................................................................................................. 2054.3.1 JTAG Interface Pins ..................................................................................................... 2054.3.2 JTAG TAP Controller ................................................................................................... 2074.3.3 Shift Registers ............................................................................................................ 2084.3.4 Operational Considerations .......................................................................................... 2084.4 Initialization and Configuration ..................................................................................... 2114.5 Register Descriptions .................................................................................................. 2114.5.1 Instruction Register (IR) ............................................................................................... 2124.5.2 Data Registers ............................................................................................................ 213

5 System Control ..................................................................................................... 2165.1 Signal Description ....................................................................................................... 2165.2 Functional Description ................................................................................................. 2165.2.1 Device Identification .................................................................................................... 2175.2.2 Reset Control .............................................................................................................. 2175.2.3 Non-Maskable Interrupt ............................................................................................... 224


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5.2.4 Power Control ............................................................................................................. 2255.2.5 Clock Control .............................................................................................................. 2265.2.6 System Control ........................................................................................................... 2345.3 Initialization and Configuration ..................................................................................... 2415.4 Register Map .............................................................................................................. 2425.5 System Control Register Descriptions (System Control Offset) ....................................... 249

6 Processor Support and Exception Module ........................................................ 5136.1 Functional Description ................................................................................................. 5136.2 Register Map .............................................................................................................. 5136.3 Register Descriptions .................................................................................................. 513

7 Hibernation Module .............................................................................................. 5217.1 Block Diagram ............................................................................................................ 5237.2 Signal Description ....................................................................................................... 5237.3 Functional Description ................................................................................................. 5247.3.1 Register Access Timing ............................................................................................... 5257.3.2 Hibernation Clock Source ............................................................................................ 5257.3.3 System Implementation ............................................................................................... 5287.3.4 Battery Management ................................................................................................... 5297.3.5 Real-Time Clock .......................................................................................................... 5297.3.6 Tamper ....................................................................................................................... 5327.3.7 Battery-Backed Memory .............................................................................................. 5357.3.8 Power Control Using HIB ............................................................................................. 5357.3.9 Power Control Using VDD3ON Mode ........................................................................... 5367.3.10 Initiating Hibernate ...................................................................................................... 5367.3.11 Waking from Hibernate ................................................................................................ 5367.3.12 Arbitrary Power Removal ............................................................................................. 5377.3.13 Interrupts and Status ................................................................................................... 5387.4 Initialization and Configuration ..................................................................................... 5387.4.1 Initialization ................................................................................................................. 5387.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5397.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5397.4.4 External Wake-Up from Hibernation .............................................................................. 5407.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5417.4.6 Tamper Initialization ..................................................................................................... 5417.5 Register Map .............................................................................................................. 5417.6 Register Descriptions .................................................................................................. 543

8 Internal Memory ................................................................................................... 5908.1 Block Diagram ............................................................................................................ 5908.2 Functional Description ................................................................................................. 5928.2.1 SRAM ........................................................................................................................ 5928.2.2 ROM .......................................................................................................................... 5928.2.3 Flash Memory ............................................................................................................. 5948.2.4 EEPROM .................................................................................................................... 6058.2.5 Bus Matrix Memory Accesses ...................................................................................... 6108.3 Register Map .............................................................................................................. 6118.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6138.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6398.6 Memory Register Descriptions (System Control Offset) .................................................. 656



9 Micro Direct Memory Access (μDMA) ................................................................ 6679.1 Block Diagram ............................................................................................................ 6689.2 Functional Description ................................................................................................. 6689.2.1 Channel Assignments .................................................................................................. 6699.2.2 Priority ........................................................................................................................ 6709.2.3 Arbitration Size ............................................................................................................ 6719.2.4 Request Types ............................................................................................................ 6719.2.5 Channel Configuration ................................................................................................. 6729.2.6 Transfer Modes ........................................................................................................... 6749.2.7 Transfer Size and Increment ........................................................................................ 6829.2.8 Peripheral Interface ..................................................................................................... 6829.2.9 Software Request ........................................................................................................ 6839.2.10 Interrupts and Errors .................................................................................................... 6839.3 Initialization and Configuration ..................................................................................... 6839.3.1 Module Initialization ..................................................................................................... 6839.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6849.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6859.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6879.3.5 Configuring Channel Assignments ................................................................................ 6909.4 Register Map .............................................................................................................. 6909.5 μDMA Channel Control Structure ................................................................................. 6919.6 μDMA Register Descriptions ........................................................................................ 698

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 73110.1 Signal Description ....................................................................................................... 73210.2 Pad Capabilities .......................................................................................................... 73710.3 Functional Description ................................................................................................. 73710.3.1 Data Control ............................................................................................................... 73910.3.2 Interrupt Control .......................................................................................................... 74110.3.3 Mode Control .............................................................................................................. 74210.3.4 Commit Control ........................................................................................................... 74310.3.5 Pad Control ................................................................................................................. 74310.3.6 Identification ............................................................................................................... 74410.4 Initialization and Configuration ..................................................................................... 74410.5 Register Map .............................................................................................................. 74610.6 Register Descriptions .................................................................................................. 749

11 External Peripheral Interface (EPI) ..................................................................... 80611.1 EPI Block Diagram ...................................................................................................... 80711.2 Signal Description ....................................................................................................... 80811.3 Functional Description ................................................................................................. 80911.3.1 Master Access to EPI .................................................................................................. 81011.3.2 Non-Blocking Reads .................................................................................................... 81011.3.3 DMA Operation ........................................................................................................... 81111.4 Initialization and Configuration ..................................................................................... 81211.4.1 EPI Interface Options .................................................................................................. 81311.4.2 SDRAM Mode ............................................................................................................. 81311.4.3 Host Bus Mode ........................................................................................................... 81711.4.4 General-Purpose Mode ............................................................................................... 83811.5 Register Map .............................................................................................................. 845


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11.6 Register Descriptions .................................................................................................. 847

12 Cyclical Redundancy Check (CRC) .................................................................... 93712.1 Functional Description ................................................................................................. 93712.1.1 CRC Support .............................................................................................................. 93712.2 Initialization and Configuration ..................................................................................... 93912.2.1 CRC Initialization and Configuration ............................................................................. 93912.3 Register Map .............................................................................................................. 94012.4 CRC Module Register Descriptions .............................................................................. 940

13 General-Purpose Timers ...................................................................................... 94613.1 Block Diagram ............................................................................................................ 94713.2 Signal Description ....................................................................................................... 94813.3 Functional Description ................................................................................................. 94913.3.1 GPTM Reset Conditions .............................................................................................. 95013.3.2 Timer Clock Source ..................................................................................................... 95013.3.3 Timer Modes ............................................................................................................... 95113.3.4 Wait-for-Trigger Mode .................................................................................................. 96013.3.5 Synchronizing GP Timer Blocks ................................................................................... 96113.3.6 DMA Operation ........................................................................................................... 96213.3.7 ADC Operation ............................................................................................................ 96213.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 96213.4 Initialization and Configuration ..................................................................................... 96313.4.1 One-Shot/Periodic Timer Mode .................................................................................... 96313.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 96413.4.3 Input Edge-Count Mode ............................................................................................... 96413.4.4 Input Edge Time Mode ................................................................................................. 96513.4.5 PWM Mode ................................................................................................................. 96513.5 Register Map .............................................................................................................. 96613.6 Register Descriptions .................................................................................................. 967

14 Watchdog Timers ............................................................................................... 101914.1 Block Diagram ........................................................................................................... 102014.2 Functional Description ............................................................................................... 102014.2.1 Register Access Timing ............................................................................................. 102114.3 Initialization and Configuration .................................................................................... 102114.4 Register Map ............................................................................................................ 102114.5 Register Descriptions ................................................................................................. 1022

15 Analog-to-Digital Converter (ADC) ................................................................... 104415.1 Block Diagram ........................................................................................................... 104515.2 Signal Description ..................................................................................................... 104615.3 Functional Description ............................................................................................... 104715.3.1 Sample Sequencers .................................................................................................. 104815.3.2 Module Control .......................................................................................................... 104815.3.3 Hardware Sample Averaging Circuit ........................................................................... 105415.3.4 Analog-to-Digital Converter ........................................................................................ 105415.3.5 Differential Sampling .................................................................................................. 105715.3.6 Internal Temperature Sensor ...................................................................................... 105915.3.7 Digital Comparator Unit .............................................................................................. 106015.4 Initialization and Configuration .................................................................................... 1064



15.4.1 Module Initialization ................................................................................................... 106415.4.2 Sample Sequencer Configuration ............................................................................... 106515.5 Register Map ............................................................................................................ 106515.6 Register Descriptions ................................................................................................. 1068

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 115316.1 Block Diagram ........................................................................................................... 115416.2 Signal Description ..................................................................................................... 115416.3 Functional Description ............................................................................................... 115616.3.1 Transmit/Receive Logic .............................................................................................. 115716.3.2 Baud-Rate Generation ............................................................................................... 115716.3.3 Data Transmission ..................................................................................................... 115816.3.4 Serial IR (SIR) ........................................................................................................... 115816.3.5 ISO 7816 Support ...................................................................................................... 116016.3.6 Modem Handshake Support ....................................................................................... 116016.3.7 9-Bit UART Mode ...................................................................................................... 116116.3.8 FIFO Operation ......................................................................................................... 116216.3.9 Interrupts .................................................................................................................. 116216.3.10 Loopback Operation .................................................................................................. 116316.3.11 DMA Operation ......................................................................................................... 116316.4 Initialization and Configuration .................................................................................... 116416.5 Register Map ............................................................................................................ 116516.6 Register Descriptions ................................................................................................. 1167

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 121917.1 Block Diagram ........................................................................................................... 121917.2 Signal Description ..................................................................................................... 122017.3 Functional Description ............................................................................................... 122217.3.1 Bit Rate Generation ................................................................................................... 122217.3.2 FIFO Operation ......................................................................................................... 122217.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 122317.3.4 SSInFSS Function ..................................................................................................... 122417.3.5 High Speed Clock Operation ...................................................................................... 122517.3.6 Interrupts .................................................................................................................. 122517.3.7 Frame Formats ......................................................................................................... 122617.3.8 DMA Operation ......................................................................................................... 123317.4 Initialization and Configuration .................................................................................... 123317.4.1 Enhanced Mode Configuration ................................................................................... 123517.5 Register Map ............................................................................................................ 123517.6 Register Descriptions ................................................................................................. 1236

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 126818.1 Block Diagram ........................................................................................................... 126918.2 Signal Description ..................................................................................................... 127018.3 Functional Description ............................................................................................... 127118.3.1 I2C Bus Functional Overview ...................................................................................... 127118.3.2 Available Speed Modes ............................................................................................. 127718.3.3 Interrupts .................................................................................................................. 127918.3.4 Loopback Operation .................................................................................................. 128018.3.5 FIFO and µDMA Operation ........................................................................................ 128018.3.6 Command Sequence Flow Charts .............................................................................. 1282


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18.4 Initialization and Configuration .................................................................................... 129018.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 129018.4.2 Configure the I2C Master to High Speed Mode ............................................................ 129118.5 Register Map ............................................................................................................ 129218.6 Register Descriptions (I2C Master) .............................................................................. 129418.7 Register Descriptions (I2C Slave) ............................................................................... 132318.8 Register Descriptions (I2C Status and Control) ............................................................ 1340

19 Controller Area Network (CAN) Module ........................................................... 134919.1 Block Diagram ........................................................................................................... 135019.2 Signal Description ..................................................................................................... 135019.3 Functional Description ............................................................................................... 135119.3.1 Initialization ............................................................................................................... 135219.3.2 Operation .................................................................................................................. 135219.3.3 Transmitting Message Objects ................................................................................... 135319.3.4 Configuring a Transmit Message Object ...................................................................... 135419.3.5 Updating a Transmit Message Object ......................................................................... 135519.3.6 Accepting Received Message Objects ........................................................................ 135519.3.7 Receiving a Data Frame ............................................................................................ 135619.3.8 Receiving a Remote Frame ........................................................................................ 135619.3.9 Receive/Transmit Priority ........................................................................................... 135719.3.10 Configuring a Receive Message Object ...................................................................... 135719.3.11 Handling of Received Message Objects ...................................................................... 135819.3.12 Handling of Interrupts ................................................................................................ 136019.3.13 Test Mode ................................................................................................................. 136119.3.14 Bit Timing Configuration Error Considerations ............................................................. 136319.3.15 Bit Time and Bit Rate ................................................................................................. 136319.3.16 Calculating the Bit Timing Parameters ........................................................................ 136519.4 Register Map ............................................................................................................ 136819.5 CAN Register Descriptions ......................................................................................... 1369

20 Universal Serial Bus (USB) Controller ............................................................. 140020.1 Block Diagram ........................................................................................................... 140120.2 Signal Description ..................................................................................................... 140120.3 Register Map ............................................................................................................ 1402

21 LCD Controller .................................................................................................... 140921.1 Block Diagram ........................................................................................................... 140921.2 Signal Description ..................................................................................................... 141021.3 Functional Description ............................................................................................... 141221.3.1 LCD DMA Engine ...................................................................................................... 141221.3.2 LIDD Bus Operation .................................................................................................. 141421.3.3 Raster Control ........................................................................................................... 141521.3.4 Clocking ................................................................................................................... 141821.3.5 LCD Frame Buffer ..................................................................................................... 141921.3.6 Palette ...................................................................................................................... 142521.3.7 Gray-Scaler/Serializer - Passive (STN) Mode .............................................................. 142521.3.8 Gray-Scaler/Serializer - Active (TFT) Mode ................................................................. 142521.3.9 Color/Grayscale Intensities and Modulation Rates ....................................................... 142521.3.10 Summary of Color Depth ............................................................................................ 1426



21.3.11 Output Format ........................................................................................................... 142621.3.12 Subpicture Feature .................................................................................................... 142721.4 Interrupts .................................................................................................................. 142821.5 Bus Transaction Modes ............................................................................................. 142921.6 Initialization and Configuration .................................................................................... 142921.7 Register Map ............................................................................................................ 143021.8 Register Descriptions ................................................................................................. 1431

22 Analog Comparators .......................................................................................... 147722.1 Block Diagram ........................................................................................................... 147822.2 Signal Description ..................................................................................................... 147822.3 Functional Description ............................................................................................... 147922.3.1 Internal Reference Programming ................................................................................ 148022.4 Initialization and Configuration .................................................................................... 148222.5 Register Map ............................................................................................................ 148322.6 Register Descriptions ................................................................................................. 1483

23 Pulse Width Modulator (PWM) .......................................................................... 149323.1 Block Diagram ........................................................................................................... 149423.2 Signal Description ..................................................................................................... 149623.3 Functional Description ............................................................................................... 149623.3.1 Clock Configuration ................................................................................................... 149623.3.2 PWM Timer ............................................................................................................... 149723.3.3 PWM Comparators .................................................................................................... 149723.3.4 PWM Signal Generator .............................................................................................. 149823.3.5 Dead-Band Generator ............................................................................................... 149923.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 149923.3.7 Synchronization Methods .......................................................................................... 150023.3.8 Fault Conditions ........................................................................................................ 150123.3.9 Output Control Block .................................................................................................. 150223.4 Initialization and Configuration .................................................................................... 150223.5 Register Map ............................................................................................................ 150323.6 Register Descriptions ................................................................................................. 1506

24 Quadrature Encoder Interface (QEI) ................................................................. 157224.1 Block Diagram ........................................................................................................... 157224.2 Signal Description ..................................................................................................... 157424.3 Functional Description ............................................................................................... 157424.4 Initialization and Configuration .................................................................................... 157724.5 Register Map ............................................................................................................ 157724.6 Register Descriptions ................................................................................................. 1578

25 Pin Diagram ........................................................................................................ 159526 Signal Tables ...................................................................................................... 159626.1 Signals by Pin Number .............................................................................................. 159726.2 Signals by Signal Name ............................................................................................. 161526.3 Signals by Function, Except for GPIO ......................................................................... 163126.4 GPIO Pins and Alternate Functions ............................................................................ 164626.5 Possible Pin Assignments for Alternate Functions ....................................................... 165126.6 Connections for Unused Signals ................................................................................. 1658


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27 Electrical Characteristics .................................................................................. 165927.1 Maximum Ratings ...................................................................................................... 165927.2 Operating Characteristics ........................................................................................... 166027.3 Recommended Operating Conditions ......................................................................... 166127.3.1 DC Operating Conditions ........................................................................................... 166127.3.2 Recommended GPIO Operating Characteristics .......................................................... 166127.4 Load Conditions ........................................................................................................ 166327.5 JTAG and Boundary Scan .......................................................................................... 166427.6 Power and Brown-Out ............................................................................................... 166527.6.1 VDDA Levels .............................................................................................................. 166627.6.2 VDD Levels ................................................................................................................ 166727.6.3 VDDC Levels .............................................................................................................. 166827.6.4 Response ................................................................................................................. 166927.7 Reset ........................................................................................................................ 167027.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 167227.9 Clocks ...................................................................................................................... 167327.9.1 PLL Specifications ..................................................................................................... 167327.9.2 PIOSC Specifications ................................................................................................ 167527.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 167527.9.4 Hibernation Clock Source Specifications ..................................................................... 167527.9.5 Main Oscillator Specifications ..................................................................................... 167627.9.6 System Clock Specification with ADC Operation .......................................................... 168027.9.7 System Clock Specification with USB Operation .......................................................... 168027.10 Sleep Modes ............................................................................................................. 168027.11 Hibernation Module ................................................................................................... 168127.12 Flash Memory ........................................................................................................... 168227.13 EEPROM .................................................................................................................. 168327.14 Input/Output Pin Characteristics ................................................................................. 168427.14.1 Types of I/O Pins and ESD Protection ......................................................................... 168627.15 External Peripheral Interface (EPI) .............................................................................. 168727.16 Analog-to-Digital Converter (ADC) .............................................................................. 169427.17 Synchronous Serial Interface (SSI) ............................................................................. 170027.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 170327.19 Universal Serial Bus (USB) Controller ......................................................................... 170427.20 LCD Controller .......................................................................................................... 170527.20.1 LCD Interface Display Driver (LIDD Mode) .................................................................. 170627.20.2 LCD Raster Mode ...................................................................................................... 171527.21 Analog Comparator ................................................................................................... 172127.22 Current Consumption ................................................................................................. 1723

A Package Information .......................................................................................... 1726A.1 Orderable Devices ..................................................................................................... 1726A.2 Part Markings ............................................................................................................ 1727A.3 Packaging Diagram ................................................................................................... 1728A.4 Packaging Materials .................................................................................................. 1729



List of FiguresFigure 1-1. Tiva™ TM4C1297NCZAD Microcontroller High-Level Block Diagram ....................... 50Figure 2-1. CPU Block Diagram ............................................................................................. 77Figure 2-2. TPIU Block Diagram ............................................................................................ 78Figure 2-3. Cortex-M4F Register Set ...................................................................................... 81Figure 2-4. Bit-Band Mapping .............................................................................................. 106Figure 2-5. Data Storage ..................................................................................................... 107Figure 2-6. Vector Table ...................................................................................................... 115Figure 2-7. Exception Stack Frame ...................................................................................... 118Figure 3-1. SRD Use Example ............................................................................................. 136Figure 3-2. FPU Register Bank ............................................................................................ 139Figure 4-1. JTAG Module Block Diagram .............................................................................. 204Figure 4-2. Test Access Port State Machine ......................................................................... 208Figure 4-3. IDCODE Register Format ................................................................................... 214Figure 4-4. BYPASS Register Format ................................................................................... 214Figure 4-5. Boundary Scan Register Format ......................................................................... 214Figure 5-1. Basic RST Configuration .................................................................................... 220Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 220Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 220Figure 5-4. Power Architecture ............................................................................................ 226Figure 5-5. Main Clock Tree ................................................................................................ 229Figure 5-6. Module Clock Selection ...................................................................................... 237Figure 7-1. Hibernation Module Block Diagram ..................................................................... 523Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 527Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 527Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 528Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 532Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 532Figure 7-7. Tamper Block Diagram ....................................................................................... 532Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 533Figure 8-1. Internal Memory Block Diagram .......................................................................... 591Figure 8-2. Flash Memory Configuration ............................................................................... 595Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 596Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 596Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 597Figure 8-6. Prefetch Fills from Flash ..................................................................................... 598Figure 8-7. Mirror Mode Function ......................................................................................... 599Figure 9-1. μDMA Block Diagram ......................................................................................... 668Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 675Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 677Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 678Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 680Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 681Figure 10-1. Digital I/O Pads ................................................................................................. 738Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 739Figure 10-3. GPIODATA Write Example ................................................................................. 740


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Figure 10-4. GPIODATA Read Example ................................................................................. 740Figure 11-1. EPI Block Diagram ............................................................................................. 808Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 816Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 816Figure 11-4. SDRAM Write Cycle ........................................................................................... 817Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 828Figure 11-6. iRDY Signal Connection ..................................................................................... 828Figure 11-7. PSRAM Burst Read ........................................................................................... 830Figure 11-8. PSRAM Burst Write ........................................................................................... 831Figure 11-9. Read Delay During Refresh Event ...................................................................... 832Figure 11-10. Write Delay During Refresh Event ....................................................................... 832Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 833Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 836Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 836Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 837Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 837Figure 11-16. Continuous Read Mode Accesses ...................................................................... 837Figure 11-17. Write Followed by Read to External FIFO ............................................................ 838Figure 11-18. Two-Entry FIFO ................................................................................................. 838Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 841Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 842Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 842Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 843Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 843Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 843Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 843Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 844Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 844Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 844Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 845Figure 13-1. GPTM Module Block Diagram ............................................................................ 947Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 955Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 957Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 959Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 959Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 960Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 960Figure 13-8. Timer Daisy Chain ............................................................................................. 961Figure 14-1. WDT Module Block Diagram ............................................................................. 1020Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1045Figure 15-2. ADC Module Block Diagram ............................................................................. 1046Figure 15-3. ADC Sample Phases ....................................................................................... 1051Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1052Figure 15-5. Skewed Sampling ............................................................................................ 1053Figure 15-6. Sample Averaging Example .............................................................................. 1054Figure 15-7. ADC Input Equivalency Diagram ....................................................................... 1055



Figure 15-8. ADC Voltage Reference ................................................................................... 1056Figure 15-9. ADC Conversion Result ................................................................................... 1057Figure 15-10. Differential Voltage Representation ................................................................... 1059Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1060Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1062Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1063Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1064Figure 16-1. UART Module Block Diagram ........................................................................... 1154Figure 16-2. UART Character Frame .................................................................................... 1157Figure 16-3. IrDA Data Modulation ....................................................................................... 1159Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1220Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1227Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1228Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1229Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1229Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1230Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1231Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1231Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1232Figure 18-1. I2C Block Diagram ........................................................................................... 1269Figure 18-2. I2C Bus Configuration ....................................................................................... 1271Figure 18-3. START and STOP Conditions ........................................................................... 1272Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1273Figure 18-5. R/S Bit in First Byte .......................................................................................... 1273Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1273Figure 18-7. High-Speed Data Format .................................................................................. 1279Figure 18-8. Master Single TRANSMIT ................................................................................ 1283Figure 18-9. Master Single RECEIVE ................................................................................... 1284Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1285Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1286Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1287Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1288Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1289Figure 18-15. Slave Command Sequence .............................................................................. 1290Figure 19-1. CAN Controller Block Diagram .......................................................................... 1350Figure 19-2. CAN Data/Remote Frame ................................................................................. 1351Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1360Figure 19-4. CAN Bit Time ................................................................................................... 1364Figure 20-1. USB Module Block Diagram ............................................................................. 1401Figure 21-1. LCD Block Diagram ......................................................................................... 1410Figure 21-2. LCD Raster Data Path ...................................................................................... 1417Figure 21-3. Input and Output Clocks ................................................................................... 1418Figure 21-4. Palette RAM Structure for 1, 2, and 4 Bits Per Pixel ........................................... 1420Figure 21-5. 24 bpp Packed Data Format ............................................................................. 1422Figure 21-6. 24 bpp Unpacked Data Format ......................................................................... 1422Figure 21-7. 24 bpp Color RGB Remapping on LCDDATA[23:0] ............................................. 1423Figure 21-8. 16 bpp Data Format ......................................................................................... 1423Figure 21-9. 16 bpp Color Component Ordering .................................................................... 1423


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Figure 21-10. 12 bpp Data Format ......................................................................................... 1424Figure 21-11. 12 bpp Color Component Ordering .................................................................... 1424Figure 21-12. 1/2/4/8 bpp Dither Output ................................................................................. 1424Figure 21-13. Monchrome and Color Output ........................................................................... 1427Figure 21-14. Example of Subpicture ..................................................................................... 1428Figure 21-15. Subpicture Output with HOLS Bit Variations ....................................................... 1428Figure 22-1. Analog Comparator Module Block Diagram ....................................................... 1478Figure 22-2. Structure of Comparator Unit ............................................................................ 1479Figure 22-3. Comparator Internal Reference Structure .......................................................... 1480Figure 23-1. PWM Module Diagram ..................................................................................... 1495Figure 23-2. PWM Generator Block Diagram ........................................................................ 1495Figure 23-3. PWM Count-Down Mode .................................................................................. 1498Figure 23-4. PWM Count-Up/Down Mode ............................................................................. 1498Figure 23-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1499Figure 23-6. PWM Dead-Band Generator ............................................................................. 1499Figure 24-1. QEI Block Diagram .......................................................................................... 1573Figure 24-2. QEI Input Signal Logic ...................................................................................... 1574Figure 24-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1576Figure 25-1. 212-Ball BGA Package Pin Diagram (Top View) ................................................. 1595Figure 27-1. Load Conditions ............................................................................................... 1663Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1665Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1665Figure 27-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1667Figure 27-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1668Figure 27-6. POK Assertion vs VDDC ................................................................................... 1669Figure 27-7. POR-BOR VDD Glitch Response ....................................................................... 1669Figure 27-8. POR-BOR VDD Droop Response ...................................................................... 1670Figure 27-9. Digital Power-On Reset Timing ......................................................................... 1671Figure 27-10. Brown-Out Reset Timing .................................................................................. 1671Figure 27-11. External Reset Timing (RST) ............................................................................ 1671Figure 27-12. Software Reset Timing ..................................................................................... 1672Figure 27-13. Watchdog Reset Timing ................................................................................... 1672Figure 27-14. MOSC Failure Reset Timing ............................................................................. 1672Figure 27-15. Hibernation Module Timing ............................................................................... 1682Figure 27-16. ESD Protection ................................................................................................ 1686Figure 27-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1687Figure 27-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1688Figure 27-19. SDRAM Read Timing ....................................................................................... 1689Figure 27-20. SDRAM Write Timing ....................................................................................... 1689Figure 27-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1690Figure 27-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1690Figure 27-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1691Figure 27-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1691Figure 27-25. General-Purpose Mode Read and Write Timing ................................................. 1692Figure 27-26. PSRAM Single Burst Read ............................................................................... 1693Figure 27-27. PSRAM Single Burst Write ............................................................................... 1694Figure 27-28. ADC External Reference Filtering ..................................................................... 1700Figure 27-29. ADC Input Equivalency Diagram ....................................................................... 1700



Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer TimingMeasurement .................................................................................................. 1701

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1702Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1702Figure 27-33. I2C Timing ....................................................................................................... 1704Figure 27-34. ULPI Interface Timing Diagram ......................................................................... 1705Figure 27-35. Command Write in Hitachi Mode ....................................................................... 1708Figure 27-36. Data Write in Hitachi Mode ............................................................................... 1708Figure 27-37. Command Read in Hitachi Mode ...................................................................... 1709Figure 27-38. Data Read in Hitachi Mode ............................................................................... 1709Figure 27-39. Motorola 6800 Graphic Display Mode Write (Synchronous & Asynchronous

Operation) ....................................................................................................... 1710Figure 27-40. Motorola 6800 Graphic Display Mode Read (Synchronous & Asynchronous

Operation) ....................................................................................................... 1711Figure 27-41. Motorola 6800 Graphic Display Mode Status (Synchronous & Asynchronous

Operation) ....................................................................................................... 1712Figure 27-42. Micro-Interface Graphic Display Intel Write ........................................................ 1713Figure 27-43. Micro-Interface Graphic Display Intel Read ........................................................ 1714Figure 27-44. Micro-Interface Graphic Display Intel Status ...................................................... 1715Figure 27-45. LCD Raster-Mode Display Format .................................................................... 1717Figure 27-46. LCD Raster-Mode Active .................................................................................. 1718Figure 27-47. LCD Raster-Mode Passive ............................................................................... 1719Figure 27-48. LCD Raster-Mode Control Signal Activation ....................................................... 1720Figure 27-49. LCD Raster-Mode Control Signal Deactivation ................................................... 1721Figure A-1. Key to Part Numbers ........................................................................................ 1726Figure A-2. TM4C1297NCZAD 212-Ball BGA Package Diagram .......................................... 1728Figure A-3. 212-Ball BGA ZAD Package Carrier Tape .......................................................... 1729Figure A-4. 212-Ball BGA ZAD Package Plastic Reel .......................................................... 1730Figure A-5. 212-Ball BGA ZAD Package Tape and Reel Box ................................................ 1730


Table of Contents

List of TablesTable 1. Revision History .................................................................................................. 43Table 2. Documentation Conventions ................................................................................ 45Table 1-1. TM4C1297NCZAD Microcontroller Features .......................................................... 48Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 80Table 2-2. Processor Register Map ....................................................................................... 81Table 2-3. PSR Register Combinations ................................................................................. 87Table 2-4. Memory Map ....................................................................................................... 98Table 2-5. Memory Access Behavior ................................................................................... 102Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 104Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 105Table 2-8. Exception Types ................................................................................................ 110Table 2-9. Interrupts .......................................................................................................... 111Table 2-10. Exception Return Behavior ................................................................................. 119Table 2-11. Faults ............................................................................................................... 120Table 2-12. Fault Status and Fault Address Registers ............................................................ 121Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 123Table 3-1. Core Peripheral Register Regions ....................................................................... 130Table 3-2. Memory Attributes Summary .............................................................................. 134Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 136Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 137Table 3-5. AP Bit Field Encoding ........................................................................................ 137Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 138Table 3-7. QNaN and SNaN Handling ................................................................................. 141Table 3-8. Peripherals Register Map ................................................................................... 142Table 3-9. Interrupt Priority Levels ...................................................................................... 167Table 3-10. Example SIZE Field Values ................................................................................ 195Table 4-1. JTAG_SWD_SWO Signals (212BGA) ................................................................. 204Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 206Table 4-3. JTAG Instruction Register Commands ................................................................. 212Table 5-1. System Control & Clocks Signals (212BGA) ........................................................ 216Table 5-2. Reset Sources ................................................................................................... 217Table 5-3. Clock Source Options ........................................................................................ 227Table 5-4. Clock Source State Following POR ..................................................................... 228Table 5-5. System Clock Frequency ................................................................................... 231Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 233Table 5-7. Actual PLL Frequency ........................................................................................ 233Table 5-8. Peripheral Memory Power Control ...................................................................... 238Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 239Table 5-10. MOSC Configurations ........................................................................................ 242Table 5-11. System Control Register Map ............................................................................. 243Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 272Table 5-13. MOSC Configurations ........................................................................................ 276Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 295Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 298Table 5-16. Module Power Control ........................................................................................ 443Table 5-17. Module Power Control ........................................................................................ 445



Table 5-18. Module Power Control ........................................................................................ 448Table 5-19. Module Power Control ........................................................................................ 454Table 5-20. Module Power Control ........................................................................................ 456Table 5-21. Module Power Control ........................................................................................ 458Table 5-22. Module Power Control ........................................................................................ 460Table 5-23. Module Power Control ........................................................................................ 463Table 5-24. Module Power Control ........................................................................................ 465Table 5-25. Module Power Control ........................................................................................ 469Table 5-26. Module Power Control ........................................................................................ 471Table 5-27. Module Power Control .......................................