TiSi2thickness limitations for use with shallow junctions and SWAMI or LOCOS isolation

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 10, OCTOBER 1986 1463

TiSi, Thickness Limitations for Use with Sh.allow Junctions and SWAMI or LOCOS Isolation

DEVEREAUX C. CHEN, THOMAS R. CASS, JOHN E. TURNER, PAUL P. MERCHANT, AND KUANG YI CHIU, MEMBER, IEEE

Abstruct-We have examined the impact of TiSiz formation on the properties of shallow n+ and p+ junctions (0.17-0.20 pm) in Si. The deposited Ti thickness varied from 300 to l O O q A . The p+ junctions developed high leakage currents after a reaction with Ti of initial thickness greater than 700 A while the n+ junctions were not de- graded. In these studies LOCOS isolation was used and the TiSiz was formed away from the island edges. Additional experiments were performed on n+ and p+ diodes using SWAMI isolation with the TiSi2 formed right up to the edges of the isolation. From step-height, spreading resistance, and RBS measurements, it was found that the thickness of TiSi, formed on n' Si was less than on p' Si for a given initial Ti thickness. The amount of electrically active dopant remaining in the substrates was seen to decrease with increasing Ti thickness. The result was supported by SIMS measurements, which also showed an accu- mulation of atomic fluorine at the TiSiz interface (on p+ diodes only). Cross-sectional transmission electron microscopy was used to examine the silicide morphology and interface planarity.

I. INTRODUCTION

I N VLSI TECHNOLOGY, titanium disilicide (TiSi2) has the potential of providing low-resistance interconnects,

low contact resistance, and self-aligned formation [ 11, [2]. However, in implementing TiSi2 one must consider the possible degradation of the devices due to silicidation. Specific areas of concern include possible gate dielectric degradation due to stress effects or consumption of gate polysilicon, undesirable gate to source-drain leakage due to lateral Si diffusion [3], [4], accelerated dopant diffusion (observed for tantalum disilicide [5]), dopant segregation [6], and possible degradation of device junctions due to silicon consumption during formation of the TiSi2. Inter- face roughness and contact spiking [7] are also concerns. Additionally, the compatibility of TiSi2 with new isolation techniques, e.g., SWAMI [8] is not well known. This investigation addresses the impact of TiSi2 formation upon shallow n+-p and pt-n junction properties and its compatibility with the SWAMI isolation process, using con- ventional LOCOS isolation as a control. Fig. 1 shows a typical MOS device cross section and the regions where TiSi2 would be formed in a self-aligned (also referred to as Salicide [l]) process.

Manuscript received December 31, 1985; revised May 2, 1986. The authors are with Hewlett-Packard Laboratories, Palo Alto, CA

IEEE Log Number 8609827. 94304.

TiSi, -- I Si SUBSTRATE I

~ ~~~~

Fig. 1 . Mos device with self-aligned formation of TiSi2.

11. EXPERIMENTAL

nf-p diodes were fabricated on p(100) 16-24-Q cm Si wafers, and p f -n diodes were fabricated on n(100) 4- 8-Q * cm wafers in which a blanket n-well of 1 X cm-3 concentration was previously formed. Six lots of 24 wafers each were used to study n+-p dio'des. Initial thicknesses of deposited Ti were 450, 700, and 1000 .&, respectively, and both LOCOS and SWAMI isolations were used. For the pt-n diodes five lots were used with similar thicknesses of Ti. After island formation, ion implantation of the n+ or p+ regions was performed using arsenic and boron difluoride, respectively, in the dose range of 2 to 6 X cmV2 and energy range of 50 to 100 keV. The n+-p and p+-n junctions were then furnace annealed in flowing N2 to achieve junction depths :in the 0.2-pm regime. Some wafers (hereafter referred to as Schottky splits) did not receive any implants. The experiments were further subdivided after this stage. Those of which TiSiz was formed at the eges of the isolation (Salicide splits) had various thicknesses of Ti deposited. TiSi2 was selectivily formed on the active regions using a three-step furnace annealing and etch process. A typical example of a TiSi2 formation process is by a first anneal at tempera- tures around 600-700°C, and then a second anneal is performed at 800°C after, selective wet etching of the un- reacted Ti layer on oxide [2]. The sFlect,ive wet etch is by a 2H2S04 : H202 mixture. A 4200- A low-temperature oxide (LTO) was deposited and contacts defined within the borders of the isolation. Another set of wafers (enclosed splits) had LTO deposited and contacts formed before Ti deposition. TiSi2 was then selectively formed inside these contacts and did not touch the edges of the isolation. Wa- fers which were not silicided (control splits) accompanied each lot and served as monitors. Each split then under- went a sequential deposition of lOOO-,& W-Ti( 10 wt%) and 6000- A A1-Si(2 wt %) after an Ar sputter etch. This

0018-9383/86/1000-1463$01.00 O 1986 IEEE

1464 IEE3 TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 10, OCTOBER 1986

u n + OR p + JUNCTION

SWAMI OR LOCOS

p OR n Si < l o o > ~

SUBSTRATE

(a) (b) ME TALLURGICAL SPECIMENS

( F O R ANALYSiS 1

n + OR p +

Si SUBSTRATE

(c) Fig. 2. Experimental test structures: (a) ENCLOSED diode, (b) !'ALI-

CIDE diode, and (c) metallurgical specimens.

metallization system has been previously shown [9] It I be reliable in consacting the TiSi2/Si system. Standard st1;ps of lithography, plasma etching, backside A1-Si, and 450°C H2 alloying followed.

Unpatterned wafers were prepared in the same pro:ess to provide larger areas for secondary ion mass spectmm- etry (SIMS), He ions backscattering (RRS), step-height, spreading resistance, and four-point probe measureme:rllts. The cross-section of these metallurgical specimens as ell as those of the enclosed and silicided devices can be :'<:en in Fig. 2.

111. RESULTS From four-point probe measurements the final slleet

resistance (R,) of the silicided regions was seen to tle- crease with increasing Ti thickness. For example, n-' regions showed a decrease from 6.0 to 1.65 Wsq when the initial Ti thickness was varied from 450 to 1000 A . For the same Ti thicknesses the sheet resistance of the ps regions decreased from 2.4 to 0.85 Wsq.

The reverse leakage current of diodes of area 3. I1 X cm2 and perimeter 25.3 cm was measured at 2;;''C

and 5-V reverse bias. We chose a diode with a long perimeter because it was found that the leakage for diclcies with comparable areas was greater, the longer the perilm- eter. Diodes with leakage currents greater than 500 ],A were defined as failures. This translates to a leakage 4 'llr- rent density of approximately 2 fA/pm of active junc,irsn edge.

In Fig. 3 yield data is shown in n+-p LOCOS-enclc sed silicided splits as a function of Ti thickness. The y c:ld is relatively unaffected by silicidation. The p-Scholrky diodes showed high leakage currents (average leakage 10 pA) as might be the case if the junction were totally cctn- sumed. Data for the n+ SWAMI splits is shown in F&; 4 for both enclosed and salicide structures. The yields illre similar to the n+ LOCOS-enclosed case and relatively !In- dependent of whether or not the TiSi2 touches the edges of the isolation. The average leakage of all the good dio Jes (which passed the yield test) is shown in Fig. 5. IN a11 these figures each data point represents measurements 'on

q - 1 1 ir-, 8 .8

0

2- @ .4

ij .2 e 0.0 400 500 I300 700 800 900 1000 1100

Ti THICKNESS (A)

Fig. 3. Relative yield of silicided n + and Schottky diodes for LOCOS- ENCLOSED structure. Solid circles are for silicided n + diodes; hollow circles are for Schottky diodes.

n G: .4 ?: 9 .2

F 0.0

- Y

200 300 400 500 600 700 800 90010001100

Ti THICKNESS (A)

Fig. 4. Relative yield of silicided n + and Schottky diodes for SWAMI SALICIDE and ENCLOSED structures. Solid circles are for SWAMI SALICIDE diodes, squares are for SWAMI ENCLOSED diodes, and hollow circles are for Schottky diodes,

0 200 400 600 800 1000

Ti THICKNESS ( A o )

Fig. 5 . Average leakage current of n + SWAMI-SALICIDE diodes versus initial Ti thickness.

at least 56 diodes from two wafers (and in some cases 84 diodes from three wafers).

Fig. 6 shows yield data for the first 3 lots of p+-n LOCOS-enclosed splits. The introduction of TiSi2 appar- ently reduces the 'yield by approximately 45 percent for Ti in the 450-700-A regime. Note that for 1000-A Ti the yield is zero (average leakage 32 PA). Also note that the nonsilicided controls that accompanied each lot also exhibit quite poor yield ( - 50 percent). The n-Schottky diodes are also quite leaky (average leakage 354 pA for 450-A Ti, 0.3 A for 700- and 1000-A Ti).

Our following p+ junction lots had excellent yields for the control wafers in contrast to our earlier lots. It is still not clear whether the improvement was related to a change in the starting material or a slightly modified junction annealing schedule. These results are shown in Figs. 7 and 9. The average leakage current of all good diodes is plot- ted in Figs. 8 and 10 also as a function of Ti thickness.

CHEN et al.: TiSiz THICKNESS LIMITATIONS

1 .:r 9 4

5 . 2 W F 0.0

400 500 600 700 800 900 1000 1100

Ti THICKNESS (A)

Fig. 6 . Relative yield of silicided p + and Schottky diodes for LOCOS- ENCLOSED structure. Solid circles are for silicided p + diodes; hollow circles are for Schottky diodes.

l o o f - T 1 90

80 - 7 0 -

Y

30 - 20 -

10 -

0 200 400 600 800 1000

1465

Ti THICKNESS (A "I

Fig. 9. Yield of p + SWAMI-SALICIDE diodes versus initial Ti thickness.

1

Ti THICKNESS (A'I

Fig. 7 . Yield of p+ LOCOS-SALICIDE diodes versus initial Ti thickness. 0 200 400 600 800 1000

Ti THICKNESS ( A o )

Fig. 10. Average leakage current of p + SWAMI-SAILICIDE diodes versus initial Ti thickness.

- - 1 1 lb+J 10 0 200 400 - 600 800 1 1000

Ti THICKNESS ( A " )

Fig. 8. Average leakage current of p+ LOCOS-SALICIDE diodes versus initial Ti thickness.

The yield and reverse leakage current clearly show that an upper limit to usable Ti thickness (approximately 700 A ) exists for 0.2-pm-deep p+ junctions for both the SWAMI and LOCOS isolation schemes. This is to be contrasted with the n+ junctions where up to 1000-A Ti could be used. The explanation for this can be seen from the following observations.

For the same process conditions, the thickness of TiSi2 formed on n+ diodes was less than on pf diodes, which agrees with the observations of other workers [lo]. Re- sults of this differential formation are manifested in the

spreading resistance profiles of Figs. 11 and 12 where the n+ junctions show significant arsenic relmaining in the Si even for 1000-A Ti, while p+ junctions are almost consumed for 700- A Ti.

RBS, spreading resistance, and stepheight measurements were used to measure the TiSi2 thickness on the different substrates (see Fig. 13). Assuming stochiometric TiSiz (suggested by RBS), the amount of Si consumed is approximately 0.9 of the TiSiz thickness [ l l ] , which agrees with the spreading resistance data when Si consumption is calculated.

By plotting the peak concentration of the electrically active dopant remaining in the substrate (from spreading resistance) versus deposited Ti thickness, one might de- duce the process sensitivity of specific contact resistance to Ti thickness (Fig. 14). In theory, it is proportional to the inverse root peak surface concentratlion [12]. A more quantitative measure of junction consumption can be ob- tained by considering the integrated dosage of the remaining electrically active dopant shown in Fig. 15, which shows the same trend as the peak concentration. From the SIMS profiling the fraction of atomic bo'ron remaining in the substrate also appears to decrease with increasing TiSi2 thickness (Fig. 16), as one would expect from the spread-

1466 IEE3 TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 10, OCTOBER 1986

1 O'L

10'0

10'.

Carrier Concentration

(cmY

10"

10'.

10"

l o > & [

n CONTROL NO Ti

0 4 5 0 A Ti

X 700A Ti

A lOOOA Ti

0.1 0.2 0.3 0.4 0.5 (

,PPP

DEPTH - microns

Fig. 11. Spreading resistance profiles of nC samples after TiSi:, was stripped.

10"

1 O'?

10"

Carrier Concentration

Icm-')

10"

10"

10''

10" , 1 0.1 0.2 0.3 0.4 0.5 0 .6

DEPTH - Microns

Fig. 12. Spreading resistance profiles of p+ samples after TiSi,, was stripped. Initial thicknesses of Ti deposiaed are indicated. No jurction was seen for the samples that had 1000-A deposited.

2000

P+ Si P + Si P + Si

N + S i N + S i N T S ~ RES Alpha Step R Spread

0 I 1 , , 400 500 600 700 800 900 1000

Deposited Ti (A)

Fig. 13. TiSi, formed versus initial Ti thickness.

1E14

0 200 400 600 BOO 1000

Ti DEPOSITED IAl

Fig. 14. Peak electrical carrier concentration formed after TiSiz strip.

1 E l O

clEB 0 200 400 600 BOO 1000

INITIAL Ti THICKNESS IAI

Fig. 15. Remaining electfically active dopant after Ti strip.

0 500 1000 1500 2000 2500

Sputtering time (sed

(b)

Fig. 16. SIMS profile of p+ silicided samples at two initial Ti thicknesses (a) 450-A initial Ti, (b) 1000-A initial Ti.

ing resistance data. Fluorine is also found to pile up at the TiSi2 interface.

TEM specimens were prepared for n+-p SWAMI-salicide and p+-n LOCOS-enclosed splits for 450- and 1000- A Ti thicknesses. Some examples are shown in Figs. 17- 19. In these pictures the thermally grown field oxide is approximately 40qO A thick, and the deposited LTO was nominally 4200 A thick. The line of defects shown in Figs. 17 and 18 is interpreted as ion-implantation damage remaining after post-implantation annealing. These defects are situated at the limit of amorphization. It can be seen that the TiSi2 layers showed uniform morphology. Samples having thinner Ti had smoother interfaces with the Si substrate. As the thickness of Ti was increased the silicide layers became less uniform and the interfaces rougher. The 1000-A n+-p SWAMI-salicide sample showed a slight encroachment of the TiSiz ( - 900 A ) onto the adjacent field oxide. The 1000-A p+-n SWAMI-salicide samde shows gross Si consumDtion. Note that our

CHEN et al.: TiSi2 THICKNESS LIMITATIONS 1467

Al(Si) W(Ti) TiSiz / I / \ CONTACT

DEPOSITED SiOz I

I ISOLATION TiSiz OXIDE

DEPOSITED SiOz TiSi2

I

\ ' \ 0.5pm " ISOLATION ' OXIDE

TiSiz I

(b)

Fig. 17. TEM Cross sections of n f SWAMI-SALICIDE diodes: (a) 450- A initial Ti, (b) 1000-A initial Ti.

Fig. 19. TEM cross sections of p+ SWAMI-SALICXDE diodes: (a) 450- A initial Ti, (b) 700-A initial Ti, and (c) 1000-A initial Ti.

W(Ti) AI(Si)

\ \ \ SiOa DEFECTS T i s i p CONTACT

Fig. 18. TEM cross sections of p + LOCOS-ENCLOSED diodes: (a),450- A initial Ti, (b) 1000-A Ti.

initial concerns of enhanced TiSi, formation, and there- fore greater junction consumption at the SWAMI isolation edges due to possible existence of higher stresses than for LOCOS isolation edges, appear to have been unfounded.

IV. DISCUSSION The electrical data indicate that the p"-n junctions that

had poor yields of the nonsilicided controls further yield reduction when TiSi, was introduced. Tlhe n+ junctions were much less affected. This difference: could be due to precipitation of Ti at residual BF2 implantation damage sites that have not been completely annealed out. While the n+-p junctions also possess residual dislocations, these do not appear to be electrically active. The reasons for fluctuating p+ junction yield (Figs. 6 , 7, 9) require further investigation. It is not clear whether the problem is related to the starting material or is rlenated to process contamination or insufficient annealing. However, it is clear that nonsilicided controls should always be included when evaluating junction leakage as it relates to silicides.

Given that one is constrained to a certain junction depth by device design, p+ junctions set the upper limit to Ti thickness. This restriction becomes obvious when one compares the yields of n+-p and p+-n for 1000-A Ti (Figs. 6 , 7, 9), where the p+-n yield is zero while the n+-p yield remains high. The reason for this lies in the relative difference in the silicidation rate: on p+ and 11'

areas [lo]. The p+ junction is totally consumed by 1000- A Ti whereas the n+ junction is not. Thick Ti is more

1468 IEEli TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 10, OCTOBER 1986

desirable for low sheet resistance, but an upper limit is reached since rougher interfaces and more junction :#on- sumption result (Figs. 17-19) if the Ti is too thick. ‘This factor will cause unacceptable leakage and probably llead to higher contact resistance, which is theoretically Fro- portional to the inverse square root of surface dopant concentration (Fig. 14).

The data also indicate that TiSi2 is compatible ,,vith SWAMI isolation, for the case of n’ and p’ junctilons provided that the SWAMI is processed correctly ancl the Ti thickness is kept below the 700-A regime.

V. CONCLUSIONS p+ junctions set the limit for Ti thickness and are mlore

susce,ptible to silicide-induced leakage than n’ junctions, due to greater leakage sensitivity and junction consumption. TiSi2 is Compatible with SWAMI isolation for Imth n+ and pi junctions. Ti thicker than 700-A should nc t be used on 0.2-pm junctions in order to avoid excessive junction consumption and rough interfaces, which will tend to increase reverse leakage current and contact rc,r;is- tance. This limit will vary somewhat depending on the specific annealing schedule of the TiSi2 formation.

ACKNOWLEDGMENT The authors would like to thank M. Flores for her ‘ex-

cellent technical support in processing and testing the wafers, D. Hayes for TEM sample preparation, and the !;taff of the Integrated Circuit Processing Laboratory for wafer processing. The Testing Group provided testing and ZiClf t - ware support, in particular T. Harms, T. Ekstedt, P. 1710- res, and U. Kaempf. Some of the electron microgrs phs presented were taken at the High Voltage Electron Mi- croscopy Laboratory, National Center for Electron Mi- croscopy, Berkeley, CA. We also thank J. Moll for x v - era1 useful discussions, and D. Bartelink and C. Tylell for their support of this work.

REFERENCES 111 C. K. Lau, Y . C. See, D. B. Scott, J . M. Bridges, S. M. Perna and

R. D. Davies, “Titanium disilicide self-aligned source/drain i- I;ate technology,” in IEDM Tech. Dig . , p. 714, 1982.

[ 2 ] C. Y. Ting, “Silicide for contacts and interconnects,” in ZEDM :?i,ch. Dig . , p. 110, 1984.

[3] M. E. Alperin, T. C. Holloway, R. A. Haken, C. D. Gosmeye .: R. V. Karnaugh, and W. D. Parmantie, “Development of the self-alj ;ned titanium silicide process for VLSI applications,” IEEE J . Solid-,i!uate Circuits, vol. SC-20, no.1, p. 61, Feb. 1985.

[4] P. Revesz,, J. Gyimesi, I,. Pogany, and G. Peto, “Lateral grow 11 of titanium silicide over a silicon dioxide layer,” J . Appl. Phys., vol. 54, no. 4 , p. 2114, Apr. 1983.

[5] L. C. Parillo, S. J. Hillenius, R. L. Field, E. L. Wu, W. Fitchner and M.-L. Chen, “A fine-line CMOS technology that uses p+ poly- siliconisilicide gates for NMOS and PMOS devices,” in IEDM i’ech. D i g . , p. 418, 1984.

[6] C. B. Cooper, 111, R . A. Powell, and R. Chow, “Dopant red c,tri- bution in silicides: Materials and process issues,” J . Vac. Sei. Tech- nol. B , vol. 2, no. 4, p. 718, Oct./Dec. 1984.

171 C. Y. Ting and M. Wittrner “Investigation of the Al/TiSi,iSi colllact system,” J . Appl. P h y s . , vol. 54, no. 2 , p. 937, Feb. 1983.

[8] K. Y. Chiu, J. L. Moll, K. M. Cham, J. Lin, C. Lage, S. Ang, los, and R. T’illman, “The sloped wall SWAMI,” ZEEE Truns. Elec tl*on Devices, vol. ED-30, no. 11, p. 1506, Nov. 1983.

191 D. C. Chen, P. Merchant, and Jun Amano, “Thermal stability of Al- SilTiSi,lSi Schottky diodes,” J . Vac. Sci. Technol. A , vol. 3, no. 3, p. 709, MayIJune 1985.

[lo] H. K. Park, J. Sachitano, M. McPherson, T. Yamaguchi, and G. Lehman, “Effects of ion implanation doping on the formation of TiSi2,” J . Vac. Sci. Technol., A , vol. 2, no. 2, p. 264, Apr./June 1984.

[ I l l S. P. Murarka, Silicides for VLSI Applications. New York: Aca- demic, 1983, p. 130.

[12] S . M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, p. 304.

* Devereaux C. Chen was born in Kingston, Ja- maica. He received the B.S. degree from the Uni- versity of Manchester, United Kingdom, in physics and electric engineering and the M.S. degree from Yale University in electrical engineering.

Since joining Hewlett-Packard Laboratories in 1981, he has focussed on submicrometer CMOS/ VLSI process development where he has. been active in the research of planarization, interconnects, silicides, diffusion barriers, novel structures, device design, and process integration.

*

the photo-electronic pr acterization Departmer focussed on secondary and devices.

John E. Turner was born in 1954 in Hammond, IN. He received the B.S. degree in engineering physics in 1976 from the University of Illinois at Champaign-Urbana and the Ph.D. degree in physics in 1982 from the University of California. San Diego. His doctoral research focussed on experimental studies and mathematical modeling of non- linear catalyzed chemical reactions.

In post-doctoral work at Lawrence Berkeley Laboratories and at the University of California, Berkeley, he published several surface studies of

operties of oxides. Since joining the materials char- it of Hewlett-Packard Laboratories in 1984, he has ion mass spectrometry of semiconductor structures

*

Paul P. Merchant received the Ph.D. in con- densed matter physics from Brown University in 1978.

He then held postdoctoral positions at Brown and with the C.N.R.S. in Bordeaux, France, prior to joining Hewlett-Packard Laboratories in 1979. He is currently a Project Leader on the technical staff of the Silicon Process Laboratory at Hewlett- Packard working mainly on electromigration, silicide process development, and multilevel metallization.

Dr. Merchant is a member of the APS, the AVS, and Sigma Xi.

CHEN et al.: TiSiz THICKNESS LIMITATIONS 1469

Kuang Yi Chiu ("81) was born in Kaohsiung, Taiwan. He received the B.S.E.E degree from National Cheng Kung University, Taiwan, in 1966, the M.S.E.E degree from National Chiao Tung Univeristy, Taiwan, in 1968, and the Ph.D. degree in materials science from University of Southern California, Los Angeles, in 1974.

He was at Northrop Research and Technology Center, Los Arrgeles, CA, from 1973 to 1979, where he worked on radiation effects on MOS devices. Later, he became Group Leader responsible

for the development of infrared focal plane imaging sensor arrays. He joilled Hewlett-Packard Laboratories in 1979, where he has done research on VLSI process development. His current interests include new device development hot-electron degradation in submicrometer MOSFET's, and silicide technology for submicrometer VLSI. He is presently Project Manager. of the Integrated Circuit Laboratory of Hewlett-Packard responsible for submicrometer CMOS/VLSI process development.

Dr. Chiu is a member of Eta Kappa Nu and IEElE Electron Device So- ciety.

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TiSi2thickness limitations for use with shallow junctions and SWAMI or LOCOS isolation