Time, Phase and Frequency Synchronization of Low-Cost DVB ...nts.uni-duisburg-essen.de/downloads/nt-prakt12/dokum/1531143033... · Communication Systems Time, Phase and Frequency

Xuan Liup. 1

Chair ofCommunication Systems

N T STime, Phase and Frequency Synchronization of Low-Cost DVB-T USB Receivers Acting as Software Defined Radios in a Multi-Channel Coherent Receiver

Time, Phase and Frequency Synchronization of Low-Cost DVB-T USB Receivers Acting as Software Defined Radios in a Multi-Channel

Coherent Receiver

Xuan Liu

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Outline

§ Motivation and Objective§ Theoretical Background§ Multi-Channel Coherent Receiver Model§ Hardware and Software Implementation§ Verification and Measurement§ Conclusion and Outlook

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Motivation

Software Defined Radio (SDR)§ Pros

• Less need for dedicated hardware• Fulfill multi-purpose with one module

§ Cons• Most SDR platforms are fairly expensive • Less feasibility for having multiple devices

RTL-SDR (DVB-T Receiver) is currently the cheapest (around 10€) andhas surprisingly good performance in terms of general usability

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Objective

§ Theoretical study of RTL-SDR§ Building a four-channel coherent receiver with RTL-SDRs

• Time Synchronization• Frequency Synchronization• Phase Synchronization

§ Measurement and Verification

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Outline

§ Motivation and Objective§ Theoretical Background§ Multi-Channel Coherent Receiver Model§ Hardware and Software Implementation§ Verification and Measurement § Conclusion and Outlook

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Theoretical BackgroundSoftware Defined Radio

§ Software Defined Radio (SDR) offers a solution to build a flexible and cost-efficient wireless network by software defining some or all of the radio operating functions.

§ SDR Block Diagram

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Theoretical BackgroundDVB-T Dongle (RTL-SDR)

§ MCX Female Connector§ USB 2.0§ Tuner Chip R820T § Demodulator Chip RTL2832U

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Theoretical BackgroundDVB-T as a SDR

R820T RTL2832UDSP

RF Front End ADC & DSP

I

Q

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Outline


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Multi-Channel Coherent Receiver Model

§ Coherent Receiver Requirement• The sample clock must be synchronized among receivers• The starting moment of sampling must be aligned among receivers

§ Applications which require phase synchronous reception• Frequency synchronization• Phase prior knowledge

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§ Sample clock and frequency synchronization• Clock jitter and drift • 28.8MHz clock crystal is the single clock source for RTL-SDR• Solution: Sharing a common clock source among RTL-SDRs

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§ Fractional-N PLL Residual Frequency Error

• Continuous phase drift between two RTL-SDRs even with shared common clock

• Hidden 17th bit of the fractional-N PLL is set randomly at retune• Frequency mismatch assumes discrete values

Frequency Mismatch

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§ Time Synchronization

• USB communication couple of milliseconds

• PLL lock time max. 5ms

• Solution: A wideband noise signal is fed into each RTL-SDR at the beginning of the reception and cross-correlation is calculated

Ø The autocorrelation of white noise is a Dirac delta function

Ø No retune is needed when the antenna reception starts

• Time offset stays constant as long as no samples are lost

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§ Phase Synchronization• Random phase offset due to the fractional-N PLL inside the tuner chip

R820T occurs at every retune• Solution: Angle difference between time aligned noise signal of RTL-

SDRs is the phase offset • Phase offset stays constant as long as no retune occurs

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Outline

§ Motivation and Objective§ Theoretical Background§ Multi-Channel Coherent Receiver Model§ Hardware and Software Implementation§ Verification and Measurement§ Conclusion and Outlook

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Hardware and Software Implementation

RTL-SDR 2

RTL-SDR 3

28.8MHz Clock Source

Demodulator TunerRTL-SDR 4

RTL-SDR 1

I2C CommunicationTimer Circuit

Power Divider

RF Switch 1Antenna 1

Antenna 2

Antenna 3

Antenna 4 RF Switch 4

RF Switch 3

RF Switch 2

Wideband NoiseSource

CTRL

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MatlabScript Retune Pause

ReceiveData /

Time delayEstimation

AntennaSignal

Detection

ReceiveData

Phase & Frequency

Offset Estimation

Time, Phase &Frequency

Compensented

RTL Status Idle Retune PLL Locked

I2C Idle Active Idle

CTRL Low High Low

RXSignal

AntennaSignal Calibration Noise Signal Antenna Signal

tt=0

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Outline


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Verification and Measurement

§ S-parameter with a two port vector network analyzer • Magnitude of S21

Ø PCB functionality verification• Angle of S21

Ø PCB phase correction

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Verification and Measurement§ RF Switches Set to Noise Reception

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Verification and Measurement§ RF Switches Set to Antenna Signal Reception

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Verification and Measurement§ Phase offset added by PCB

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Verification and Measurement§ Measurement Setup

• PC• 12V power supply• Signal generator• 28.8MHz clock source

Output signal with the same phase

I/Q ModulatedRectangle

Signal

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Verification and Measurement§ Measurement Results

• Without phase drift compensation

• With phase drift compensation

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Before time, phase and frequencysynchronization

After time, phase and frequencysynchronization

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Conclusion § A four-channel coherent receiver based on the synchronization of RTL-

SDRs has been realized§ The residual frequency error due to the fractional-N PLL has been

successfully compensated from 250 to 1350MHz§ Synchronization shows quite robust performance at 433MHz as long as

the phase drift is continuous

Further Works§ Cooling and shielding§ Measurement at higher frequencies§ AGC for the reference noise signal§ Application demonstration

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Thank You !Any Questions?

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§ Timer § RF Switches§ Clock Distribution§ Noise Source Power Switch

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Hardware and Software ImplementationRF Switches

§ ADG918• Absorptive SPDT RF switch

§ SCA-4-132+• 4-way power divider• Phase unbalance

§ Minimum loss pad • Provide broadband 50Ω to 75Ω impedance matching

must be compensated !

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Hardware and Software ImplementationTrigger Signal

§ SDAT as trigger signal• I2C communication between tuner chip R820T/EEPROM and

demodulator chip RTL2832U only occurs at the beginning of the RTL-SDR configuration

• I2C communication starts with a falling edge at SDAT while SCLK stays high and finishes with a rising edge at SDAT while SCLK stays high

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Hardware and Software ImplementationTimer

§ TLC555• Low power timing circuit• Falling edge-triggered

§ LSF0102• Voltage level translator• Open drain and push pull compatible

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Hardware and Software ImplementationSynchronization Algorithm

§ Latency difference between channels inside of the first processing loop

§ Latency decreases inside of the secondprocessing loop until there is no latencydifference among RTL-SDRs

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Hardware and Software ImplementationSynchronization Algorithm

§ Determine when the antenna signalreception begins

Documents

Time, Phase and Frequency Synchronization of Low-Cost DVB ...nts.uni-duisburg-essen.de/downloads/nt-prakt12/dokum/1531143033... · Communication Systems Time, Phase and Frequency