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S.E. Sem. III [EXTC] Electronic Devices and Circuits I

Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1 Attempt any FIVE questions : Q.1(a) Explain various types of resistors. [5] Ans.: There are two basic types of resistors.

1. Linear Resistors 2. Non Linear Resistors

Linear Resistors : Those resistors, which values change with the applied voltage and temperature, are called linear resistors. In other words, a resistor, which current value is directly proportional to the applied voltage is known as linear resistors. Generally, there are two types of resistors which have linear properties. (a) Fixed Resistors (b) Variable Resistors (a) Fixed Resistors : As the name tells everything, fixed resistor is a resistor which has a

specific value and we can’t change the value of fixed resistors.

Types of Fixed resistors : Carbon Composition Resistors Wire Wound Resistors Thin Film Resistors

Q.1(b) Why gain of BJT is higher than gain of JFET? [5] Ans.: Gain of BJT is proportional to and is large hence gain of BJT is large, whereas gain of

FET is proportional to gm and is of order of milli, hence gain of JFET is small. Q.1(c) What is zero temperature drift biasing. [5] Ans.: Mutual Characteristics of JFET

The operation of JFET is temperature dependent. Hence, when we plot the transfer characteristics of JFET for different operating temperatures, it can be seen that the drain current ID decreases with increase in temperature. The transfer characteristics of JFET for different operating temperature is as shown.

Assume T3 > T2 > T1. One of the important characteristics of JFET is, all the transfer characteristics cross a particular point on the transfer curve. If this point is selected as the operating point of JFET, it can be seen that the drain current IDQ is independent of temperature. This phenomenon by which IDQ is made independent of temperature is called Zero Temperature Drift. The condition for Zero Temperature Drift is |Vp| |VGS| = 0.63 volts.

ID

VGS

DC bias line

0

IDQ = DSI2

Q

slope = 1/RS

VGSQ

IDSS

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Effect of temperature on mutual characteristics There are two factors associated with zero temperature drift.

1) When temperature increases, the lattice atoms gains energy, they vibrate faster, hence collisions between the lattice atom and the carrier increases. Due to increased number of collisions, the mobility of the carrier decreases. Hence ID

decreases with increase in temperature. Experimentally it is seen that ID decreases by 0.7 % of ID.

ID = 0.007 ID … (1) 2) When temperature increases, the junction barrier decreases. The decrease in

junction barrier increases the width of the channel, hence the resistance offered by the channel decreases, hence ID increases. Experimentally it is seen that the increase in ID is proportional to 2.2 mV change in VGS per C.

ID = gm VGS = 2.2 103 gm … (2) At one point on the transfer curve, the decrease in ID due to decrease in mobility

and increase in ID due to decrease in junction barrier will oppose each other, making the drain current independent of temperature. This is the principle behind zero thermal drift.

Q.1(d) Consider a BJT has parameters fT = 500 MHz at IC = 1mA, = 100 and

C = 0.3 pF. Calculate bandwidth of f and capacitance C of a BJT. [5]

Ans.: Given : fT = 500 MHz at IC = 1mA, = 100 and C = 0.3 pF Find : f, C fT = f f = 5 MHz

re = C

26mVI

= 26

hie = re = 2.6 k

f = ie

12 h (C C )

=

12 (2.6k)(C C )

C = 11.9 Rf Q.1(e) Write short note on different types of filters. [5] Ans.: (i) Inductor Filter:

This type of filter is also called choke filter. It consists of an inductor L which is inserted between the rectifier and the load resistance. RL. The rectifier contains A.C components as well as D.C components. When the output passes through the inductor, it offers a high resistance to the A.C component and no resistance to D.C components. Therefore,

L

RL OutputInputVidyalan

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Prelim Paper Solution

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A.C components of the rectified output is blocked and only D.C components reached at the load.

(ii) Capacitor Filter:

In this filter a capacitor is connected across the load during the rise of voltage cycle it gets charge and this charge is supply to the load during the fall in the voltage cycle. This process is repeated for each cycle and thus the repel is reduced across the load. It is shown in the above Figure. It is popular, because of its low cost. Small size, less weight and good characteristics. Useful for load up to 50mA as in transistor radio battery eliminators.

(iii) LC Filter: In inductor filter, the ripple factor is directly proportional to the load resistance. On the

other hand in a capacitor filter, it is varying inversely with the load resistance. Hence if we combine the inductor filter with the capacitor the ripple factor will become almost independent of the load filter. It is also known as inductor input filter, choke input filter. L input or LC-section.

(iv) CLC or Pie Filter:

It consists of one inductor and two capacitor connected across its each end. The three components are arranged in shape of Greek letter Pi. It is also called capacitor input Pi filter. The input capacitor C1 is selected to offer very low reactance to the repel frequency hence major parts of filtering is done by C1. Most of the remaining repels are removed by the combining action of L and C2. This circuit gives much better filter then LC filter. However C1 is still directly connected across the supply and would need high pulse of current if load current is large. This filter is used for the low current equipment’s.

Input Pulsating DC

Charging Discharging

RL

Input OutputRL

L

C C RL OutputInput

L

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Q.1(f) Explain the hybrid pi model of BJT. [5] Ans.: The figure shows hybrid model of a BJT in which : (i) r = It is the resistance offered by forward biased BE junction, given as,

r =

CQ

VTI

: forward current gain, VT : 26 mV, ICQ : DC value of collector current. (ii) The IB is a dependent current source which indicates the collector current of BJT. (iii) As we known that in, BJT we have early effect, because BJT offers finite value of

output resistance ro, given as :

ro = A

CQ

VI

VA : Early voltage of BJT, ICQ : DC value of collector current (iv) gm is known as transconductance of BJT is given as :

gm = CQ

A

IV

Q.2(a) Write short note on DC load line and significance of Q-point [10] Ans.: Concept of DC Loadline : Consider the output characteristics of CE transistor as shown

Saturation region

CC

CC E

VI

R R

Q

cut off region VCE =VCC VCE

Active Region

DC loadline Slope = 1/(RC + RE)

IBQ

VCEQ

ICQ

IC

B

E

Vbe

IB

IC

VCC

C

E

VBE

B

E

C

E

IC

r ro VCC

IB

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Prelim Paper Solution

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Consider a fixed bias or self bias or voltage divider bias circuit using transistor. Apply KVL to the collector side, VCC = C C CE C B EI R V (I I )R VCE = CC C C C B EV I R (I I )R CC C C EV I (R R )

IC = CE CC

C E C E

V VR R R R

This equation is of the form y = mx + c, an equation to a straight line having slope =

C E

1R R

and having y intercept = CC

C E

VR R

and x intercept = VCC.

This line is called DC loadline. It will intercept the output characteristics for a given value of IB at a point called Q point. The significance of DC load line is that it actually indicates region of operation. if it is to be operated s switch then Q point should be chosen in saturation of cutoff region and if it is to be operated as an amplifier then it should be operated in Active region.

Q.2(b) A full wave rectifier using a center tapped transformer with two diodes gives output voltage of 250 V to a resistive load, the current being 75 25 mA. If the ripple factor is 0.001, calculate the specification of the devices and components required fi the filter used are L section LC filter.

[10]

Ans.: VLdc = 250 V, ILdc = 75 25 mA, r = 0.001 L section (LC) filter : Circuit diagram : Range of the load resistance :

RL (min) = Ldc

L(max)

VI

= 3

250100 10

= 2.5 k

RL (max) = Ldc

L(min)

VI

= 3

25075 10

= 3.3 k

RL (min) = 2.5 k and RL (max) = 3.3 k Value of LC : To ripple factor is given by

r = 2

16 2 LC

R1

VB

+VCC

RC

Q

CE RE R2

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with f = 50 Hz, r = 0.001 we have

LC = 2

16 2 r

= 2

16 2(2 50) 0.001

= 1.194 103

Bleeder resistance RB : Let us assume bleeder current to be 10% of maximum current, Bleeder current, IB = 0.1 Maximum load current = 0.1 100 mA = 10 mA

Bleeder resistor, RB = LdcVBleeder current

= Ldc

B

VI

RB = 250

10mA = 25 k

Wattage of RB, WRb VLdc IB = 250 10 103 2.5 W Select RB = 25 k/5 W Calculate LC and select L :

Critical inductance, LC = BR

3 =

325 103 2 50

= 26.5 H

Select L = 30 H, 100 mA Calculate C : We have, LC = 1.194 103

C = 31.194 10

30 = 3.98 105 F

C = 39.8 F Select, C = 47 F/500 V Ratings of the diodes :

Average current through diode = Ldc bI I

2 = 100 10

2 = 55 mA

Iavg = 55 mA The load voltage is the voltage across capacitor C which charges to Vm Volts. With a

very small value of ‘r’, the ripple voltage is small. VLdc = Vm = 250 V PIV of each diode, Vm = 250 V Ratings of transformer :

Secondary rms voltage, Vs (rms) = mV2

= 2502

= 176.7 V

Turns ratio, 1

2

NN

= 230

176.7 = 1.3

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Q.3(a) Obtain expression for gain bandwidth product. [10] Ans.: The small signal high frequency model of CE amplifier with load is as shown :

To determine short circuit current gain,

Aisc = OSC

B

II

, short the load.

The resulting model is as shown, r(k) || rb’c (M ) r (k) Cbe + Cbc = Ci

Aisc = OSC

b

II

IOSC = gm . V

V = Ib . Z = bIy

Z = ci

1r ||

s 1

Z =

Ci1

Sr

y = gm + SCi

V =

b

m Ci

Ig S

IOSC = gm . b

m Ci

Ig S

Aisc = OSC

b

II

=

m

m Ci

gg S

Aisc =

m

Cim

m

gS

g 1g

Aisc =

mg .rf1 jf

……where f = i

12 r C

r = hie = hfe . re =

mg = r . gm

+

b rbb

V Ci r

VS

Iosc

c

e

Ic = gm V

b Ib

b'ar

rbb

bb'eC

Cb’c

r ro

10b

r

Ic = gmV

VS

RL

Vo

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Aisc =

f1 jf

f = ie be bc

12 h [C C ]

|x jy] = 2 2x y

|Aisc| =

2f1f

Case 1: f < f

f 1f

2f1 (neglect)

f

|Aisc|= = constant Pass Band, i.e. gain in pass band remains constant.

Case 2: f = f (cutoff frequency)

Aisc = 2

Case 3: f > f

2ff

|Aisc| =

2ff

= f . f

|Aisc| 1f

In stop band as frequency increases , gain decreases From (1), (2) and (3), the responses are shown : lower cutoff frequency is negligible compared to upper cutoff (f) Bw = upper cutoff (f) The frequency at which amplifier provides unit gain. i.e. |Aisc| = 1 At f = fT |Aisc| = 1 From equation (1)

From graph, fT > f

Tf 1f

2

Av

1

fT f

f(HZ)

(w)cc = f

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Prelim Paper Solution

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2Tf 1

f neglect 1

1 =

2Tf

f

Tff

= fT = . f

fT = Gain BW = Gain BW Product And Gain BW Product (GBP) for an amplifier always remains constant. Q.3(b) Determine IDQ, VGSQ, VDSQ if IDSS = 9 mA and Vp = 3V

for the circuit given in Figure.

[10]

Ans.: IDSS = 9 mA, VP = 3V KVL at gate, 0 Vgs ID RS + 10 = 0 Vgs = 10 ID Vgs = + 0.14 V VDS = VDD ID = 7.58 V Q.4(a) Design single stage BJT CE Amplifier for the following requirements.

AV 100, Zi 3K, VCC = 18 V [15]

Ans.: Given : AV 100, Zi 3K, VCC = 18 V Selection of transistor : We select BC1478 with following parameters, PD max = 0.25 W, IC max = 0.1 A, VCEO = 48V, hfe = 330, hie = 4.5 k, VBE = 0.7 V, VCE out = 0.25 V Selection of bias : We use voltage divider bias with RE partially by passed. Design of RC : Let RC = 10 k

|AV| =

fe C

ie fe E1

h Rh (1 h )R

Let RE1 = 100 ; (1/4)W

RC = 1253 k =

C C

C C

R RR R

RC = 1.432 k RC sat = 1.5 k; (1/4)W

20V

10V

1.8 K

ID = IDSS

2gs

P

V1

V = 9

2D10 I

13

= 9.85 mA

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To determine Q point :

VCEQ = QV2

(mid point bias)

= 9V Let VRE = 10%, VCC = 1.8 V

IC = CC CE RE

C

V V VR

= 4.8 mA

VCEQ = 9V, ICQ = 4.8 mA Determine of RE, VRE = 1.8 = IC RE

RE = RE

C

VI

= 375

but RE = RE1 + RE2 RE2 = 275 RE2 = 270 ; (1/4)W To design R1 and R2, Given, Ri = 3 k, Let Ri = 3.2 k but Ri = RB || (hie + (1 + hfe) RE1)

3.2k =

B

B

R yR y

y = hie + (1 + hfe) RE1 = 37.6 k

R3 = 3.497 k =

1 2

1 2

R RR R

VB = VBE + VRE = 0.7 + 1.8 = 2.5 V

VB =

2CC

1 2

RV

R R

3

1 2

RR R

= B

CC

VV

= 0.1388

R1 = 25.178 k R2 = 4.057 k R1 sat = 27 k; (1/4)W R2 sat = 3.9 k; (1/4)W Design of capacitors : Let f = 20 Hz

fLCC1 = i C1

12 R C

Ri = RB || (hie + (1 + hfe) RE1) = 252 k CC1 = 2.4 F Let CC1 = 10 F; 5V

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Prelim Paper Solution

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fLCC2 = 0 C2

12 R C

R0 = RC + RE = 11.5 k

CC2 = 0.7 F CC2 = 1 F ; 20V

fLCC = E2 E

102 R C

CE = 294 F

CC = 300 F; 5V Design circuit : Q.4(b) For above designed circuit calculate Av, Ri, and Ro. [5] Ans.: From Q.4(a) design circuit, Ro = RC = RC || RE = 1.253 k

AV =

fe C

ie fe C1

h R

h (1 h )R = 10.9

Ri = RB || [hie + (1 + hfe) RCC1] Ri = 3.2 k Q.5(a) For the circuit using JFET as shown in Figure, if IDSS = 6 mA, VP = 6V, rd = ,

Cgd = 4 pF, Cgs = 6 pF, Cds = 1 pF, determine : higher cutoff frequency.

[10]

600 CC1

Vs

3 K

1.2 K

10 V

0.1 F

CS 100 F

CC2

4.7 F

3.9 K

Vo

BC 147B

1 F Vo

10 k

300 F270

100

3.9 k

10 F Vi

27 kR1

1.5 k

18 V

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Ans.: Given : IDSS = 6 mA, VP = 6V, rd = , Cgd = 4 pF, Cgs = 6 pF, Cds = 1 pF Vgs = ID Rs = 1.2 ID = 2.4V

ID = IDSS

2gs

p

V1

V = 2.1 mA

gm =

gsDSS

P P

VI1

|V | V = 1.31 m

|AV|= gm RD RD = 3 k || 3.9 k = 1.09 k |AV| = 2.22

VA2

= 1.57

Ri = 600 Ci = Cgs + (1 + A) Cgd = 18.88 Rf

fHC = i i

12 R C

= 14.05 MHz

Ro = RD || R2 = 1.69 k Co = Cds + Cmo = 5 pF fHC = 18 kHz Q.5(b) Find Z0, Zi, AV, Ai for the network given :

[10]

Ans.: AV =

fe c

ie fe E1

h Rh (1 h )R

= 4.55

Ai = hfc 3

3 ie fe E1

RR h (h h )R

= 100 (0.72) = 72

Zi = RB || (hie + (1 + hie) RE1) = 89.6 k R0 = RC = 5.6 k Q.6 Write short notes on (any FOUR) : [20] Q.6(a) Write short note on Millers Theorem. [5] Ans.: Statement : It states that, when impedance Z is connected between input and output of

an amplifier that provides gain Av, then equivalent circuit is obtained by connecting Zmi (miller’s i/p impedance) at input and Zmo (miller’s o/p impedance) at output.

CERE2

RE1 1.2 k

470

5.6 k

V0330 k

CC

Vi

VCC = 20 V

hfe = 100 hie =1K8

|AV|

2.221.57

14.59 f (Hz)

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Prelim Paper Solution

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i.e.

From fig. (1)

I1 = 1 2V VZ

From fig. (2)

I1 = 1

mi

VZ

Equating…. 1

mi

VZ

= 1 2V VZ

mi

ZZ

= 1 2

1

V VV

= 2

1

V1

V

mi

ZZ

= 1 Av

Zmi = v

1. Z

1 A

For CE and CS amplifier, a) For CE amplifier,

Zmi = v

Z1 A |

…(1)

and Zmo Z …(2)

From fig. (1)

I2 = 2 1V VZ

I2 = 2

mo

VZ

2

mo

VZ

= 2 1V VZ

mo

ZZ

= 1

2

V1

V

mo

ZZ

= v

11

A =

v

v

A 1A

zmo =

v

v

A. Z

A 1

…..gain of CE is (inverted) Av

v

v

AA L

and Av is very high

Av >>>> 1

Q.6(b) Write short note on stability factors of various biasing techniques of BJT. [5] Ans.: (a) Temperature stability factor SI/S

It is defined as the ratio of the change in the collector current to the change in the leakage current, keeping and VBE constant.

IS =

C

CO

II

, , VBE constant.

(b) Voltage stability factor SV/S It is defined as the ratio of the change in the collector current to the change in the base emitter voltage keeping ICO and constant.

VS =

C

BE

IV

, COI , constant.

I1 I2 Amp.Av

o/p i/p

V1 Zmi Zmo V2 I1 I2

Amp.Av

Z

o/pi/p

V1 V2

Fig. : (1) Fig. : (2)

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(c) stability factor S /S It is defined as the ratio of the change in the collector current to the change in the value of , keeping COI and VBE constant.

S =

CI , COI , VBE constant.

the total change in CI is given by CI = IS COI + VS VBE + S Q.6(c) Comparison of BJT CE ,CB and CC amplifier [5] Ans.:

Mode Type Shift Av Ai Zi/Ri

CE Inverted 180 fe c

ie

h .Rh

= gm . Rc

large

= hie 20 500

large

hie = Moderate

(in k)

CB NonInverted 0 gmRc large = 0.9 0.99 small

re =

r

10 100 small

CC Buffer 0 Av = 1 (ideal)

0.9 0.99 + 1 large

r + (1 + )RE (ideal)

Q.6(d) Write short note on Zener as Regulator. [5] Ans.: The circuit diagram of zener shunt

regulator is as shown. The zener is connected in shunt with the load, and zener is kept reverse biased. The unregulated input Vi must be greater than V0 , atleast by 5 to 10 V. The resistor RS will ensure a minimum current through zener when Vi = Vi min , keeping the zener in ON state. Also it limits the maximum value of zener current when Vi = Vi max.

In the ON state, zener maintains a constant voltage across its terminals. Therefore V0 = Vz. Since Vz is a stable zener reference source, the output voltage is stable and hence the load gets a constant voltage.

Q.6(e) Write short note on JFET as VVR. [5] Ans.: In most linear applications of field effect transistors, the device is operated in the

constant current portion (Pinchoff Region) of its output characteristic. Now, consider FET operation in the region before pinchoff, where VDS is small. In this region FET behaves as a voltage controlled resistor; i.e. the drain to source resistance is controlled by the bias voltage VGS. In such an application the FET is also referred to as a voltage variable resistor (VVR) or voltage dependent resistors (VDR).

Vi Vz V0 RL

IL Iz

I RS

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Prelim Paper Solution

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Figure above shows the low level bidirectional characteristics of JFET. The slope of these

characteristics gives rd as a function of VGS. Figure drawn above has been extended into the third quadrant to give an idea of device linearity around VDS = 0.

The variation of dr with GSV is given by, dr =

0

GS

r1 KV

where r0 is the drain resistance at zero gate bias, K is a constant dependent upon JFET type, VGS is the gate to source voltage.

0.1 0.2 0.3

-0.1-0.2-0.3

-3V

-2V-1V

VGS = 0

VDS (Volts) -VDS (Volts)

ID (mA)

ID (mA)

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