TI Digital Signal Processors · 2020. 9. 17. · TI Confidential – NDA Restrictions SoCs 2 Single-core to Multicore DSP (C5x, C66x, C674x, C7x) ARM (Cortex-A53, A72 cores) Compute

TI Confidential – NDA Restrictions

TI Digital Signal Processors

Scalable portfolio for aerospace & defense

9/8/2020


SoCs

2

Single-core to Multicore DSP (C5x, C66x,

C674x, C7x) ARM (Cortex-A53, A72

cores) Compute

Safety

& Security

Secure-boot, run-time security, tamper

protection and high-security modules

Deep Learning

& Accelerators

Power-optimized neural network

accelerators, radar accelerators, vision

accelerators, audio DSP, and GPU

Analog

Dual-core to quad-core Arm Cortex-R5F

with optional Lock-Step support

High-level integration of high-performance

ADC, DAC, comparators and PWM

Control

Connect USB3, PCIe Switch, Ethernet Switch,

Industrial Protocols, CAN-FD, and more

Processors overview

Scalable, cost-optimized portfolio with accelerators, analog integration, robust connectivity,

security and functional safety designed for automotive and industrial markets

Power-optimized design ASIL-B/D and SIL2

functional safety

-40 to 140C temperature

range on products Q100 automotive qualified

options

Scalable platform with common software development kit and pin-to-pin compatibility in common packages

Unified Software Platform Simplified tools (SysConfig) and libraries

(DSPLIB, TIDL, ...) to accelerate

development and performance entitlement

Open source device enablement for

Mainline Linux, RTOS and Bare Metal

3P software support – AUTOSAR, QNX, …


Industry requirements

Long product lifecycles

Ability to withstand harsh environments

Compliance with strict defense and space certifications

Higher density of features & products

TI delivers

Continuity of supply and options for anti-obsolescence

Enhanced Reliability: Extended Temperature & High Voltage, protection features

Hi-rel, EP and space qualified devices

Enhanced integration & advanced packaging

TI’s commitment to A&D customers Delivering solutions that meet harsh environment and long operating life standards, while maintaining continuity of supply


Full system solutions make TI your one-stop shop

for software, tools and support

Power

management

Signal

conditioning

Temperature

Pressure

Position

Speed

Flow

Humidity

Sound

Light

Proximity

The real

world

Analog signal

conversion

to digital

Digital signal

conversion

to analog

Signal

conditioning

Display/interface

Clocks & timers

Embedded

processor

Wireless

connectivity


DSP Aerospace & Defense markets

5

PMR / LMR, Radio

Scalable portfolio

>30 Hi-Rel DSPs

Space Radar & Imaging Avionics Smart Munitions

Scalable, Real-time Solutions • Single core DSPs

• System on Chips (SoCs)

• Up to 320 GFLOPS with TI DSP

• Up to 100K DMIPS with Cortex-A Core

• High speed peripherals

• Code and tools compatible

Size, Weight and Power • Highly integrated devices

• Efficient processing solutions

• Low power operation (<200mW)

• 2.7 GFLOPs at ~750mW

• 320 GFLOPS at ~20W

Reliability and Longevity • Long Aerospace & Defense history

• Extended temperature and –EP

range of products available

• Low SER and FIT rates

• Device longevity

Space qualified devices available.

Actively working to expand –EP portfolio

http://www.ti.com/lsds/ti/processors/applications/avionics-and-defense/avionics-and-defense-radar.page


TI’s Range of Product Solutions

6

Commercial Q100 EP QMLQ SEP QMLV

QMLV QMLV-RHA

Packaging Plastic Plastic Plastic Ceramic Plastic Ceramic Ceramic

Single Controlled

Baseline No No Yes Yes Yes Yes Yes

Bond Wires Au/Cu Au/Cu Au Al Au Al Al

Is Pure Sn used? Yes Yes No No No No No

Production Burnin No No No No No Yes Yes

Typical

Temperature Range -40ºC - 85ºC -40ºC - 125ºC

-55ºC - 125ºC

(majority) -55ºC - 125ºC

-55ºC - 125ºC

(majority) -55ºC - 125ºC -55ºC - 125ºC

Radiation (SEL/SEE) No No No No Yes Yes Yes

Radiation (TID) Lot

Acceptance (RLAT) No No No No Yes (20krad) No Yes

Outgassing tested

per ASTM E595 No No No N/A Yes N/A N/A

Lot Level Temp

Cycle No No No Group D Lot Level Group D Group D

Lot Level HAST No No No N/A Yes N/A N/A

Multiple wafer lots

per reel possible Yes Yes Yes No No No No

Life Test Per Wafer

Lot No No No No No Yes Yes

Quality / Reliability / Cost


Hi-Rel Enhanced Products (-EP) Space

SMV320C6727B-SP

SMJ320C6701-SP

DSP Product Portfolio for Aerospace & Defense

SM320C6201-EP

SM320C6701-EP

SM320C6711D-EP

SM320C6727B-EP

OMAPL138B-EP

SM320VC33-EP

SM320VC5510A-EP

SM320VC5507-EP

SM320C6424-EP

SM320C6415-EP

SM320VC5421-EP

SM320C6712D-EP

SM32C6416T-EP

SM320DM355-EP

Released

SM320VC5416-EP

TI Radiation Reports available. Visit TI.com or speak

with your account manager for more details.

OMAP3525-HIREL

SM320VC5510A-HIREL

SM320DM6446-HIREL

OMAP3530-HIREL

SM320DM642-HIREL

SM320C6472-HIREL

SM320C6678-HIREL

SM320C6457-HIREL

SM320C6748-HIREL

SM320DM6446-HIREL

All roadmaps are subject to change based on market direction, resource limitations, etc.

* -HIREL generally indicates part will be the same as an EP product without extended HAST or a V62 number

SMOMAPL138B-HIREL

http://www.ti.com/product/SMV320C6727B-SP



http://www.ti.com/product/SMJ320C6701-SP



http://ti.com/


Enhanced Product 2 Classification -EP2

8

• Targeted to have a cost and development timeline that is less than a

traditional –EP device

• Addresses key concerns of commercial parts: – Reduces tin whiskering

– Increased temperature range

• Key differences between –EP and –EP2 – Solder bumps on wafer remain same composition as commercial device with tin content.

– Same leadframe as commercial device variants.

– Balls/lead wires on the device will match –EP requirements.

• All other aspects the same including device qualification requirements.

Always willing to discuss traditional –EP or extended temperature

needs with our customers for current or future devices.


Texas Instrument’s DSP Cores

64-bit DSP

16x bandwidth

5x floating point

512bit Vector SIMD

C code compatible

Object code compatible

Increased

Fixed and float performance

Improved complex arithmetic

Improved matrix computation

Advanced VLIW

architecture

2x registers

Enhanced

floating-point

Object code compatible with C64x,

C64x+, C67x and c67x+

Fixed and Float

Four 16-bit or

eight 8-bit MACs

Two-level cache

SPLOOP

16-bit instructions

Flexible mem

architecture

iDMA

C674x

C66x

C64x+ C64x C67x

C67x+

FLOATING-POINT FIXED-POINT

Perf

orm

an

ce i

mp

rovem

en

t

C7x


10

DSP Single Core Processor Portfolio

C6748/6/2 • 1x C674@ 456 MHz, <1W • EMAC, USB2, McASP • 13x13, 16x16mm

Concept Development

C6747/5 • 1x C674@ 456 MHz, <1W • EMAC, USB2, McASP • 16x16mm

Production D

SP

-On

ly

DS

P +

AR

M

66AK2G12 • 1x C66@ 600MHz, 1GHz • 1x A15@ 1GHz, GbE • QSPI, ECC, ASRC • 21x21mm

OMAP-L137 HT

OMAP-L137 • 1x C674@ 456 MHz, <1W • 1x ARM9@ 456 MHz • EMAC, USB2 • 16x16mm

OMAP-L138 - EP

OMAP-L138 • 1x C674@ 456 MHz, <1W • 1x ARM9@ 456 MHz • EMAC, USB2 • 13x13, 16x16mm

Audio support

CC55x

C5517 •1xC55x, 200 MHz •320KB, EMIF •USB, McBSP, LCD •10x10mm

Next Gen OMAP-L138

in development.

Multiple R5F + C66x DSP in development

New C66x Device in development


OMAP-L138 Functional Diagram

11

Link to OMAPL138B on TI.com

Link to OMAPL138B-EP on TI.com

Link to SMOMAPL138B-HIREL on TI.com

https://www.ti.com/product/OMAP-L138

https://www.ti.com/product/OMAPL138B-EP



https://www.ti.com/product/SMOMAPL138B-HIREL




12

DSP Multicore Portfolio

C667x • 4-8x C66@ 1.25 GHz • 8MB of L2 • PCIe, GbE, SRIO • 24x24mm

C665x • 1-2x C66@ 1.25 GHz • 3MB L2, 1.5-3W • PCIe, UPP, GbE, SRIO • 21x21mm

Concept Development

66AK2H14 • 8x C66@ 1.2 GHz • 4x A15@ 1.4 GHz • PCIe, USB3, 10GbE, SRIO • 40x40mm

Production

DS

P-O

nly

D

SP

+ A

RM

66AK2E05 • 1x C66@ 1GHz • 4x A15@ 1GHz • PcIe, USB3, 1-GBE w/switch • 27 x 27mm

Sampling

V – visualization needed (with GPU)

A – analytics processing only (no GPU)

7th generation DSP C7x with JacintoTM 7 Processors

TDA4V Mid/DRA8x • 1x C7x, 2xC66x (112 GLFOPS) • 2x A72 (25K DMIPS) • 1x MMA Deep Learning (8 TOPS)

• 24x24mm

Many more multicore

C7x Devices in

Development


TMS320C6678/4/2/1 Functional Diagram

Tera

Net

Security AccelerationPac

Packet AccelerationPac

Debug DDR3 72b -1600

512KB L2 Per C66x Core

1G Ethernet Switch

40 nm

Multicore Shared Memory Controller

4MB MSMC SRAM

011100

100010

001111

EMIF16

1GbE 2x

EMIF and IO High Speed SerDes Lanes HyperLink

4x

I2C UART

GPIO x16

PCIe 2x

SRIO 4x

+ * - <<

C66x DSP

SPI

TSIP x2

System Services

Power Manager

Debug

System Monitor

EDMA PktDMA

• Cores & Memory

– 8/4/2/1 C66x DSP 1GHz-1.25GHz

– 320 GMACs, 160 GFLOPS

– 8MB on chip memory w/ECC

• Multicore Infrastructure

– Navigator with 8k queues, 1600 MIPS

– Non blocking Network on Chip

– Multicore Shared Memory Controller reduce external memory access

latency

• Switches

– 1GbE: 2 external port switch

• Network, Transport

– Crypto: IPsec, ESP, AH Tunneling, SRTP

– Packet Acceleration – Multiple IP Addr, 1.5Mpps @ full wire-rate, QoS

support

• Connectivity – 82Gbps

– HyperLink(50), PCIe(10), SRIO(20), 1GbE(2)

• Power Optimized

– <10W at 1GHz nominal temp

– Advanced power optimization including Smart Reflex

• Packaging: 24mm x 24mm

+ * - <<

C66x DSP

+ * - <<

C66x DSP

+ * - <<

C66x DSP

+ * - <<

C66x DSP

+ * - <<

C66x DSP

+ * - <<

C66x DSP

+ * - <<

C66x DSP

Link to TMS320C6678 on TI.com

Link to SMS320C6678-HIREL on TI.com

https://www.ti.com/product/TMS320C6678

https://www.ti.com/product/SM320C6678-HIREL




Compute Performance C674x vs C66x vs C7x

C674x C66x C7x

64-bit Memory Addressing No No Yes

Vector size (SIMD capability) 32 128 512-bits

Fixed point 16x16 MACs per cycle 8 32 128

16-bit Fixed Point Vector Adds per cycle 4/3 cycle 8/3 cycles 32/cycle

Floating point operations per cycle 6 16 80

Load/store bandwidth 2x64-bits 2x64-bits 2x512-bits

Total bandwidth to memory 64 bits 128 bits 2048-bits

Power Consumption Lowest Middle Highest

• C66x Instruction Set

– The C66x ISA builds on the C674x ISA, expanded

to include complex & matrix operations.

– Instructions are tuned to audio, vision, industrial

communication and broad market uses.

• C7x Instruction Set

– The C7000 ISA builds on the C6000 ISA, expanded to

include vector operations

– Most operations are supported in 8-bit, 16-bit, 32-bit and

64-bit forms, and both Signed and Unsigned versions are

provided for each type


Control Efficiency

Control Features C66x C7x Benefits

Unprotected Pipeline Mode Yes Yes Traditional VLIW Exposed Pipeline

Protected Pipeline Mode No Yes Control Code Efficiency

Speculative Loads No Yes Control Code Efficiency

Branch Prediction No Yes Control Code Efficiency

Data Tracking Scoreboards No Yes Control Code Efficiency

Precise Interrupts No Yes Enable Virtual Memory Management

• Control code performance improves by ~30% over C66x


.L Unit

.S Unit

.D Unit

Register File

Register File

.M Unit

.N Unit

C7x Evolution

.L Unit

.S Unit

.D Unit

.M Unit

64

.L Unit

.S Unit

.M Unit

64

Register File Register File

Intra-vector Unit

Register File

.D Unit

.M Unit

Register File

Register File

512

Streaming Engine AGEN

LUT

HIST

.M Unit

.N Unit

C66x C7x

• Expand B-side to 512-bit wide

• Split M-unit into two parts to maximize usage of available multipliers • New Intra-vector Unit for vector data alignment and other functions of a whole vector • Additional Registers, and Streaming Engine to supply vector data • Parallel look-up table and Histogram hardware, and 6-D Address generation


Higher Performance

• 512-bit wide vector SIMD datapath

• New “Streaming Engine” feature removes cache miss

penalties on data fetch, performs data formatting and 6-D

addressing

• Combined Scalar and Vector cores, suitable for variety of

applications

• Vector floating point capability

• Wide vector processing including intra-vector operations

• Built for high throughput and large data sets

• Improved control code efficiency

Software Ease of Use

• C-code compatible with C66x software installed base

• Native OpenCL and OpenMP support

C7x CPU Overview

L1P EDC Prefetch

1024bit 512bit

512bit

C7x Core

New or improved from C66x / EVE

.D 512b

.S 64b

.L 64b

.M 64b

Emulation Fetch Execute Dispatch

.D 512b

.S 512b

.L 512b

.C 512b

Debug Fetch Execute Dispatch

Register Files

Streaming Engine

.M 512b

Register Files

Scalar Vector

.N 512b

.N 64b

Debug.

Intc

Dynamic

Power Ctrl

EDC

DMA

Prefetch

Firewall

MMU L1D EDC LUT/HIST

L2 Controller


C7x Caches & Memory System

18

C Scalar Vector

L1I

L1D

L2

MSMC

C7x Core

Safety Prefetch

Safety Hist/LUT

Safety

Firewall DMA

Coherence

Improved Performance & Memory Bandwidth

Streaming Engine

Coherency & Virtualization

Functional Safety

Histogram and Look-up Table Acceleration

Control Code Efficiency

Safety

Streaming

Engine

MMU

Safety

Security & Firewall

C66x Core

Scalar


Performance & Memory Bandwidth

• 2x C7x-MSMC B/W at ½ the wires

19

C Scalar Vector

L1I

L1D

64 bit

512 bit

SE

512 bit

64 bit

512 bit

512 bit

2048 bits Total Mem B/W

1024 bits Load / Store

L2

512 bit 512 bit

512 bit 512 bit

512 bit 512 bit

MSMC

C7x-MSMC I/F

512 bit

C7x Core

1024 bits Streaming Data • 1024 bits data from Streaming Engine

• 1024 bits Load / Store B/W

- 8x compared to C66x

• 2048 bits Total Memory B/W

- 16x compared to C66x

• Scalar Side for C66x compatibility

• Control code lift by L1I Prefetch

accommodating Branch Prediction


Coherency & Virtualization

• Internal & External Coherency

• SE -- L1D Cache

• L2 DMA -- L1D Cache (C66x)

• L2 -- L3 Cache, MSMC

• L2-- DDR, ARM, DSP

20 20

CACHE L1D SE

SRAM CACHE L2

SRAM CACHE MSMC

DDR DSP ARM

DMA SNOOP

Scalar Vector C7x

SNOOP


C7x Functional Safety

21

C7x Safety

PBIST

CPU Illegal Opcode Detection

SECDEC on all SRAM’s for lower

FIT rate

Error Injection to verify Customer software and

Safety logic

Protection on pipeline & datapath

registers

LBIST


Streaming Engine • Automated Data Prefetch Engine (forwarding and not transferring)

– After programmed, forwards data from L2 and beyond directly to CPU boundary (C7x)

– Communicates with L2 memory controller for requests beyond L2 (L3, DDR)

– Supports data formatting: element promotion, decimation, duplication, Matrix transpose loads, predication, endian conversion, Complex number swap, lane-order reversal

– Multi-dimensional (up-to 6D) address generator built in

– DMA-like engine bolted onto the front end of the DSP

• No intervention by the CPU required while data is streaming

– Direct Connection to L2 – handles large data sets

– No L1D Cache thrashing during DSP intensive loops

• Up to 1024-bits every cycle

22

C7x Core

Streaming

Engine 512 bits

512 bits

L1D 512 bits

512 bits

L2

512 bits

512 bits

512 bits

512 bits

1024 bits Streaming Data

512 bits

512 bits

512 bits

512 bits


Performance benchmarks

• Performance relative to c66x observed to be

generally 8x-10x faster if not more

– Some operations have >20x improvement

• The results on the right do not factor in c66x

cache misses

23

Improvement over C66

Image Gradients 10.98

X/Y Grad, Mag, Orientation, Sobel X/Y

Transforms 11.01

Integral Image, Hough Lines

Filtering 18.09

Convolution, median, Gaussian

Features 18.80

Fast9, HOG, Harris score

Optical Flow 3

LK tracker

Morphology 25.71

Erosion, Dilation

FFT 5.58

1024 pt, 32bit complex FFT Overall 12.12


C66x code porting to C7x

• C-code compatible with C66x software

installed base

• Open CL support

• C7x : 8x-12x of C66x performance

Ported C66x Code

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Out of the box Targeted optimization C7x native


Jacinto Processors for Aerospace and Defense

Jacinto™ 7

Processors

Edge Compute /

Communication

Grid infrastructure

Edge Compute with

Vision Analytics &

visualization

DRA829

TDA4VM Unmanned vehicle and robots, Camera and vision systems, Smart munition, Surveillance systems …

C7x + A72s + R5s

C7x + A72s + R5s +

Vision + AI accelerators

Un

ified

So

ftware

Pla

tform

Fu

nctio

nal S

afe

ty

Ruggedized Communication, Control systems, Data concentrator ...

Control Panels In-flight entertainment

Sec

ure

Bo

ot




• Accelerating key functions lowers power – DSP for Computer Vision

– Vision Processing

– Video, Graphics

– Deep Learning

• Industry’s most efficient DL architecture – Enables passively-cooling designs

– 5x Efficiency of competitors

– 90% utilization due to smart memory system

• Automotive Quality-ready process technology – Power reduction is achieved through smart

architecture, not process

• Integrated SoC optimizes system design – key functionality integrated into SoC

• Supports SIL-3 on safety MCU, integrated ISP, on-chip hardware acceleration, ethernet and PCI switch

– Lower component count lowers total system power and cost

Jacinto 7 Architecture Designed for Power Efficiency

High speed interconnect 16nm FF

ASIL D

C7x DSP

32k/48K L1 512KB L2

ASIL B

Po

we

r is

ola

tio

n

Security acceleration Crypto: AES, 3DES, SHA, PKA, RNG

Encode Decode

Video acceleration

Encode Decode

Ethernet switch Up to 8 Ports ETHERNET

Audio acceleration HD ATL ASRC

Vision acceleration Vision ISP

w/ LDC

Dense Optical

Flow

Stereo Disparity

Estimation

Arm Cortex A7x

48k/32K each

Arm Cortex A7x

48k/32K each

1M shared L2

Rogue 8XE GPU

Display sub-system

1x DP/eDP, 1x DSI

Safety MCU

DMSC Device Management &

Security Controller

Hardware Diagnostics

CRC

RTI

ESM

DCC

BIST

Arm Cortex R5F

32K/32K L1

64KB RAM

Arm Cortex R5F

32K/32K L1

64KB RAM Lock

Ste

p

1MB SRAM

2x ADC

3x I2C* 2x UART*

3x SPI* 2x I3C*

UDMA GPIO

2x

RGMII/RMII

Capture sub-system

2x CSI2 x 4 DL

GPIO

IPC

IOMMU

UDMA

SMMU Debug Timers

WDT

System services

Hardware Diagnostics

Connectivity Network

4x PCIe 14x

6 Pin 4096FS

Serial

1x I3C 1x SDIO

8x McSPI 10x UART

12x McASP

7x I2C

MMA 32k/32K L1 288KB L2

C66xDSP

MMA - + * =

32k/32K L1 288KB L2

C66xDSP

MMA - + * =

8 MB L3 RAM w/ECC and Coherency 011100

100010

001111

32b LPDDR4/4x-3732 +ECC

Arm Cortex R5F

16K/16K L1

64KB RAM

Arm Cortex R5F

16K/16K L1

64KB RAM Lock

Ste

p

Arm Cortex R5F

16K/16K L1

64KB RAM

Arm Cortex R5F

16K/16K L1

64KB RAM Lock

Ste

p

0.5 MB SRAM

Storage

1x UFS 2.x 1x SD 3.0

1x eMMC5.x 2x USB


Multi-core Shared Memory Controller Data Routing Unit (DRU) Data L3$/ 8 MB SRAM

Programmable cores Mid/hi level object processing, decision making &

customer differentiation, feature extraction, classification

Configurable HWA Low level brute force pixel pre-processing

Color filter array (CFA), color convert, wide dynamic range (WDR), filtering, scaling, depth, motion

Designing ICs with system level performance in mind

Auxiliary MPU

Image capture

Flexible RAW CFA Any 2x2 CFA pattern

Wide Dynamic Range (WDR/HDR)

Flexible WDR format, 3 exposure

12 bit pipe

Vision pre-processing

Pixel Remap / Distortion Correct

Edge Preserving Noise Filter

12 bit pipe

Image Pyramid Luma + Chroma

Fractional bi-cubic/bi-

linear ROI Support

Distance & motion processing

WDR

Image

Stereo

Disparity

: Depth

Dense

Optical Flow :

Motion

MPUs AMPUs HWAs

Ou

tpu

t

Deep Learning and Perception

DSP Scalar

* +

<< - MMA

Vector

Up to 3 MB L2$

…

Nx

CSI2

GPUs

DDR EMIF

Up to 3x CSI-2

Up to 48 virtual channels, 30 gbps


28

C66x DSP C7x DSP

DSPType True 32 bit

32bit/64bit floating point types

6bit/32bit complex types

True 64 bit

32bit/64bit floating point types

6bit/32bit complex types

Functional Units 8 functional units (.L1/.L2, .S1/.S2, .M1/.M2, .D1/.D2) 12 functional units (.L1/.L2, .S1/.S2, .M1/.M2, .N1/.N2 .D1/.D2, .C, .P)

Data paths 2 x 64 bit , 64 bit cross path 64 bit + 512 bit + 2x512 (read only), 64 bit cross path

Registers 32x2 – 32 bit registers 16-64 bit global, 24-64 bit local, 16-512 bit global, 24-512 bit local, 8-64 bit local (.P)

Cache 32KB L1P + 32KB L1D, 256KB L2 32KB L1P + 32KB L1D + 16KB L1SRAM, 512KB L2

Multipliers 32 -16bit fixed, 8 – 32bit fixed / floating 128 - 16bit fixed, 32 – 32bit fixed / floating

Operations 32-GMAC, 16-GFLOPS at 1 GHz 128-GMAC*, 80-GFLOPS at 1 GHz

Transfer engines IDMA (2 channels),1D – 32bit Streaming Engines (2 sets), 6D – 512bit, read-only

Coherency Coherent with L2 Fully coherent with L2, L3, DDR

Safety ECC – SED, L1 ECC – SECDED, L1/L2, SE FIFO

SIMD Packed SIMD (8b, 16, 32b, 64bit)

Inter or Vertical SIMD (.L, .S, .M, .D)

Packed SIMD (8b, 16, 32b, 64bit)

Inter or Vertical SIMD (.L, .S, .M, .N, .C, .D)

Intra or Horizontal SIMD (.C)

HW Acceleration SPLOOP HW NLC (Nested Loop Controller), branch predictor

Lookup Table, Histogram

C66x vs C7x - Summary

*Excluding MMA mac


Jacinto 7 multi-chip connections

Jacinto 7 Jacinto 7

Ethernet Ethernet

PCIe PCIe

HyperLink™ HyperLink™

RGMII

SGMII

PCIe

HyperLink™

JESD204C to

PCIe FPGA

TI Information – NDA Restrictions

Processor SDK RTOS: Maximize Software Reuse

May be used “as is” or customer can implement value-add modifications

Needs to be modified or replaced with customer version

No modifications required

CSL

TI Platform

Network

Dev Kit

Demo Application

TI Demo Application on TI Evaluation Platform

IPC LLD

EDMA, Etc

Tools

(UIA)

CSL

Custom Platform

TI Demo Application on Customer Platform

IPC LLD

Network

Dev Kit

EDMA, Etc

Tools

(UIA)

Demo Application

CSL

Custom Platform

Network

Dev Kit

IPC LLD

EDMA, Etc

Tools

(UIA)

Customer Application on Customer Platform

Custom Application

CSL

Next Gen TI Platform

Network

Dev Kit

IPC LLD

EDMA, Etc

Tools

(UIA)

Custom App on Next Generation TI SOC

Platform

Customer Application

Platform Migration Application Migration Future Proof

Software may be different. But API remains the same

(CSL, LLD, etc.)

TI Information – NDA Restrictions

Thank You for your Time

Documents

TI Digital Signal Processors · 2020. 9. 17. · TI Confidential – NDA Restrictions SoCs 2 Single-core to Multicore DSP (C5x, C66x, C674x, C7x) ARM (Cortex-A53, A72 cores) Compute