IEEE Transactions on Nuclear Science, Vol. NS-31, No. 6, December 1984

THIRTY MEGARAD CMOS GATE ARRAY FOR SPACECRAFT APPLICATIONS

Henry D. VossLockheed Palo Alto Research Laboratory, Palo Alto, CA. 94304

Larry Roffelsen and Charles HardageCalifornia Devices, Inc., San Jose, CA. 95112

Frank C. JonesNational Semiconductor, Inc., Santa Clara, CA. 95051

ABSTRACT

The recent development, testing, qualificationand integration for spacecraft applications of a

general purpose, 30 Megarad-hard, CMOS logic gatearray having 3000 transistors is reported. Fabri-cated on the National Semiconductor, Inc. class Sradation-hard line, the gate array operates at >3 MHz

(OV) after 107 rad(Si) total dose from a Co60source. The threshold voltage change is 0.2 volts(0.5 volts) for the n-channel (p-channel) devicesunder IOV bias conditions. The rad-hard process dfthe CDI gate array family is mask compatible with theconventional process for cost effective semicustomdesign. The rad-hard array is presently operatingin-orbit on the AMPTE satellite and is planned forinstruments to be flown on the CRRES and UARSsatellites.

INTRODUCTION

Sophisticated and reliable data processing isrequired in state-of-the-art satellite instrument-ation to improve flight hardware performance whilereducing circuit densities and cost. The maturingfeatures of the low power CMOS logic gate array

family affords new solutions to the previouslycomplicated, costly, and long development cycleassociated with fully custom manufacture. This paper

reports on the logic-gate array characteristics,fabrication process modification, radiation test

results, and qualification assurance plan for a 3000transistor logic array circuit designed by Lockheedand produced by California Devices, Inc. in conjunc-tion with National Semiconductor, Inc. This now

proven gate array and radiation-hard process are

available to other companies for rad-hard appli-cations.

A logic gate array is an integrated circuitwhich usually contains thousands of transistorsordered into a uniform array on a chip with assoc-

iated I/O buffers, interconnect pathways and otherspecial components (Figure 1). These arrayedintegrated circuits are mass processed up to, but not

including, the unique circuit interconnect level.For each specific circuit the interconnect layer isthe last process step in manufacturing so a singleradiation hardened wafer can provide the circuits formany different applications. Since these gate arrays

have special provisions for interconnect, virtuallyunlimited circuit possibilities are available. Thefamily of metal gate CMOS gate arrays produced byCalifornia Devices, Inc. have circuit complexities

that range from 240 to 3500 CMOS transistors . The

family has available devices which range in pin countfrom 31 to 72 pins (Table 1).

Total dose testing to 108 rad(Si) was ggrformed

using the National Senconductor certified Co

Table 1. CDI Series Rad-Hard Metal Gate CMOS Arrays.

Part Available Available OutputNumber Gates* Pins LSTTL

CDI 1000CDI 2000CDI 4000CDI 6000CDI 8800

100200420600880

3040626468

1416322420

BuffersTTL

1016182840

* A gate is defined as four CMOS transistors for

reference only. This is equivalent to a two inputNAND or NOR logic gate.

radiation source. Both in situ and post irradiation

tests were conducted. Dose rate effects were

inferred for the gate array circuit based on test

data of similar complexity rad-hard circuit designsprocessed on the National Semiconductor, Inc.

rad-hard line. Wafer lot acceptance testing was

performed using method 5007 of MIL-M-38510. All

circuits were subsequently tested and screened to

MIL-STD-883 class B.

I

Figure 1. A corner view of the rad-hard gate arrayshowing the the IO/buffers and inter-

connect pathways.

PROCESS DESCRIPTION

The mask geometries of the four micron longmetal gate family allow operation over a wide rangeof power supply voltages (3V to 15V). Speeds equalor exceed those of the 4000 B series SSI/lfSI family.With a 15V power supply a two input gate delay is 15

0018-9499/84/1200.1364$1.00l1984 IEEE

1364

nanoseconds (250C) for a fanout of two under worstcase processing parameters. At 5 volts the gatedelays are less than 40 nanoseconds. Although thesespeeds are relatively slow compared to VHSIC goalsthe metal gate process is extremely radiation-hard,reliable, rugged and achieves high wafer yields. Itthus serves as a new and cost effective solution forreplacing entire printed circuit boards (whichconsist of 20 to 100 SSI/MSI 4000 B Series CMOS IC's)with a single semicustom gate array.

The process parameters and mask design rules ofthis family are compatible with the radiation-hardwafer fabrication line at National Semiconductor,Inc. However, special precautions were taken toextend the gates of the p-channel devices to overlapthe p-well to prevent a possible latch-up condition.

Products hardened to withstand > 10 Megaradswere the result of an intensive multi-year researchand development program between National Semi-conductor, Inc. and Sandia Laboratories. Thisprogram has enabled National Semiconductor, Inc. tooffer radiation-hard processing of the CaliforniaDevices, Inc. metal gate arrays.

Gate Oxidation

To minimize both the radiation-induced positiveoxide charge and formation of Si-SiO2 interface

states, a dry oxidation step was used. The gateoxide was thermally grown in a dry oxygen atmosphereat 1000°C, followed by a nitrogen anneal to produceoxides which have a high degree of resistance toionizing radiation effects as well as excellentpre-radiation MOS characteristics.

Metal ization

The oxide gate thickness is 750 2, the metal-

ization thickness 11900 R and the glassivation

thickness 9126 i. Use of a non-E-beam metallizationtechnique circumvented the problem of high thresholdshifts due to irradiation under zero and negativegate bias associated with soft X-ray damage. Forthis reason, induction heated evaporation of aluminumwas used to fabricate the radiation-hardened CMOSgate array.

Substrate and P-Tub Surface

In anticipation of threshold voltage shifts, theradiation-hardened CMOS devices were designed withthe initial value of VTN as high as possible and VTPas low as possible without sacrificing pre-radiationcircuit performance. Both the substrate resistivityand the P-tub surface concentration were modifiedwith the initial value of VTN increased to 1.8 volts

from the standard value of 1.3 volts and VTP changed

from the standard -1.7 volts to -1.3 volts.

CIRCUIT DESCRIPTION

The f irst radiation-hard circuit developed was a

dual 16-bit parallel-serial accumulator micro-processor port (Figure 2). This circuit fully met

military specif ications and was primarily intendedfor count rate applications. It featured high speedSchmitt trigger clock inputs with internal storageregisters capable of asynchronous parallel datatransfer. The stored results could be tri-stateddirectly onto a microprocessor data bus or shifted

1365PARALLEL DATA

OUT WORD SELECT

CARRY OVERFLOW CARRY OVERFLOWA FLAG A B FLAG B

Figure 2. Circuit block diagram of a dual 16-bitparallel-serial accumulator IO port usedfor radiation testing.

serially for such applications as PCM communicationlinks. Status registers were provided to indicateoverflow conditions. For ease of use, the circuitfeatured TTL drive compatible outputs and inputs whenoperated at 5 volts. It also featured decoding logicfor simple microprocessor addressing of the indivi-dual stored bytes. All inputs and outputs werestatic protected and fully buffered.

TOTAL DOSE RADIATION TEST RESULTS

The National Semiconductor, Inc. certified Co60radiation source was used for circuit irradiation.Two test phases were undertaken; a post irradiationtest phase and an in situ test phase.

Post Irradiation Testing

A sample size of 10 gate arrays was powered at 9volts during irradiation with the inputs tied toeither VDD or Vs* Post irradiation tests were per-formed on all devices at 10 4, 3 x 104 , 105, 3 x 105106$ 3 x 106,1 3 x10,7, and 108 rad(Si) atvarious supply voltages. The shif t of the p andn-channel thresholds are shown in Figure 3 and themaximum operating frequency at 5, 10, and 15 volts isshown in Figure 4. All electrical tests wereperformed on a Sentry VII computer at CaliforniaDevices within 1.5 hours of circuit irradiation.

In Figures 3 and 4 the radiation scale begins at

106 rad(Si) because the test data at 10 , 3 x 104,105, 3 x 105 and 106 rad(Si) indicated that the p andn-channel voltage thresholds and operating frequencyremained unchanged. The p-channel threshold, VTP,increased in magnitude with irradiation in agreement

4with theory4. For p-channel devices the radiationinduced holes in the gate oxide drift away from theSi-SiO2 interface and towards the metal oxide

interface. The trapped holes shift the p-channeldevice gate threshold to a larger negative voltage.This negative shift is augmented by the additionalVTP shift associated with the interface states.

1366For the n-channel device the threshold, VTN, is

expected to decrease due to radiation charge build-upin the gate oxide. The gate high condition drivesholes to the SiO2 - Si interface where they can

become trapped and induce a negative shif t in VTN.

The negative shift in VTN is not observed in Figure 2

since the gate was biased low for this case. TheN-channel threshold for the gate biased high condi-tion indicated an initial 0.6 volt decrease (minimum)

in VTN at 3 x 106 rad(Si) with a subsequent increase

in VTN with increasing irradiation in agreement withTN ~~~~~2previous test results * The n-channel threshold

voltage increased during irradiation by about 1 volt

at 108 rad(Si) for both the gate biased high or low.

An explanation for the VTN shif t is that the inter-

face states, generated by the Co60 radiation,compensate for and eventually exceed the negative

4charge build-up effect in the gate oxide * For thegate biased low the holes have more time to recombinewithin the gate oxide since the low electric fieldacross the gate does not drive them rapidly to theinterface.

In Figure 4 the maximum frequency of the countercircuit is shown as a function of total dose forsupply voltages of 5, 10, and 15 volts. At 10 MRadsthe maximum counter frequency is 5, 3, and 0.7 Mhzfor supply voltages of 15, 10, and 5 volts respect-ively. The degradation in speed is consistent withthe shift in the p and n-channel thresholds observedduring irradiation (Figure 3).

5.0

4.10-J03:CW 3.II-

2.

106 3 x 106

RADIATION

Figure 3. P and N-channel

wui 6 S _ o Sz v i

U0 5

zU 2

0>w V =D1 V

u 3Dz 1 ;

RADIATION (RADS-Si )Figure 4. Maximum clock frequency for rad-hard gate

thresholds during irradiation are shown in Figure 5and are similar to the results obtained previously(Figure 3). A slight lowering of the n-channel

threshold at about 3 x i06 is consistent with

2~~~~

previous studies.The supply current of the gate array operating

at 0.5 MHz (by0) was 0.4 mA. After an exposure to

7

10/ rad(Si) the supply current decreased to 0.35 mA

and at 3 x 107 rad(Si) to 0.32 mA. The observeddecrease in supply current with increasing total dose

(10 - 10 rad(Si) range) is likely due to the shiftsin the p and n-channel thresholds which internallychange the switching characteristics of the CMOSdevices (4).

DOSE RATE EFFECTS

When CMOS IC's are subjected to large bursts ofionizing radiation, hole-electron pairs are createdin the silicon substrate. The resultant current

flowing through the high resistivity P and N-sub-strates can cause voltage differences which mayimpair circuit performance. Specific dose-rate dataon the gate array circuit has not been acquired to

date, although it is expected to follow the rather

N-CHANNEL well known characteristics of the National Semi-conductor, Inc. rad-hard process. Special precau-tions were taken during the design phase to prevent a

107 3 x 107 108 latch-up condition (e.g. extended p-channel gates to10 3x 010 overlap to p-well). Detailed dose-rate effects on

4 (RADS-Si) the 30 megarad CMOS gate array are presently underwayas part of the CRRES satellite microelectronic

threshold shifts for the program and will be reported later.I6rad-hard gate array. Below 10 rad(si)the thresholds remained unchanged. Thep-channel threshold voltages are ofnegative sign.

In Situ Radiation Testing

During a second irradiation test, real-timemeasurements were made of the rad-hard gate arraywhile it was being irradiated. The functionality ofthe circuit was continuously monitored and the supplycurrent and p and n-channel thresholds were tested at

selected intervals. A 0.5 MHz square wave with a 50%duty cycle was continuously applied to the accum-ulator clock inputs. During irradiation to a totaldose of 30 megarads the accumulator circuit wasmonitored and remained completely functional. Thereal-time measurements of the p and n-channel

One technique in the processing phase which has beensuccessfully employed to eliminate latch-up on the

National Semiconductor, Inc. rad-hard line has beenthe use of neutron irradiation to lower minoritycarrier lifetime in the gate array silicon substrate.This directly affects the parasitic bipolar current

gains. By treating wafers with neutron fluxes on the

order of 1014/cm2, enhanced circuit performance is10

obtained (> 10 rad(Si)/sec) without sacrificingparameteric performance. Additional tests are

planned for the neutron irradiated gate array devicesto ascertain stability with temperature and longrange annealing effects.

-1-J0

I-,

a.

- 2

3

-4

-J

-j0

z

4I

3

2

1'

DOSE (Rad-Si)

Figure 5. In situ total dose measurements of therad-hard gate array P and N channelthreshold shifts.. Id = 0 curves represent

the VT threshold and the Id = 100 micro-amps curves represent the voltage thres-hold when the supply current is 100microamps.

Data upset effects result in the loss of stored datain a circuit after being subjected to burst radia-tion. It is typically of most concern in gate arraycircuits such as memories and shift registers, wherestored data bits are not directly coupled to circuitinputs. Photo currents induced by bursts of ionizingradiation can cause a current flow across a normallyreverse-biased PN junction. This current flow canupset the logic level stored at a node associated

Table 2. Radiation Hardness Assurance Plan

I. Plan A-Qualification to 105 rad(Si)Sample Size (Wafers)Sample Size (Devices/Wafer)Total Devices IrradiationAccept Level

25100 Relect

II. Plan B-Qualif ication to 10 rad(Si)Sample Each WaferSample Size (Devices/Wafer) 4Accept Level 0 RejectsReject Level 1 Reject

III. Product Flow (Per Mil-STD-883, Method 1019):A. Assemble Sample Devices in Appropriate

Production Package.B. Read-And-Record Electrical Parameters

(Pre-Radiation) .

C. Irradiate to Applicable Total Gamma Dose.D. Read-And-Record Electrical Parameters

(Post-Radiation) .

E. Evaluate gerformance Per Table III-A (10 ),III-B (10 ), or III-C (10 ), As Applicable.

1367with the p-n junction. Again neutron treatment canimprove data-upset errors. However, the effect isnot nearly as dramatic as it is in the case oflatch-up. For neutron untreated wafers the upsedose rate has been found to be about 4 x 10rad(Si)/sec for the National Semiconductor, Inc.

rad-hard process 2.

QUALIFICATION

Radiation acceptance and qualification testingof the production units was performed at 106 rad( Si)in accordance with the radiation hardness assuranceplan of Table 2. Wafer lot acceptance testing wasperformed using method 5007 of MIL-STD-883. Allcircuits were subsequently tested and screened toMIL-STD-883 class B.

CONCLUSION

The radiation-hard accumulator gate array is nowoperating in orbit on the NASA Active MagnetosphericParticle Tracer Explorer (AMPTE) satellite. It isalso being used for instruments to be flown in thejoint NASA and DoD Combined Release and RadiationEffects Satellite (CRRES) and in the NASA UpperAtmospheric Research Satellite (UARS). Although theoperating speeds of the metal gate array family arerelatively slow (e.g. < 15 ns at 15 volts) comparedto VHSIC goals the metal gate process is extremelyradiation-hard, reliable, and rugged. It thus servesas a new and cost effective solution for replacingentire printed circuit boards (which consist of 20 to100 SSI/MSI 4000B Series CMOS IC's) with a singlesemicustom gate array. Both in situ and post

irradiation test using a certified Co60 radiationsource indicated a radiation tolerance of 30 Mega-rads. Wafer lot acceptance testing was performedusing method 5007 of MIL-M-38510.

REFERENCES

1. Specification Data Sheet, CDI Series, CaliforniaDevices, San Jose, CA.

2. Radiation Hardened Technologies,Semiconductor, Inc., Santa Clara, CA.

National

3. Dawes, W. R., Jr., G. F. Derbenwich, and B. L.Gregory, Process Technology for RadiationHardened CMOS Integrated Circuits, IEEE Journalof Solid State Circuits, SC-li, No. 4, 459, 1976.

4. Nicollian, E. H., and J. R. Brews, MOS Physicsand Technology, Bell Laboratories, Murray Hill,N.J., 1982.

ACKNOWLEDGEMENTS

Much of this research was performed under theLockheed Independent Research Program. Appreciationis extended to Dr. J. B. Reagan of Lockheed forvaluable consultation, to S. R. Roselle of Lockheedfor developing test circuits and associated software,to the layout engineer G. Mcleod and quality assu-

rance engineer G. 0. Compton of California Devices,Inc., to the process engineers at NationalSemiconductor, Inc. and to Bruce Beers of BECOS, Inc.

Id x 0

Id- lOOpA

VDD = 1 V

CO 60 RADIATION

Id = lOOpA

Id = 0

I,

1

61 07