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Bebop to the Boolean Boogie An Unconventional Guide
to Electronics
Third Edition
Clive "Max" Maxfield
AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO
SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO ELSEVIER Newnes is an imprint of Elsevier Newnes
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Contents
ABOUT THE AUTHOR xvii
FOREWORD xix
ABOUT THIS BOOK xxi
ACKNOWLEDGMENTS xxv
SECTION 1 • Fundamentals
CHAPTER 1 Analog Versus Digital 3
It Was a Dark and Stormy Night 3
Analog Versus Digital Views of the World 4
Multi-Value Digital Systems 5
Experiments with Bricks 6
CHAPTER 2 Atoms, Molecules, and Crystals 11
Protons, Neutrons, and Electrons 11
Quantum Levels and Electron Shells 13
Making Molecules 13
Crystals and Other Structures 15
CHAPTER 3 Conductors, Insulators, and Other Stuff 17
Conductors and Insulators 17
Voltage, Current, and Resistance 18
Resistance and Resistors 19
Capacitance and Capacitors 21
Inductance and Inductors 23
Memristance and Memristors 28
Impedance and Reactance 28
Admittance, Conductance, and Susceptance 29
Unit Qualifiers 30
CHAPTER 4 Semiconductors (Diodes and Transistors) 3 3
Herding Wild Electrons 33
The Electromechanical Relay 33
The First Vacuum Tubes 35
Semiconductors 36
Semiconductor Diodes 37
Bipolar Junction Transistors (BJTs) 39
Metal-Oxide Semiconductor Field-Effect Transistors
(MOSFETs) 41
The Transistor as a Switch 43
Gallium Arsenide Semiconductors 4 4
Light-Emitting Diodes [LEDs] 45
Organic LEDs (OLEDs) 4 6
Active Versus Passive and Electric Versus Electronic 47
CHAPTER 5 Pr imit ive Logic Functions 4 9
Switch Representations of AND and OR Functions 4 9
FALSE and TRUE Versus OPEN and CLOSED 50
BUF and NOT Functions 51
"Connect the NOTs" 52
AND, OR, and XOR Functions 52
NAND, NOR, and XNOR Functions 53
Not a Lot 55
Functions Versus Gates 56
CHAPTER 6 Using Transistors t o Build Logic Gates 5 7
NMOS, PMOS, and CMOS 57
Using Os and Is Instead of Fs and Ts 57
NOT and BUF Gates 58
NAND and AND Gates 6 0
NOR and OR Gates 61
XNOR and XOR Gates 62
XNOR and XOR Gates: Pass-Transistor
Implementations 63
Pass-Transistor Logic 65
CHAPTER 7 Al ternat ive Number Systems 6 7
Fingers, Toes, and Pebbles 67
Bones with Notches 67
Tally Sticks: The Hidden Dangers 68
The Abacus 69
Roman Numerals 69
Decimal (Base-10) 70
Duo-Decimal (Base-12) 71
Sexagesimal (Base-60) 73
The Concepts of Zero and Negative Numbers 74
Vigesimal (Base-20) 76
Contents
Jobs Abound for Time-Travelers 76
Quinary (Base Five) 77
Binary (Base-2) 78
Octal (Base-8) and Hexadecimal (Base-16) 8 0
Way Back in the Mists of Time 82
Representing Numbers Using Powers 82
Lucky and Unlucky Numbers 8 4
Tertiary Logic 85
CHAPTER 8 Binary Ar i thmet ic 8 7
Before We Start 87
Unsigned Binary Numbers 87
Adding Unsigned Binary Numbers 8 8
Nines' and Ten's Complements 89
Subtracting Unsigned Binary Numbers 91
Sign-Magnitude Binary Numbers 93
Signed Binary Numbers 9 4
Adding Signed Binary Numbers 95
Subtracting Signed Binary Numbers 9 6
Binary Multiplication 97
Binary Division 9 8
CHAPTER 9 Boolean Algebra 9 9
Cabbages, Parrots, and Buckets of Burning Oil 9 9
Primitive Logic Functions 100
Combining a Single Variable with Logic О or Logic 1 102
The Idempotent Rules 102
The Complementary Rules 102
The Involution Rule 103
The Commutative Rules 104
The Associative Rules 104
Precedence of Operators 105
The First Distributive Rule 105
The Second Distributive Rule 105
The Simplification Rules 106
DeMorgan Transformations 106
Minterms and Maxterms 112
Sum-of-Products and Product-of-Sums 112
Canonical Forms 114
An Interesting Conundrum 114
Contents
CHAPTER l O Karnaugh Maps 117
The Tree of Porphyry 117
John Venn and his Venn Diagrams 117
Allan Marquand and Lewis Carroll 117
Maurice Karnaugh and Karnaugh Maps 118
Minimization Using Karnaugh Maps 119
Grouping Minterms 120
Incompletely Specified Functions 122
Populating Maps Using Os Versus Is 123
CHAPTER 11 Slightly M o r e Complex Functions 125
First Gather a Bucket of Logic Gates 125
Scalar Versus Vector Notation 125
Equality Comparators 126
Multiplexers 127
Decoders 129
Tri-State Functions 130
Combinational Versus Sequential Functions 132
RS Latch (NOR Implementation) 132
RS Latch (NAND Implementation) 137
D-Туре Latches 138
D-Туре Flip-flops 139
Implementing a D-Туре Flip-flop 142
JK and T Flip-flops 143
Shift Registers 144
Counters 146
Setup and Hold Times 148
Brick by Brick 149
CHAPTER 12 Sta te Machines 151
"Is That a Gizmo in Your Pocket, Or . . . " 151
State Diagrams 152
State Tables 153
State Machines 154
State Assignment 155
Don't Care States, Unused States, and Latch-Up Conditions.... 158
CHAPTER 13 Analog-to-Digital and Vice Versa 161
Setting the Scene 161
Analog-to-Digital 162
Digital-to-Analog 164
DSP Versus DSP 165
Analog Signal Processing [ASP] 165
Digital Signal Processing [DSP] 166
DSP Examples 167
What Implements the Digital Signal Processing? 167
SECTION 2 • Components and Processes
CHAPTER 14 In tegrated Circuits (ICs) 173
The First Integrated Circuits 173
An Overview of the Fabrication Process 175
A Slightly More Detailed Look at the Fabrication Process 176
An Introduction to the Packaging Process 181
Integrated Circuits Versus Discrete Components 185
Different Types of ICs 186
TTL, ECL, and CMOS 187
Core Supply Voltages 187
Equivalent Gates 188
Device Geometries 188
What Comes After Optical Lithography? 190
How Many Transistors? 192
Moore's Law 192
CHAPTER 15 M e m o r y ICs 193
RAMs and ROMs 193
Cells, Words, and Arrays 195
Addressing a Word in Memory 196
Kilo, Mega, Giga, Tera, Etc 196
Bits and Bytes 197
ROM Control Decoding 197
RAM with Separate Data In and Data Out Busses 199
RAM with Single Bidirectional Bus 2 0 0
Increasing Width and Depth 201
Mask-Programmed ROMs 2 0 2
PROMs 203
EPROMs 205
EEPROMs/EEPROMs 207
FLASH 207
SRAMs and DRAMs 208
SDRAMs 208
DDR, DDR2, DDR3, QDR, RAMBUS, Etc 210
SIMMs, DIMMs, and RIMMs 210
ECC Memory 211
MRAMs 211
nvRAMs, FRAMs, PRAMs, RRAMs, CBRAMs, SONOS, Etc 211
CHAPTER 16 Programmable ICs 213
A Simple Programmable Function 213
Fusible-Link Technologies 214
Antifuse Technologies 215
EPROM, E2PROM, FLASH, and SRAM Technologies 217
The First Programmable Logic Devices (PLDs) 217
PROMs 218
PLAs 221
PALsandGALs 223
Additional Programmable Options 224
Introducing CPLDs 224
Introducing FPGAs 227
Alternative FPGA Architectures 229
Alternative FPGA Configuration Technologies 232
Mixed-Signal FPGAs, CSSPs, and 233
Summary 233
CHAPTER 17 Application-Specific In tegrated Circuits (ASICs) 2 3 5
Introducing ASICs 235
Full Custom Devices 236
Gate Arrays 236
High-Level View of the Gate Array Design Flow 238
Standard Cell Devices 2 4 0
High-Level View of the Standard Cell Design Flow 241
IT Versus 6 T SRAM 241
Structured ASICs 242
Input/Output (I/O) Cells and Pads 245
ASICs Versus ASSPs 2 4 6
Who Are All the Players? 2 4 6
Summary 2 4 8
CHAPTER 18 Pr inted Circuit Boards (PCBs) 2 5 1
Not Much Fun 251
The First Circuit Boards 251
PCBs and PWBs 252
RoHS and Lead-Free Solder 252
Subtractive Processes 253
Additive Processes 255
Single-Sided Boards 257
Lead Through-Hole (LTH) 259
Wave Soldering 259
Surface Mount Technology (SMT) 2 6 0
Double-Sided Boards 262
Holes Versus Vias 2 6 4
Multilayer Boards 265
Through-Hole, Blind, and Buried Vias 266
Power and Ground Planes 267
High Density Interconnect (HDI) and Microvia Technologies... 270
Backplanesand Motherboards 271
Conductive Ink Technology 272
Chip-on-Board (COB) 273
Flexible Printed Circuits (FPCs) 274
CHAPTER 19 Hybrids 2 7 7
The Offspring Resulting from Crossbreeding 277
Hybrid Substrates 277
The Thick-Film Process 278
Creating Tracks 279
Creating Resistors 2 8 0
Laser Trimming 281
Creating Capacitors and Inductors 282
Double-sided Thick-Film Hybrids 283
Subtractive Thick-Film Technology 283
The Thin-Film Process 283
Laser Trimming 285
The Assembly Process 286
Attaching the Die 286
Wire Bonds 287
Tape-Automated Bonding 288
Flipped-Chip Techniques 289
Advantages of Using Bare Die 2 9 0
The Packaging Process 2 9 0
CHAPTER 2 0 Advanced Packaging Techniques 2 9 3
Sliding Down the Rabbit Hole 293
Wire Bonds Versus Flip-Chip 293
Wire Bonding and Flip-Chip 2 9 4
Contents
Chip-Scale Package [CSP) Technology 2 9 4
3-D Die Stacking 295
System-in-Package [SiP], PiP, and PoP 296
A Positive Plethora of Substrates 297
An Example SiP Based on Cofired Ceramics 298
Low-Fired Cofired Ceramics 301
Assembly and Packaging 301
Pin Grid Arrays 3 0 2
Pad, Ball, and Column Grid Arrays 302
Fuzz-Buttons 3 0 4
Populating the Die 3 0 4
The Mind Boggles 305
CHAPTER 2 1 Al ternat ive and Future Technologies 3 0 7
A Smorgasbord of Technologies 307
Reconfigurable Computing 307
Elemental Computing Arrays (ECAs) 310
Optical Interconnect 314
Fiber-Optic Interconnect 314
It Pays to Keep Your Eyes Open 317
Free-Space Interconnect 317
Guided-Wave Interconnect 318
Optical Memories 3 2 0
Protein Switches and Memories 321
Electromagnetic Transistor Fabrication 324
Heterojunction Transistors 325
Виску balls and Nanotubes 328
Diamond Substrates 331
Chemical Vapor Deposition 331
Chemical Vapor Infiltration 332
Ubiquitous Laser Beams 332
The Maverick Inventor 333
The Requirement for Single-Crystal Diamond 333
Conductive Adhesives 334
Superconductors 335
Nanotechnology 337
Back to the Water Molecule 337
Imagine a Soup 339
Once Again, the Mind Boggles 341
Summary 342
Contents
SECTION 3 • Design Tools and Stuff
CHAPTER 2 2 General Concepts 3 4 5
Stuff, More Stuff, and Yet More Stuff 345
The Origins of EDA 345
Computer-Aided Design (CAD) 346
Computer-Aided Engineering (CAE) 346
Designers Versus Engineers 347
Electronic Design Automation (EDA) 347
Automation 347
Embedded Systems 348
Programming Versus Hardware Design Languages 349
Netlists 350
Transistor-Level 350
Gate-Level 351
Component-Level 351
Different Levels of Abstraction 351
Transistor-Level 352
Switch-Level 352
Gate-Level 353
Structural 353
Functional (Boolean, RTL) 353
Behavioral 354
Algorithmic 354
Different Languages 354
Programming Languages 354
Scripting Languages 355
Hardware Description Languages (Digital) 355
Hardware Description Languages (Analog) 358
Verification Languages (General) 358
Verification Languages (Formal) 358
Electronic System Level (ESL) 359
CHAPTER 2 3 Design and Verif icat ion Tools 3 6 1
Weasel Words 361
Design Capture 361
Transistor-Level and Gate-Level Netlists 361
Schematic Capture 362
Higher Levels of Abstraction 363
Graphical Design Entry Lives On 363
Functional Verification (Simulation) 3 6 4
Formal Verification 365
Logic Synthesis 366
Layout (Place-and-Route) 367
Parasitic Extraction 367
Timing Analysis 368
Static Timing Analysis (STA) 368
Statistical Static Timing Analysis (SSTA) 369
Design for Manufacturability (DFT) 370
And So Much More 371
Schematic Synthesis 371
Analog Synthesis 371
RF/Microwave Design Tools 372
Hardware Simulation Acceleration and Emulation 372
Mixed-Signal Simulation 373
Physical Verification (DRC, ERC, LVS) 373
Signal Integrity (SI) Analysis 374
Thermal Analysis 374
Power Analysis 374
Electromagnetic Interference and Compliance
(EMI and EMC) 374
SCAN, BIST, JTAG, etc 375
Automatic Test Pattern Generation (ATPG) 376
Fault Simulation 376
Turn That Frown Upside Down 376
A P P E N D I X A Assert ion-Level Logic 3 7 7
A P P E N D I X В Posit ive Versus Negat ive Logic 3 8 3
A P P E N D I X С Reed-Mül ler Logic 3 8 9
A P P E N D I X D Gray Codes 3 9 3
A P P E N D I X E Linear Feedback Shift Registers (LFSRs) 4 0 7
A P P E N D I X F Pass-Transistor Logic 4 2 3
A P P E N D I X G More on Semiconductors 4 2 7
A P P E N D I X H Rounding Algori thms l O l 4 3 5
A P P E N D I X I An Interesting Conundrum 4 5 5
A P P E N D I X J A No-Holds Barred Seafood Gumbo 4 5 9
Glossary 4 6 5
Index 525
