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Thin Silicon R&D for LC Thin Silicon R&D for LC applications applications D. Bortoletto D. Bortoletto Purdue University Purdue University Status report Status report Hybrid Pixel Detectors for LC Hybrid Pixel Detectors for LC

Thin Silicon R&D for LC applications

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D. Bortoletto Purdue University. Status report Hybrid Pixel Detectors for LC. Thin Silicon R&D for LC applications. TESLA TDR. Pixel micro-vertex r=1.5 cm -6 cm (VTX) Time Projection Chamber (TPC) provides not only good p/p but also excellent dE/dx - PowerPoint PPT Presentation

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Page 1: Thin Silicon R&D for LC applications

Thin Silicon R&D for LC Thin Silicon R&D for LC applicationsapplications

D. BortolettoD. BortolettoPurdue University Purdue University

Status reportStatus reportHybrid Pixel Detectors for LCHybrid Pixel Detectors for LC

Page 2: Thin Silicon R&D for LC applications

TESLA TDR TESLA TDR

Pixel micro-vertex Pixel micro-vertex r=1.5 cm -6 cm r=1.5 cm -6 cm (VTX)(VTX)Time Projection Time Projection Chamber (TPC) Chamber (TPC) provides not only provides not only good good p/p but also p/p but also excellent dE/dx excellent dE/dx Silicon tracker (SIT) Silicon tracker (SIT) in barrel (to improve in barrel (to improve p/p)p/p)Silicon disks (FTD) Silicon disks (FTD) and forward and forward chamber (FCH) chamber (FCH) provide tracking in provide tracking in the forward regionthe forward region

Page 3: Thin Silicon R&D for LC applications

LC: Pixel Vertex DetectorLC: Pixel Vertex Detector

5 layers, 0.1%X0

4 layers, 0.2%X0/layer

Stefania Xella

CCD are the default option in CCD are the default option in the barrelthe barrel– small pixel size small pixel size (20 (20 μμm )m )22

– excellent spatial resolution (<5 excellent spatial resolution (<5 μμm)m)– Slow readout (R&D)Slow readout (R&D)– Concern about radiation hardness Concern about radiation hardness

(R&D)(R&D)– CoolingCooling

• DEPFET, MAPS

5 layers, 0.1%X0/layerThinning SI bulk to 50 μμmm

Page 4: Thin Silicon R&D for LC applications

Hybrid Active Pixels Hybrid Active Pixels – Advantages:Advantages:

fast time stampingfast time stampingsparse data read outsparse data read outexcellent radiation tolerance.excellent radiation tolerance.

– Further improvements are needed for:Further improvements are needed for:point resolutionpoint resolution, which is currently limited by the , which is currently limited by the pixel dimensions of 50 pixel dimensions of 50 m m 300 300 m limited by the m limited by the VLSI. Can be improved by using VLSI. Can be improved by using interleaved pixel interleaved pixel cells which induce a signal on capacitivecells which induce a signal on capacitivelyly coupled coupled read-out pixelsread-out pixelsreduction in materialreduction in material (thin silicon) (thin silicon)

– Interesting for the FTD ???Interesting for the FTD ???Purdue is collaborating with J. Fast, S. Kwan, Purdue is collaborating with J. Fast, S. Kwan, W. Wester and C. Gingu at Fermilab on LC W. Wester and C. Gingu at Fermilab on LC effort. Proposal was submitted to the NSF. effort. Proposal was submitted to the NSF.

Thin Hybrid PixelsThin Hybrid Pixels

Page 5: Thin Silicon R&D for LC applications

Work has been done by Caccia, Bataglia, Niemiec et al.Work has been done by Caccia, Bataglia, Niemiec et al.Interleaved pixelsInterleaved pixels

p+

n

PolyresistorInterleaved pixelReadout pixelreadout pitch = n x pixel pitch

Large enough to house the

VLSI front-end cell

Small enough for an effective

sampling

Structures with: Structures with: 60 60 m implant width, 100 m implant width, 100 m m pixel pitch, 200 pixel pitch, 200 m readout pitch yield m readout pitch yield rresolution:esolution:– Interleaved pixels (max charge sharing): Interleaved pixels (max charge sharing): 3 3 mm– Readout pixels (min charge sharing): Readout pixels (min charge sharing): 10 10 mm

New prototypes with Pixel pitch 25 New prototypes with Pixel pitch 25 m x 25 m x 25 m and m and 25 25 m x 50 m x 50 m should yield improved performancem should yield improved performance

Page 6: Thin Silicon R&D for LC applications

TESLA: Forward trackingTESLA: Forward tracking

Layout of a Layout of a forward pixel forward pixel layer layer

Layout of a Layout of a forward strip layer forward strip layer

Material minimization is importantMaterial minimization is important

Page 7: Thin Silicon R&D for LC applications

LC: trackingLC: tracking

Silicon option NLC: Silicon option NLC: – SmallSmall– 5 samplings/track 5 samplings/track – No dE/dxNo dE/dx– Reduce volume of Ecal (SiW)Reduce volume of Ecal (SiW)

SD thin achieves good momentum SD thin achieves good momentum resolutionresolution– 3 thin inner layers (200 3 thin inner layers (200 μμm)m)– 2 outer layers (300 2 outer layers (300 μμm)m)

Gaseous detector (TPC- Gaseous detector (TPC- TESLA): TESLA): – LargeLarge– many samplings/track many samplings/track – dE/dxdE/dx

Bruce Schumm

Page 8: Thin Silicon R&D for LC applications

Technical problems:Technical problems:– Manufacturing of thin devices is difficultManufacturing of thin devices is difficult– Thinning after processing is difficultThinning after processing is difficult– Industry has expressed interest in thin silicon devicesIndustry has expressed interest in thin silicon devices– Collaboration with vendors is critical Collaboration with vendors is critical

How thin:How thin:– The m.i.p. signal from such a thin, 50µm, silicon The m.i.p. signal from such a thin, 50µm, silicon

sensor layer is only ~3500 e-h pairs.sensor layer is only ~3500 e-h pairs.

R&D at Purdue has started last year. We got R&D at Purdue has started last year. We got quotes from two vendors: Sintef and Micronquotes from two vendors: Sintef and MicronSintef:Sintef: minimum thickness 140 minimum thickness 140 µm on 4 inch µm on 4 inch waferswafersMicron:Micron: 4" Thickness range from 20μm to 2000μm, 6" 4" Thickness range from 20μm to 2000μm, 6" Thickness range from 100μm to 1000μmThickness range from 100μm to 1000μm

Thin silicon R&D at PurdueThin silicon R&D at Purdue

Page 9: Thin Silicon R&D for LC applications

We have selected Micron and we are exploring We have selected Micron and we are exploring both n-on-n and p-on-n options. both n-on-n and p-on-n options. We expect to receive thin silicon strips sensors We expect to receive thin silicon strips sensors soon (fabricated with CDF-L00 masks)soon (fabricated with CDF-L00 masks)We will compare: 150, 200 and 300 We will compare: 150, 200 and 300 m thick m thick strip detectors performance using the SVX4 strip detectors performance using the SVX4 chip developed for the so called “run 2b“chip developed for the so called “run 2b“Pixel masks have been designed. Each 6” wafer Pixel masks have been designed. Each 6” wafer will contain:will contain:– Several pixels sensors matching the CMS ¼ micron Several pixels sensors matching the CMS ¼ micron

chip (100 chip (100 µmµm 150 µm)150 µm)– RD50 PAD structures for SLHCRD50 PAD structures for SLHC– Test structures to study bump bonding Test structures to study bump bonding

Sensors should be available for first tests in Sensors should be available for first tests in about 6 months.about 6 months.

Thin silicon R&DThin silicon R&D

Page 10: Thin Silicon R&D for LC applications

Masks (6”) are fabricated and processing (oxigenation) is starting this week. Devices out of fabrication within 3-4 months

Pixel Mask Layout Pixel Mask Layout

Page 11: Thin Silicon R&D for LC applications

Area is dominated by CMS pixel devices compatible with the 0.25 m chip

Page 12: Thin Silicon R&D for LC applications

Circled in red the RD50 structures (diodes)

Page 13: Thin Silicon R&D for LC applications

RAL p-on-n pixels&

Micron n-on-p pad detectors

N-side

P-side

Page 14: Thin Silicon R&D for LC applications

As usual diodes and other test structure for process control

Page 15: Thin Silicon R&D for LC applications

CMS Radiation Hard DesignCMS Radiation Hard DesignGuard ring design:Guard ring design:– Limits lateral extension of the Limits lateral extension of the

depletion regiondepletion region– Prevents breakdown at the Prevents breakdown at the

device edge device edge – 11 guard ring design 11 guard ring design

implemented in SINTEF 1999 implemented in SINTEF 1999 submission achieved NO submission achieved NO BREAKDOWN up to >800 V after BREAKDOWN up to >800 V after irradiation to irradiation to = 6 = 610101414 n neqeq/cm/cm22

Diode

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0 100 200 300 400 500 600 700 800

Reverse Bias (V)

Leak

age

Cur

rent

(A)

S22P47

S22P29

S24P29

S4P47

= 61014 neq/cm2

nn++-on-n option:-on-n option:– Allows operation of Allows operation of

un-depleted sensors un-depleted sensors after type inversionafter type inversion

– N-side pixel N-side pixel isolationisolation

P-stops (CMS)P-stops (CMS)– SINTEF 1999 showed SINTEF 1999 showed

that F design was that F design was promisingpromisingF: Single open ringA : Double open ring

TDR

Page 16: Thin Silicon R&D for LC applications

Detail of a thin strip detectorDetail of a thin strip detector

Page 17: Thin Silicon R&D for LC applications

Material minimization for LC applications makes Material minimization for LC applications makes thin silicon development very interestingthin silicon development very interestingThin silicon is also more rad-hard Thin silicon is also more rad-hard Synergy Synergy between our LC interest and LHC commitmentsbetween our LC interest and LHC commitmentsSeveral thin silicon strip and pixel sensors will Several thin silicon strip and pixel sensors will be available to study:be available to study:– Mechanical stabilityMechanical stability– Bump bonding feasibilityBump bonding feasibility– Readout and geometry not yet optimal for LC Readout and geometry not yet optimal for LC

application application – Simulation studies are needed to guide this effort and Simulation studies are needed to guide this effort and

to provide input for future submissions and optimize to provide input for future submissions and optimize geometrygeometry

ConclusionsConclusions