Theory and Experiment on an Optimal Carrier Frequency of a Modular Multilevel …iranswitching.ir/wp-content/uploads/2016/01/Theory-and... · 2016-01-28 · ular multilevel cascade

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. Seehttp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TPEL.2015.2464694, IEEE Transactions on Power Electronics

1

Theory and Experiment on an Optimal Carrier

Frequency of a Modular Multilevel Cascade

Converter With Phase-Shifted PWMFirman Sasongko, Student Member, IEEE, Kei Sekiguchi, Kota Oguma, Makoto Hagiwara, Member, IEEE,

and Hirofumi Akagi, Fellow, IEEE

Abstract—This paper provides theoretical and experimentaldiscussions on an optimal carrier frequency for a phase-shiftedPWM modular multilevel cascade converter for grid connections.The discussions conclude that the ratio of the optimal carrierfrequency with respect to the supply (ac) frequency is 5/2. Athree-phase downscaled front-to-front (FTF) system is designed,constructed, and tested to confirm the theoretical discussion. Itconsists of a pair of three-phase modular multilevel cascadeconverters rated at 400 Vdc and 10 kW, where the carrierfrequency is set to 450 Hz and the ac frequency to 180 Hz, thatis, their ratio is equal to 5/2. Moreover, simulated waveformsare compared to experimental ones under the same operatingconditions. Both experimental and simulated waveforms agreewell with each other not only in steady states but also in transientstates.

Index Terms—Front-to-front systems, grid connections, mod-ular multilevel cascade converters, phase-shifted-carrier PWM.

I. INTRODUCTION

The modular multilevel cascade converter based on double-

star chopper cells (MMCC-DSCC) has been expected as a

high-voltage, high-power ac-to-dc and/or dc-to-ac converter

in the MMCC family [1]. This paper refers to it as a DSCC

converter for clearly distinguishing it from the other family

members. It is the same in circuit configuration as the modular

multilevel converter (MMC) for grid connections and traction

applications [2]–[4]. Comprehensive research activities on

DSCC converters for grid connections and motor drives have

been going on with focus on modeling, modulation, control,

simulation, and experiment [2]–[32]. However, a large number

of papers have confirmed validity by computer simulation

although a small number of papers have verified it by ex-

periment.

Pioneering papers at the beginning of research on DSCC

converters or before recent booming paper publications can

be divided into the following two groups: One is based on the

so-called “voltage-sorting algorithm,” relying on a nonlinear

discrete model [2]–[4]. Although experimental voltage and

current waveforms of a submodule in a 2-MW MMC were

F. Sasongko, K. Oguma, M. Hagiwara, and H. Akagi arewith the Department of Electrical and Electronic Engineering,Tokyo Institute of Technology, 152-8552 Tokyo, Japan (e-mail: [email protected]; [email protected];[email protected]; [email protected]).

K. Sekiguchi is with Toshiba Corporation, Tokyo, Japan (e-mail:[email protected]).

presented, no experimental waveform of the whole MMC

was presented at the time [3], [4]. The other is characterized

by closed-loop control of the “circulating current” defined

uniquely from the positive-arm and negative-arm currents. It

is based on a linear continuous model that allows the use

of phase-shifted-carrier pulsewidth modulation (PWM), and is

supported by experimental waveforms obtained from a single-

phase DSCC converter with two chopper cells per arm [5],

[6].

From a viewpoint of “control” in a broad sense, suit-

able modulation techniques and capacitor-voltage-balancing

methods are mandatory for stable and proper operation of

DSCC converters. Modulation techniques can be categorized

into carrier-based PWM and non-carrier-based or programmed

PWM [13]–[31]. The carrier-based PWM mostly uses ei-

ther phase-shifted carriers [16]–[18] or level-shifted carriers

[19]–[22]. The phase-shifted PWM results in better overall

performance than the level-shifted PWM [23], [24]. Non-

carrier-based modulation includes selective harmonic elimina-

tion (SHE) technique [22], [27], nearest level control (NLC)

modulation technique [28]–[31], and averaging or submod-

ule unified PWM (SUPWM) [25]. However, manufacturers

prefer the matured and simple carrier-based PWM to the

other modulation techniques that may produce lower switching

frequencies but usually at the expense of more complex

implementation [13].

As for capacitor-voltage balancing, the voltage-sorting al-

gorithm takes in all the capacitor voltages and the polarity of

the current within an arm, and then selects the best appropriate

submodules in each arm, and keeps the state until the next

switching transition process [2]–[4]. This method may make

capacitor-voltage-balancing strategy simple. This would be

a main reason why many research scientists combine vari-

ous modulation techniques with the voltage-sorting algorithm

[18]–[22], [25]–[32]. However, actual switching frequencies

of all the submodules depend on operating conditions, circuit

parameters, and control gains. This results in the difficulty

of keeping the actual switching frequencies constant and

equal. On the other hand, the closed-loop control combined

with phase-shifted-carrier PWM makes the actual switching

frequency of all the chopper cells equal to the carrier frequency

[5], [6]. This equal switching frequency is independent of

operating conditions, circuit parameters, or control gains,

leading to easy thermal design of gate-commutated thyristors

(GCTs) or insulated gate-bipolar transistors (IGBTs) and their

www.IranSwitching.ir



2

heat sinks. Moreover, the phase-shifted-carrier PWM brings

easy extension of the chopper-cell count per arm to controller

implementation.

Recently, the authors of [16] have provided harmonic anal-

ysis of the capacitor current in a passively-loaded MMC

with phase-shifted-carrier PWM. The analysis is confirmed

by experimental results of a single-phase MMC with five

submodules per arm. It is concluded that the carrier frequency

in a range of 100 to 200 Hz should not be an integer multiple

of a fundamental frequency of 50 Hz, so as to prevent the mean

dc voltage of each capacitor from diverging. However, no

discussion has been provided on an optimal carrier frequency

for each submodule, and no attention has been paid to the

individual balancing control playing an important role in

regulating the mean dc voltage of each capacitor.

This paper lays emphasis on theoretical and experimental

discussions on an optimal carrier frequency for a three-phase

DSCC converter with phase-shifted-carrier PWM. The ratio

of the carrier frequency with respect to the supply frequency

should be set as low as possible because the DSCC converter

is intended for high-voltage and high-power applications.

This paper provides mathematical analysis of the power flow

formed by the arm current and the arm-side voltage of each

chopper cell under reasonable assumptions. As a result, this

paper concludes that an optimal ratio of the carrier frequency

with respect to the supply frequency is 5/2.

The validity of the mathematical analysis is confirmed by

the results obtained from experiment and computer simula-

tion. This paper designs, constructs, and tests a three-phase

downscaled DSCC-based FTF system rated at 400 Vdc and

10 kW to verify the optimal frequency ratio of 5/2, where

the carrier frequency is 450 Hz, and the ac-link frequency

is 180 Hz. Experiments are also carried out with the same

carrier frequency as 450 Hz but at different ac-link frequency

of 112.5 Hz, where the frequency ratio is 4/1. Moreover, this

paper includes simulated waveforms under the same circuit

parameters and control gains as the experimental ones. The

experimental and simulated waveforms show stable operation

and agree well with each other even in dynamic and transient

operating conditions, thus resulting in enhancing the reliability

and validity of both experiment and simulation.

II. SYSTEM CONFIGURATION OF A DSCC CONVERTER

A. Circuit Configuration and Per-Leg Circulating Current

Fig. 1 shows the circuit configuration of a three-phase

DSCC converter consisting of N series-connected chopper

cells and a center-tapped inductor LZ for each phase leg.

The line-to-neutral voltage at the ac terminal of the DSCC

converter is a PWM waveform with N+1 levels in maximum,

and the line-to-line voltage looks sinusoidal because it is a

PWM waveform with 2N + 1 levels in maximum.

Let iPu and iNu be the positive and negative arm currents,

and let iSu be the supply current flowing into the center

terminal of the u-phase center-tapped inductor in Fig. 1.

Moreover, let iZu be the “circulating current” flowing through

the u-phase leg that was defined as [5]

iZu =1

2(iPu + iNu). (1)

idc

iPu

iNu

iZuiSu

iSv

iSw

vuvVdc

v1u

v(N

2+1)u

vC1u

vC(N

2+1)u

cell

cell

cell

cell

cell

cell

cell

cell

cell

C

C

LZ

Fig. 1. Circuit configuration of the DSCC converter consisting of N choppercells per leg.

The number of independent currents among iSu, iPu, and iNu

is not three but two because Kirchhoff’s current law comes

into existence at the center terminal in the u-phase center-

tapped inductor. This paper selects the circulating current iZu,

defined by (1), and the supply current iSu as two independent

currents, so that the positive and negative arm currents act as

dependent currents:

iPu = − iSu2

+ iZu (2)

iNu =iSu2

+ iZu. (3)

The first terms on the right-hand sides in (2) and (3) are

related to the supply current. They are out of phase by 180◦

each other. As a result, the magnetic fluxes produced by the

supply current cancel out each other inside the magnetic core

of the center-tapped inductor. Therefore, the inductor presents

no inductance to the supply current, whereas it renders the

inductance LZ to the circulating current. Note that by using

the circulating current in (1) for control makes it possible to

regulate and balance the mean dc voltage of each split and

floating capacitor.

B. Control for the DSCC Converter

The DSCC converter based on phase-shifted-carrier PWM

is characterized by hierarchical control consisting of the fol-

lowing three layers [10]:

• Overall capacitor-voltage control.

• Arm-balancing control.

• Individual balancing control.

The overall capacitor-voltage control in the top layer takes

the responsibility to regulate the mean voltage of all the

capacitors to its reference. Adjusting a small amount of active

power supplied from the ac mains makes it possible to regulate

it.

The arm-balancing control in the middle layer plays an

important role in balancing six mean voltages, each of which




3

is the mean voltage of N/2 capacitors per arm. The dc

component of the circulating current in each leg is adjusted

to exchange a small amount of active power among the three

legs, while the fundamental (50 Hz) ac component is used

for the adjustment of an active-power difference between the

positive and negative arms.

The individual balancing control residing in the bottom

layer takes charge of regulating each capacitor voltage to the

mean voltage of N/2 capacitors per arm. This straightforward

control adjusts the active power formed by the arm-side

voltage of each chopper cell and the arm current.

C. Instantaneous Power Flow to Each DC Capacitor

Assuming ideal conditions, the arm-side voltage reference

of each chopper cell is given as follows [5], [6]:

v∗ju = −2v∗uN

+Vdc

N(j = 1 to N/2), (4)

v∗ju =2v∗uN

+Vdc

N(j = N/2 + 1 to N), (5)

where v∗u is the u-phase ac-terminal-voltage reference, and

N is the number of chopper cells per leg. The actual arm-

side voltage consists of v∗ju and harmonic voltages caused

by PWM, v′ju. The instantaneous power flowing into the

capacitor, pju, is given by the product between the arm-side

voltage v∗ju + v′ju and the arm current iPu or iNu. Equations

(2)–(5) give pju as follows:

pju = (v∗ju + v′ju)iPu

=v∗uiSuN

+VdciZuN

− 2v∗uiZuN

− VdciSu2N

−v′juiSu

2+ v′juiZu (j = 1 to N/2), (6)

pju = (v∗ju + v′ju)iNu

=v∗uiSuN

+VdciZuN

+2v∗uiZuN

+VdciSu2N

+v′juiSu

2+ v′juiZu (j = N/2 + 1 to N). (7)

Although the first to fourth terms at the right-hand sides

on (6) and (7) are independent of the carrier frequency fC,

their harmonic frequencies depend on the supply frequency

fS. On the other hand, harmonic frequencies of the fifth and

sixth terms depend on those of v′ju. The dominant harmonic

frequencies of v′ju consist of integer multiples of the carrier

frequency and its sideband frequencies. The amplitude of

the ac components contained in each capacitor voltage are

inversely proportional to their harmonic frequencies. When the

carrier frequency is high enough, v′ju is negligible. However,

it should be taken into account when the carrier frequency is

in a range of 100 to 200 Hz while the supply frequency is

50 Hz.

III. ANALYSIS OF CAPACITOR VOLTAGE FLUCTUATION

A. Definition of a Switching Function

The following assumptions are made to achieve power-flow

analysis:

• Two IGBTs used in each chopper cell are ideal switches.

• The arm current consists of a dc component and a

fundamental-frequency (50 Hz) component. This means

that a second-order (100 Hz) component and switching

components caused by PWM are negligible.

• Both arm-balancing control and individual balancing con-

trol produce no effect on the modulated waveform for

each chopper cell, vmd in (9).

• The phase-shifted-carrier PWM assigns a triangular-

carrier waveform to a chopper cell, vtri, and another one

that is phase-shifted by 360◦/N to the next chopper cell.

Let a switching function be S in this section, where S = 0when vmd < vtri, and S = 1 when vmd > vtri. The state

of S = 0 means that the positive switch in the chopper cell

remains turned off whereas the negative one remains turned on.

As a result, the arm-side voltage is zero and no current flows

into the floating capacitor (iC = 0). The state of S = 1 means

that the positive switch in the chopper cell remains turned on

whereas the negative one remains turned off. As a result, the

arm-side voltage is equal to vC and the current flowing into

the capacitor is equal to the arm current (iC = iarm).

The states definition produces the following equation:

iC = Siarm. (8)

The switching function S can be expanded into

S = vmd +∞∑

n=1

An. (9)

The first term at the right-hand side on (9) represents the

modulated waveform. The second term is the component

caused by switching or PWM, which is referred to as the “arm-

side switching component” hereinafter. Let fS (= ωS/2π) be

the supply frequency, φv be an initial phase, and a (0 ≤ a ≤ 1)

be the modulation factor. As a result, the modulated waveform

vmd in (9) can be written as

vmd =1

2+

a

2sin(ωSt+ φv). (10)

Since An in (9) has a center frequency nfC that multiplies

the carrier frequency fC (= ωC/2π) by a positive integer n,

it is given by

An =2

nπsin (nπvmd) cos

(

n(ωCt+ θint))

, (11)

where θint is the initial phase of the carrier waveform. Let

Jy(x) be the y-order Bessel function of the first kind, m be

an integer, and θ′int be equal to θint + π/2. The use of Jy(x)allows expanding An into

An =2

nπ

∝∑

m=−∝

Jm

(nπa

2

)

sin2(π

2(n+m)

)

× sin(

(nωC +mωS)t+ nθ′int +mφv

)

. (12)

Equation (12) shows that the harmonic frequencies of the

arm-side switching components consist of a center frequency

nfC and its even sideband frequencies nfC ± mfS for odd

number of n; and odd sideband frequencies nfC±mfS without

a center frequency for even number of n.




4

B. Derivation of the Capacitor Voltage

From (2) and (3), the arm current iarm is given as the sum

of its dc circulating-current component IZ0 and its supply-

frequency sinusoidal component by

iarm = IZ0 + ISa sin(ωSt+ φi), (13)

where ISa and φi are the amplitude and phase of the sinusoidal

component, respectively. Note that the sinusoidal component

defined in (13) is equal to half of the supply current defined

in (2) and (3). Equations (8) and (9) yield the current flowing

into the capacitor as follows:

iC = vmdiarm +

∞∑

n=1

iCswn, (14)

where iCswn is the switching components of the capacitor

current, which is the product of the arm-side switching com-

ponents and the arm current (Aniarm). Equations (12) and (13)

give iCswn in (14) as follows:

iCswn =1

nπ

∝∑

m=−∝

Jm

(nπa

2

)

sin2(π

2(n+m)

)

[

2IZ0 sin(


)

+ ISa cos(

(

nωC + (m− 1)ωS

)

t+ nθ′int +mφv − φi

)

− ISa cos(

(

nωC + (m+ 1)ωS

)

t+ nθ′int +mφv + φi

)

]

.

(15)

Equations (13) and (14) give the capacitor voltage vC as

follows:

vC =1

C

∫

vmdiarmdt+1

C

∫ ∞∑

n=1

iCswndt+ VC

= −VC1 cos(ωSt+ φ′)− aISa8ωSC

sin(2ωSt+ φv + φi)

+

∞∑

n=1

vCswn + VC , (16)

where VC1 and φ′ are the amplitude and phase of the

fundamental frequency component in the capacitor voltage,

respectively, and given by (48) and (49) in the Appendix.

The terms related to cos(ωSt+φ′) and sin(2ωSt+φv+φi) in

(16) are the voltage components resulting from the modulated

waveform, which consist of the first-order and second-order

components. The last term VC is the dc component, and the

second last term is the switching components caused by PWM.

Therefore, vCswn is referred to as the “capacitor switching

component.” It appears from the active power formed by the

arm-side switching component corresponding to An in (9)

and the arm current. Equations (15) and (16) give vCswn as

follows:

vCswn =1

nπC

∝∑

m=−∝

Jm

(nπa

2

)

sin2(π

2(n+m)

)

[

− 2IZ0nωC +mωS

cos(


)

+ISa

nωC + (m− 1)ωSsin(

(

nωC + (m− 1)ωS

)

t+ nθ′int +mφv − φi

)

− ISanωC + (m+ 1)ωS

sin(

(

nωC + (m+ 1)ωS

)

t+ nθ′int +mφv + φi

)

]

. (17)

Equation (17) shows that the spectra in the vicinity of nfCget larger in amplitude than those of the others. Equation (17)

also gives the following findings related to vCswn.

• The capacitor switching component vCswn includes har-

monic components that consist of the center frequency

nfC and its sideband frequencies nfC±mfS and nfC±(m∓ 1)fS . These harmonic components may influence

the amplitude, phase, and frequency of the original ac

component. In the worst case, they may produce overvolt-

ages across each capacitor, and may bring “saturation”

or “overmodulation” to the control system of the DSCC

converter.

• When either nfC −mfS = 0 or nfC − (m ± 1)fS = 0comes into existence, a dc component is included in

vCswn. When the dc component is low enough, it can

be canceled out by the individual balancing control.

However, when it is higher, vC would continue diverging

gradually.

• As fC gets lower, vCswn becomes more problematic

because its amplitude is inversely proportional to fC.

C. Effect of vCswn on the DC Component of the Capacitor

Voltage

Equations (16) and (17) suggest that the effect of vCswn on

the dc component of the capacitor voltage can be evaluated

by the dc component contained in iCswn. When a solution of

nfC +m′fS = 0 exists under a negative integer of m, where

m′ = −m or −m∓1, iCswn includes a dc component. Let the

irreducible fraction of the carrier frequency fC with respect to

the supply frequency fS be f ′C/f

′S

1, and let a positive integer

be k. The following combination gives the above solution:

(n,m′) = (kf ′S, kf

′C). (18)

The dc component included in iCswn=kf ′

S, ICk can be calcu-

lated by substituting (18) into the term satisfying the equation

of nfC +m′fS = 0 in (15) as follows:

ICk = |ICk| sin(kf ′Sθ

′int + kf ′

Cφv + φk), (19)

1For example, when fC = 125 Hz and fS = 50 Hz, f ′

C/f ′

S = 5/2.




5

|∆VC |%max[%]

40

10

5

0fC[Hz]50 100 150 200 250 300 350 400 450

Fig. 2. Mathematical analysis of the normalized maximum dc voltagefluctuation |∆VC |%max against the carrier frequency fC.

TABLE IPARAMETERS USED IN ANALYSIS

Supply (line) frequency fS 50 Hz

Unit capacitance constant HC 40 ms

Per-unit ac-link inductance Lpuac 0.1 pu

DC voltage/supply voltage Vdc/VS 2

Active power/rated power p/P 1

Reactive power/rated power q/P 0

where |ICk| is the absolute maximum value of ICk, and

φk depends on kf ′S, kf ′

C, and φi. By combining the same

frequency component in (15) and defining a function F (x, y)as

F (x, y) =√

x2 + y2 − 2xy cos{2(φv − φi)}, (20)

equations (15), (19), and (20) give |ICk| as follows:

• When both kf ′S and kf ′

C are even or odd numbers,

|ICk| =∣

∣

∣

∣

∣

ISakf ′

SπF

(

Jkf ′

C−1

(

kf ′Sπa

2

)

, Jkf ′

C+1

(

kf ′Sπa

2

)

)∣

∣

∣

∣

∣

. (21)

• When either kf ′S or kf ′

C is an even or odd number, and the

other is an odd or even number, respectively,

|ICk| =∣

∣

∣

∣

2IZ0kf ′

SπJkf ′

C

(

kf ′Sπa

2

)∣

∣

∣

∣

. (22)

Equations (21) and (22) show that as the three positive integers

f ′S, f ′

C, and k get larger, |ICk| gets smaller.

The dc voltage fluctuation occurring across the capacitor

voltage vC is caused by a total of dc components contained

in iC . The total current components is given by

IC =

∞∑

k=1

ICk. (23)

Let the amount of dc voltage fluctuation over a line-cycle

period TS (= 1/fS) be ∆VC . It is given as follows:

∆VC =1

C

∫ t0+TS

t0

∞∑

k=1

ICkdt =

∞∑

k=1

ICk

CTS. (24)

Thus, ∆VC can be evaluated by ICk. Equation (19) suggests

that a sinusoidal change in ICk is accompanied by a linear

∆V %C

[%]

10

5

0

-5

-10

θint[◦]

−90 −180 −270 −360

Mathematical analysisNumerical evaluation

Fig. 3. Comparisons between mathematical analysis and numerical evaluation

in terms of ∆V %C

and θint at fC = 150 Hz.

change in the initial phase of the carrier waveform, θint.When phase-shifted PWM is applied, the initial phases of

all the carrier waveforms exist in a range from 0◦ to −360◦

uniformly. In other words, all the chopper cells have different

values in ICk and ∆VC . Therefore, this paper defines the

normalized maximum dc voltage fluctuation, |∆VC |%max, that

can be used to evaluate the maximum of ∆VC .

|∆VC |%max =

∞∑

k=1

|ICk|CVC

TS × 100[%], (25)

where |ICk| represents the maximum of ICk with respect to

θint, and VC represents the capacitor-voltage reference. Note

that |∆VC |%max is inversely proportional to the unit capacitance

constant of the capacitor, HC [33]. Moreover, it can be

determined uniquely from the two frequencies fS and fC,

the per-unit ac-link inductance Lpuac , the ratio of the dc-link

voltage with respect to the supply voltage, Vdc/VS, and the

ratios of instantaneous active and reactive power p and q with

respect to the rated power, p/P and q/P , respectively. (See

the Appendix.)

Fig. 2 shows analytical values of |∆VC |%max when the carrier

frequency fC lies in a range of 50 to 450 Hz. Table I

summarizes the parameters used for the analysis, along with

TS = 20 ms. The analytical values are calculated from (21),

(22), (25), and (43)–(47). Note that all the components in the

range of k ≤ 50 are considered where fC satisfies a relation

of f ′S ≤ 50.

When f ′S = 1 and fC = nfS with a positive integer n,

|∆VC |%max takes 11% at fC = 100 Hz, 7.2% at fC = 150 Hz,

and less than 1% at fC = 200 Hz where the supply frequency

fS is 50 Hz. Moreover, when f ′S = 2 and fC = nfS/2 with

an odd number of n, it takes 7.7% at fC = 75 Hz, and less

than 1% at fC = 125 Hz. This means that significant voltage

fluctuations occur at fC = 100 Hz and 150 Hz that are twice

and triple as high as the supply frequency fS.

Fig. 3 shows the comparison of mathematical analysis and

numerical evaluation in terms of the normalized dc volt-

age fluctuation ∆V %C over the carrier initial phase θint at

fC = 150 Hz. Note that these values are calculated with the

parameters summarized in Table I. The analytical values of

∆V %C take into account two components at k =1, and 2 in

(24), which are given from

∆V %C =

∆VC

VC× 100 ≈ IC1 + IC2

CVCTS × 100 [%], (26)




6

where TS = 20 ms. On the other hand, by means of using

a spreadsheet program, the numerical evaluation is made as

follows: The ideal simulation of phase-shifted-carrier PWM

generates a gate signal that is equivalent to a switching func-

tion. The product of the switching function and the arm current

yields the current flowing into the corresponding capacitor.

The dc voltage fluctuation can be calculated by integration of

the current with respect to time. It is clear from Fig. 3 that

both mathematical analysis and numerical evaluation agree

well with each other although the mathematical analysis is

completely different from the numerical evaluation. Fig. 3

indicates that the maximum difference in ∆V %C between the

lowest and highest values is 14% over a time interval of 20 ms

at fC = 150 Hz.

D. Effect of vCswn on the AC Component of the Capacitor

Voltage

A combination (n, m′′) of n with another integer of m,

where m′′ = 0, ±m, or ±m ∓ 1, allows expanding the ca-

pacitor switching component vCswn into individual harmonic

component that has a frequency of fCsw(n, m′′)

fCsw(n, m′′) = |nfC +m′′fS|. (27)

Their amplitudes VCsw(n, m′′) are given by

• When both n and |m′′| are even or odd numbers.

VCsw(n, m′′) =

∣

∣

∣

∣

∣

ISan|nωC +m′′ωS|πC

× F(

J|m′′|−1

(nπa

2

)

, J|m′′|+1

(nπa

2

))

∣

∣

∣

∣

∣

. (28)

• When either n or |m′′| is an even or odd number, and the

other is an odd or even number, respectively.

VCsw(n, m′′) =

∣

∣

∣

∣

2IZ0n|nωC +m′′ωS|πC

J|m′′|

(nπa

2

)

∣

∣

∣

∣

. (29)

From (27)–(29), VCsw(n, m′′) is inversely proportional to

fCsw(n, m′′), and decreases as n and |m′′| increase. When

fCsw(n, m′′) = 0, the capacitor voltage can be given as a linear

function. This justifies an assumption of VCsw(n, m′′) = 0.

Equation (16) suggests that the “ac” component contained in

vC generally consists of the first-order (supply-frequency) and

second-order components, as well as the capacitor switching

components. This paper evaluates the ac component as an

arithmetic sum of the amplitudes of all the frequency com-

ponents, VCmax. Equations (16) and (17) give it as follows:

VCmax = VC1+2 +

∞∑

n=1

∞∑

m=−∞

VCsw(n, m′′), (30)

where VC1+2 represents the sum of the amplitudes of the first-

order and second-order components. The normalized value of

the maximum total amplitude V %Cmax in zero-to-peak can be

defined as

V %Cmax =

VCmax

VC× 100 [%]. (31)

V %Cmax

[%]

180

100

80

60

40

20

0fC[Hz]50 100 150 200 250 300 350 400 450

Fig. 4. Mathematical analysis of the maximum amplitude of the ac voltagepresent in vC against the carrier frequency fC .

Like |∆VC |%max in the previous subsection, V %Cmax is inversely

proportional to the unit capacitance constant HC , and can be

determined uniquely from fS, fC, Zpuac , Vdc/VS, p/P , and

q/P .

Fig. 4 shows analytical values of V %Cmax in a range of

fC from 50 to 450 Hz. They are calculated from (28)–(31)

and (43)–(47) with the parameters summarized in Table I,

considering capacitor switching components in a range of

|m| ≤ 4 at n = 1 and |m| ≤ 6 at n = 2. The values of V %Cmax

are almost constant in a range of fC from 400 to 450 Hz in

Fig. 4. This means that the value at fC = 450 Hz corresponds

mostly to VC1+2 because the first term at the right-hand side

on (30) is independent of fC. The remainder of each value in

the range of 50 to 400 Hz would be the capacitor switching

component that decreases as ωC (= 2πfC) in (28) and (29)

increases. On the other hand, when f ′S = 1 and fC = nfS with

a positive integer n, V %Cmax has peak values in the vicinity of

fC = 50, 100, 150 Hz at fS = 50 Hz. Moreover, when f ′S = 2

and fC = nfS/2 with an odd number n, it has a peak value in

the vicinity of 75 Hz at fS = 50 Hz. The reason is that one

of the main frequency components of vCsw(n, m′′) appears in

the vicinity of 0 Hz.

The aim of the individual balancing control is to regulate the

mean dc capacitor voltage. Since the ac component included

in vC acts as a disturbance that may interfere with the current

control system, it should be eliminated by a digital low-pass

filter such as a moving-average filter. Equation (16) indicates

that the ac component includes the first-order frequency (fS),

the second-order frequency (2fS), and capacitor switching fre-

quencies. If all the frequencies are given by integer multiples

of the lowest frequency fL, it is possible to set the moving

window time of a moving-average filter to 1/fL. This makes

it possible to eliminate all the frequency components from the

capacitor voltage. As fL gets higher, the moving window time

gets shorter, thus making the delay time caused by the moving

average filter shorter. It is clear from Fig. 4 that the switching

components are negligible for fC > 200 Hz. As a result, the

ac component consists only the first-order and second-order

frequency components. This leads to a relation of fL = fS, so

that the moving window time can be set to 1/fL = 1/fS.

On the other hand, for fC < 200 Hz, not only the first-

order and second-order frequency components but also the

capacitor switching components should be eliminated by the

moving average filter. The harmonic frequency fCsw(n, m′′)




7

TABLE IICOMPARISONS AMONG SEVEN CARRIER-FREQUENCY CANDIDATES IN A RANGE OF 100 TO 450 HZ

Carrier frequency [Hz] 110 120 125 130 150 175 200

f ′

C/f′

S 11/5 12/5 5/2 13/5 3/1 7/2 4/1

Moving window time [ms] 100 100 40 100 20 40 20

Stable or unstable stable stable stable stable unstable stable unstable*

Reference [16] [16] [16] [16] [16]

* The authors of [16] concluded that the MMC is unstable at the carrier frequency of 200 Hz, whereasthis paper verifies that the DSCC converter is actually stable at this carrier frequency, as shown in Fig. 12.

in (27) takes zero and nfS/f′S with a positive integer n.

This is because the combination of the initial phase of the

modulated waveform with that of the carrier frequency is

periodic with a frequency of fS/f′S. Note that a relation of

fC/fS = f ′C/f

′S indicates that the triangular-carrier waveform

with a period of TC = 1/fC is repeated f ′C times in the

time interval given by multiplying the supply-frequency period

TS = 1/fS by f ′S. This means the existence of a relation of

fL = fS/f′S. Hence, setting a moving window time of the

moving-average filter to 1/fL = f ′S/fS enables eliminating all

the ac components including the first-order and second-order

frequency components. Thus, setting f ′S to be lower makes the

delay time caused by the moving average filter shorter.

IV. OPTIMAL CARRIER FREQUENCIES OBTAINED FROM

THE ANALYSIS

Table II summarizes the comparisons in irreducible fre-

quency fraction f ′C/f

′S, moving window time, and system

stability among seven carrier-frequency candidates in a range

of 100 to 200 Hz, where the supply frequency fS is 50 Hz.

A moving average filter is mandatory for the individual

balancing control in order to extract the dc component from

each capacitor voltage. The moving window time depends on

the ratio of the carrier frequency with respect to the supply

frequency, and dominates dynamic performance of the DSCC

converter.

Figs. 2 and 4, along with Table II, lead to the following

considerations on the seven carrier-frequency candidates:

• Fig. 2 indicates that two carrier frequencies of 100 Hz and

150 Hz should be removed from the optimal candidates

because they cause a dc current to flow into, or out of,

each capacitor, thus resulting in unstable operation. In

other words, both frequencies make f ′S equal to unity in

a range of 2 ≤ fC/fS ≤ 3.

• Fig. 4 suggests that carrier frequencies in the vicinity of

100 Hz and those in the vicinity of 150 Hz should be

removed from the optimal candidates because they bring

large ac voltages to vC .

• Table II concludes that three carrier frequencies of 110,

120, and 130 Hz may be good optimal candidates [16].

However, a moving window time of 100 ms is required

for the moving average filter in order to eliminate ac

components from each capacitor voltage. This may bring

poor dynamic performance to the DSCC converter. On the

other hand, the operation at fC = 125 and 175 Hz have

better dynamic performance than those at fC = 110, 120,

and 130 Hz, since the moving window time is as short as

40 ms at two carrier frequencies of 125 Hz and 175 Hz.

AC Grid AC Grid

DC Grid DC Grid

DC

AC

AC

DC

AC

DC

DC

AC

(a)

(b)

Fig. 5. Basic configurations. (a) A back-to-back (BTB) system between twoac grids. (b) A front-to-front (FTF) system between two dc grids.

• The carrier frequency of 200 Hz can be considered

as a singular frequency. Because the operation at

fC = 200 Hz, where the carrier frequency is an integer

multiple of the supply frequency, causes a dc current to

flow in each capacitor, it is concluded that this carrier

frequency should be avoided based on the theory and

simulation presented in [16]. However, it is clear from

Fig. 2 that the dc current at 200 Hz is much smaller in

amplitude than those at 100 Hz and 150 Hz. Hence, the

individual balancing control forming a voltage feedback

loop can cancel out such a small dc current, thus making

the DSCC converter stable. This interesting finding will

be confirmed both by experiment and computer simula-

tion in the following section.

The above considerations result in the following conclusion:

An optimal carrier frequency is 125 Hz (a frequency ratio of

5/2) in a range of 100 to 200 Hz when priority is given to

a switching-power-loss reduction as well as to good dynamic

performance, where the supply frequency is 50 Hz. Another

is 200 Hz (a frequency ratio of 4/1) when more emphasis is

put on better dynamic performance.

V. DSCC-BASED FTF SYSTEM

A. BTB and FTF Systems

Fig. 5(a) shows a back-to-back (BTB) system that is one of

typical applications of DSCC converters to grid connections.

The BTB system can be used as an interface between two

ac grids. It can act practically as a frequency changer, an

asynchronous power-flow controller, or a bidirectional ac-

to-dc or dc-to-ac power converter in a long-distance high-

voltage dc current (HVDC) system. Fig. 5(b) shows a front-to-

front (FTF) system that is characterized by the combination

of two bidirectional power converters with a single ac-link

transformer, as opposed to the BTB system. Modern DSCC

converters as well as conventional two-level or three-level




8

TABLE IIIMASTER AND SLAVE CONTROL MODES

Role Control Function Frequency

DSCC-A Slave Closed-loop Current source Uncontrollable

DSCC-B Master Open-loop Voltage source Controllable

voltage-source converters are applicable to the FTF system. A

dc-link capacitor is indispensable to the conventional voltage-

source converters. However, it can be eliminated from both

BTB and FTF systems when a pair of DSCC converters are

used, thus resulting in reducing the size and weight, and in

improving system reliability.

Power converters used for grid connections usually share

their respective ac or dc terminals with other converters to

create a common ac or dc link. When an FTF system is

applied to two dc grids, the coupling of one dc grid with the

other is done through an intermediary ac-link transformer for

galvanic isolation and voltage matching. This configuration

can be expanded to use multiple converters connected to

the same ac link, creating the so-called “multiterminal dc-

grid interconnection.” Since the dc voltages are not directly

coupled, a dc fault on one feeder does not propagate directly

to the others. Fast switching operation of the converters used

in the FTF system can isolate the faulty feeder from the rest

of the system.

B. Control Strategy

The FTF system is separated into a master converter and a

slave converter. To work properly, the slave converter (DSCC-

A) should control the power flow while the master converter

(DSCC-B) should maintain the voltage and frequency on the ac

link. In this regard, the slave converter can be seen as a current

source whereas the master converter can be seen as a voltage

source. Table III summarizes the differences in control mode

between DSCC-A and DSCC-B. This strategy makes it easy

to expand the FTF system to a multiterminal interconnection,

where several slave converters are connected to a single master

converter.

Assuming DSCC-B as a master converter, the three-phase

line-to-neutral voltage commands in the master converter can

be written as

v∗uB =

√

2

3Vac sinωt, (32)

v∗vB =

√

2

3Vac sin(ωt−

2π

3), (33)

v∗wB =

√

2

3Vac sin(ωt+

2π

3), (34)

where Vac is the line-to-line rms voltage at the ac side of

the master converter, and ω is the desired frequency of the ac

link, and it can be selected freely, depending on a compromise

between the system size and the switching loss. For medium-

/high-voltage high-power converters, the switching frequency

of the system should be set as low as possible to reduce

the switching loss. On the other hand, using a low switching

frequency may make the response time of the controller slow.

The derived optimal carrier frequency can be regarded as

TABLE IVCIRCUIT PARAMETERS FOR EXPERIMENT

Rated power P 10 kW

Nominal dc voltage E 400 V

AC-link line-to-line voltage Vac 200 V

AC-link frequency fac 180/112.5/50 Hz

Transformer voltage ratio 1 : 1

Chopper-cell number per leg N 16

Capacitor C 6.6 mF

Capacitor mean voltage VC 50 V

Unit capacitance constant HC [33] 40 ms

AC-link inductor Lac 0.4 mH (11.3%*)

Center-tapped inductor LZ 3 mH (84.8%*)

PWM carrier frequency fC 450 Hz

Equivalent switching frequency NfC 7.2 kHz

Dead time 8 µs

Values in ( ) are on a three-phase, 200-V, 10-kW, 180-Hz base.

a compromise between the switching loss and the response

time of the controller. This paper discusses the power flow

control of the FTF system using the derived optimal frequency

ratios, where the carrier frequency is 450 Hz, and the ac-link

frequencies are 180 Hz and 112.5 Hz. However, the analyses

for losses and efficiency of the FTF system are not discussed

and beyond the scope of this paper.

While the master converter has the function of controlling

the ac-link voltage and frequency, the slave converter plays

an important role in adjusting power flow at the voltage

and frequency. The power flow can be adjusted indirectly

by controlling two independent currents on the rotating dqreference frames; the d-axis current for active power and the

q-axis current for reactive power, respectively. Since ac voltage

commands at the master converter are used as a feedforward

input for the decoupled current control, only the three-phase

ac-link currents of the slave converter should be detected to

form a current feedback loop. Hence, neither phase-locked

loop (PLL) circuit nor ac voltage sensor is required for the

control system.

VI. EXPERIMENTAL SETUP

Fig. 6 illustrates the circuit configuration of the DSCC-based

FTF system used in the following experiments. It uses an

adjustable dc power supply for both dc sides, and the ac-link

sides are set at 200 V. Table IV summarizes the parameters

used in the circuit. Each converter circuit consists of 16

chopper cells per leg. A phase-shifted pulsewidth modulation

(PWM) technique is applied to 16 triangular-carrier signals

at a constant frequency of fC = 450 Hz, which are phase-

shifted each other by 22.5◦. Note that the equivalent switching

frequency for each leg is 7.2 kHz. The ac-link frequency facis selected as 180 Hz with fC/fac = 5/2, and 112.5 Hz with

fC/fac = 4/1 from the analysis derived in Section IV.

The overall control system consists of the Texas Instruments

TMS320C6713 digital signal processor (DSP), two Altera

Cyclone II field-programmable gate array (FPGA) units, and

some interface circuits for signal filtering units and multiplexer

(MUX) units. Each FPGA unit detects the 48-to-6 multi-

plexed dc-capacitor voltages, and the positive and negative

arm currents. Note that no ac-link voltage is detected, so

that only 14 analog signals are sent to each FPGA unit.




9

Fig. 1

DSCC-A

(Slave)

Fig. 1

DSCC-B

(Master)

iAvdcA

iBvdcB

idcA idcB

200 V/200 V

180/112.5/50 Hz

MUX: Multiplexer

E400 V

iPAiNA

iPB

iNB

vCA vCB

p∗ q∗

Lac Lac

FPGA-A (Altera Cyclone II) FPGA-B (Altera Cyclone II)DSP

TMS320C6713

gate

signals

96 6 6

gate

signals

9666

48 48

MUX MUX

LPF LPFLPF LPF

Fig. 6. Experimental circuit configuration for the 400-Vdc, 10-kW DSCC-based FTF system with a constant carrier frequency of 450 Hz.

DSCC-ADSCC-B

DAQ-A

DAQ-B

DSP and FPGAs

Fig. 7. Photo of the 400-Vdc, 10-kW DSCC-based FTF system, the digitalcontroller, and data acquisition systems used for experiments.

Each FPGA unit produces 96 (=2×48) gate signals in total

to drive all the chopper cells, each of which consists of four

parallel RENESAS RJK1529 MOSFETs per chopper arm.

Two PC-based data acquisition (DAQ) systems (Yokogawa

WE7000) are simultaneously used for capturing experimental

waveforms. The sampling frequency of the DAQ system was

set to 100 kHz for all operations.

Fig. 7 provides an overview of the DSCC-based FTF system

used for this experiment excluding the transformer. Note that

the transformer and dc capacitors used in this experiment are

optimized for 50-Hz operation. Further reductions in size and

weight should be made, according to the ac-link frequencies

used in the system. An optimum ac-link frequency can be

decided by a good compromise among transformer size and

weight, switching losses, and ac-link harmonic contents.

VII. EXPERIMENTAL AND SIMULATED WAVEFORMS

A. Steady-State Performance With fC/fac = 5/2

Fig. 8 shows the experimental and simulated waveforms

in a steady-state condition for DSCC-A when it is sending

a power of 10 kW to DSCC-B. Fig. 9 shows the respective

experimental and simulated waveforms for DSCC-B. This

experiment was done by setting DSCC-B in master mode and

DSCC-A in slave mode. This means that DSCC-B should act

as a voltage source, while DSCC-A acts as a current source.

It can be seen that the ac link has three-phase multilevel

voltages and sinusoidal currents. Note that neither arm currents

nor capacitor voltages in the v-phase and w-phase legs is

shown in Figs. 8 and 9, because the waveforms differ only

in phase from those in the u-phase leg. The reference voltages

used for generating the ac-link voltages in DSCC-B are used

as feedforward voltages in the decoupled current control for

DSCC-A. Since DSCC-A produced no reactive power, DSCC-

B ran at unity-power-factor operation.

B. Transient Operation With fC/fac = 5/2

Fig. 10 shows the experimental and simulated waveforms

for DSCC-A with slave mode when the power reference is

changed from 10 kW to 8 kW, and then back to 10 kW

for 20 ms with step changes. This section presents only the

waveforms obtained from DSCC-A because the waveforms

from DSCC-B operating as the master converter are similar

to those from DSCC-A. The waveforms show that the system

remains stable although the power reference p∗ was changed

instantaneously. Fig. 11 shows the experimental and simulated

waveforms for the rated-power reversal in DSCC-A. This

experiment can easily be done in the FTF system by generating

the appropriate power reference without altering the polarity

or amplitude of dc-link voltages. The power reference was

changed linearly from 10 kW to −10 kW during an interval

of 20 ms. These results conclude that the power reversal can

be achieved without any problem on the capacitor-voltage

balancing.

C. Experimental Waveforms With fC/fac = 4/1

Fig. 12 shows the experimental waveforms in DSCC-A

for power-reversal operation at another ac-link frequency of

112.5 Hz. Similar results are also obtained for DSCC-B. The

power reference is adjusted with a ramp change of 10 kW to

−10 kW during 20 ms. From this result, it can be concluded

that although the carrier frequency fC is an integer multiple




10

5 ms

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[kW]pdcA

15

0

-15

[A]iPuA

iNuA

50

0

-50

❄

iPuA

(a)

5 ms

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[kW]pdcA

15

0

-15

[A]iPuA

iNuA

50

0

-50

❄

iPuA

(b)

Fig. 8. Experimental and simulated waveforms of DSCC-A with fC/fac = 5/2, operating in the slave mode under the rated inversion. (p∗ = 10 kW,q∗ = 0). (a) Experimental waveforms. (b) Simulated waveforms.

5 ms

[V]vuvBvvwB

vwuB

400

0

-400

❄

vuvB

[A]iuBivBiwB

50

0

-50

❄

iuB

[V]vC1uB

vC9uB

75

50

25

0

❄

vC1uB

[kW]pdcB

15

0

-15

[A]iPuB

iNuB

50

0

-50

❄

iPuB

(a)

5 ms

[V]vuvBvvwB

vwuB

400

0

-400

❄

vuvB

[A]iuBivBiwB

50

0

-50

❄

iuB

[V]vC1uB

vC9uB

75

50

25

0

❄

vC1uB

[kW]pdcB

15

0

-15

[A]iPuB

iNuB

50

0

-50

❄

iPuB

(b)

Fig. 9. Experimental and simulated waveforms of DSCC-B with fC/fac = 5/2, operating in the master mode under the rated rectification. (p∗ = 10 kW,q∗ = 0). (a) Experimental waveforms. (b) Simulated waveforms.

of the ac-link frequency fac with a ratio of four, the FTF

system can run in stable operation under both steady-state and

transient conditions. The simulated results have very similar

waveforms but are not shown due to page limitation reason.

D. Comparison in Capacitor Voltage Fluctuation

Fig. 13 shows the experimental waveforms of the capacitor

voltage fluctuation under the following three ac-link frequen-

cies: fac = 50, 112.5, and 180 Hz, where the carrier frequency

fC was kept constant at 450 Hz. The ac-link inductor Lac for

the 50-Hz case is 2 mH instead of 0.4 mH. The peak-to-peak

ripple voltage ∆vCju for all the cases are 8.6 V, 3.8 V, and

3.5 V at 50 Hz, 112.5 Hz, and 180 Hz, respectively. For the

180-Hz ac-link frequency case, the peak-to-peak ripple voltage

∆vCju corresponds to 7% of the rated dc capacitor voltage. It

is obvious that the peak-to-peak ripple voltage of the capacitors

gets higher as the ac-link frequency gets lower, as long as the

same capacitance value is used.

E. Harmonic Frequency Spectra of Capacitor Voltage

Figs. 14 and 15 show the normalized values of analytical,

experimental, numerical, and simulated harmonic frequency




11

20 ms[kW]p∗

15

0

-15

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[A]iPuA

iNuA

50

0

-50

❄

iPuA

[kW]pdcA

15

0

-15

(a)

20 ms[kW]p∗

15

0

-15

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[kW]pdcA

15

0

-15

[A]iPuA

iNuA

50

0

-50

❄

iPuA

(b)

Fig. 10. Experimental and simulated waveforms of DSCC-A with fC/fac = 5/2, operating in the slave mode under a step change of power reference p∗.(a) Experimental waveforms. (b) Simulated waveforms.

20 ms[kW]p∗

15

0

-15

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[A]iPuA

iNuA

50

0

-50

❄

iPuA

[kW]pdcA

15

0

-15

(a)

20 ms[kW]p∗

15

0

-15

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[kW]pdcA

15

0

-15

[A]iPuA

iNuA

50

0

-50

❄

iPuA

(b)

Fig. 11. Experimental and simulated waveforms of DSCC-A with fC/fac = 5/2, operating in the slave mode under the rated-power reversal from inversionto rectification during an interval of 20 ms. (a) Experimental waveforms. (b) Simulated waveforms.

spectra of vC1u on the slave converter at fac = 180 Hz

and 112.5 Hz, respectively, under the rated power inversion.

The figures show that all harmonic spectra agree well with

each other. Note that the harmonic components caused by

switching action influence the capacitor voltage fluctuation

when the ratio of the carrier frequency with respect to the ac-

link frequency gets lower. The harmonic components caused

by switching action include not only the second-order and




12

20 ms[kW]p∗

15

0

-15

[V]vuvAvvwA

vwuA

400

0

-400

❄

vuvA

[A]iuAivAiwA

50

0

-50

❄

iuA

[V]vC1uA

vC9uA

75

50

25

0

❄

vC1uA

[A]iPuA

iNuA

50

0

-50

❄

iPuA

[kW]pdcA

15

0

-15

Fig. 12. Experimental waveforms for DSCC-A with fC/fac = 4/1 underthe rated-power reversal operation.

20 ms[V]vC1uB

vC9uB

60

50

40

❄

vC1uB

[V]vC1uB

vC9uB

60

50

40

❄

vC1uB

[V]vC1uB

vC9uB

60

50

40

❄

vC1uB

fac = 50 Hz

fac = 112.5 Hz

fac = 180 Hz

Fig. 13. Experimental comparison in capacitor voltage fluctuation amongthree ac-link frequencies, fac = 50, 112.5, and 180 Hz at the same carrierfrequency as fC = 450 Hz.

carrier-frequency components but also the sideband frequen-

cies around the integer multiples of the carrier frequency.

When fac = 180 Hz and fC = 450 Hz, the lowest harmonic

frequency fL is 90 Hz (= fC− 2fac) on the capacitor voltage

fluctuation. Correspondingly, the moving window time of the

moving-average filter, which is used for the voltage-balancing

control of all the dc capacitors, is set on the basis of the lowest

harmonic frequency, i.e., 1/fL. On the other hand, for the ac-

link frequency of 112.5 Hz, the lowest harmonic frequency fLis the same as 112.5 Hz, so that the moving window time can

be set as 1/fac. Although the capacitor voltages are fluctuating

at 112.5 Hz and its integer multiples, the average capacitor

voltages can be kept at 50 V by using an appropriate moving-

average filter incorporated in the voltage-balancing control.

��

��

��

��

��

� ��

� ��

��

��

��

��

��

��

��

��

� ��

��

��

��

��

��

� ��

��

��

��

��

V %C1uA[%]

4

3

2

1

0

Analytical

Experimental

Numerical

Simulated

180 360 540 720 900 1080 1260 f [Hz]

Fig. 14. Frequency spectra of the ac components contained in vC1u of DSCC-A at fac = 180 Hz and fC = 450 Hz.

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

��

� ��

��

��

��

V %C1uA[%]

4

3

2

1

0

Analytical

Experimental

Numerical

Simulated

225 450 675 900 1125 1350 1575 f [Hz]

Fig. 15. Frequency spectra of the ac components contained in vC1u of DSCC-A at fac = 112.5 Hz and fC = 450 Hz.

VIII. CONCLUSION

This paper has provided theoretical and experimental dis-

cussions on optimal carrier frequencies and their effect on

voltage-balancing performance of each floating capacitor in a

three-phase DSCC converter with phase-shifted-carrier PWM.

This paper has concluded that an optimal frequency ratio of

the carrier frequency with respect to the supply (ac) frequency

is 5/2 when priority is given to a switching-power-loss re-

duction. This paper has also presented a front-to-front (FTF)

system consisting of a pair of modular multilevel cascade con-

verters based on double-star chopper cells (MMCCs-DSCC)

and a three-phase medium-frequency transformer for voltage

matching and galvanic isolation. The system configuration is

applicable to a high-voltage high-power bidirectional isolated

dc-to-dc converter. The voltage and frequency of the ac link

can be controlled directly by the master converter. As a

result, neither phase-locked loop (PLL) circuit nor ac voltage

sensor is required. The viability and validity of the system

have been verified by experimental and simulated results.

The FTF system based on phase-shifted PWM with optimal

carrier frequency ratios of fC/fac = 5/2 and 4/1 yields

stable operation and provides good dynamic performance. The

experimental and simulated results agree well with those from

the numerical and mathematical analyses developed in this

paper.

APPENDIX

From circuit symmetry in Fig. 1, the u-phase variables are

considered. Let the supply line-to-neutral voltage be vSu and




13

the supply current be iSu as

vSu =

√

2

3VS sinωSt, (35)

iSu =√2IS sin (ωSt+ φ′

i), (36)

where IS and φ′i are given by

IS =

√

p2 + q2√3VS

, (37)

φ′i = − tan−1 q

p. (38)

Equations (35)–(38) and Kirchhoff’s voltage law give the u-

phase ac terminal voltage of the DSCC converter vu as follows:

vu = vSu − LacdiSudt

=

√

2

3V sin (ωSt+ φ′

v), (39)

where a relation of Zpuac = ωSLacP/V

2S allows representing

V and φ′v in (39) as follows:

V = VS

√

(

1− q

PZpuac

)2

+( p

PZpuac

)2

, (40)

φ′v = − tan−1 pZpu

ac /P

1− qZpuac /P

. (41)

The following relation exists between the dc-link voltage of

the DSCC converter, Vdc and the dc voltage of each chopper

cell, VC [10].

Vdc =NVC

2. (42)

Equations (4), (5), (10), and (39)–(42) give the modulation

factor a and phase φv as follows:

a = 2

√

2

3

VS

Vdc

√

(

1− q

PZpuac

)2

+( p

PZpuac

)2

, (43)

φv =

{

− tan−1 pZpuac /P

1−qZpuac /P

+ π for the positive arm

− tan−1 pZpuac /P

1−qZpuac /P

for the negative arm.

(44)

The dc component of the arm current, IZ0 is given by

IZ0 = − p

3Vdc. (45)

Equations (2), (3), (13), (37), and (38) give the amplitude and

phase of the 50-Hz component of the arm current as

ISa =

√2

2IS =

√

p2 + q2√6VS

, (46)

φi =

{

− tan−1 q/p+ π for the positive arm

− tan−1 q/p for the negative arm.(47)

Equations (10), (13), and (16) give the amplitude and phase

of the fundamental frequency component of the capacitor

voltage as follows:

VC1 =1

2ωSC

√

a2I2Z0 + I2Sa + 2aIZ0ISa cos(φv − φi), (48)

φ′ = tan−1 aIZ0 sinφv + ISa sinφi

aIZ0 cosφv + ISa cosφi

. (49)

Equation (25) suggests the following relation of

|∆VC |%max ∝∑∞

k=1 |ICk|/CVC . It is clear from (20),

(21) and (22) that |ICk|/CVC has a function of f ′S, f ′

C,

a, φv − φi, ISa/CVC , and IZ0/CVC . Once fS and fC are

determined, f ′S and f ′

C are determined uniquely. Equations

(43), (44), and (47) indicate that a and φv − φi depend only

on Zpuac , Vdc/VS and p/P , q/P . Equations (42), (45), and

(46) give ISa/CVC and IZ0/CVC as follows:

ISaCVC

=1

HC

√

3

2

Vdc

VS

√

( p

P

)2

+( q

P

)2

, (50)

IZ0CVC

= − 1

HC

p

P, (51)

where HC in the above two equations is the unit capacitance

constant of the DSCC converter, and is defined as [33]

HC = 3NCV 2C/2P. (52)

REFERENCES

[1] H. Akagi, “Classification, terminology, and application of the modularmultilevel cascade converter (MMCC),” IEEE Trans. Power Electron.,vol. 26, no. 11, pp. 3119–3130, Nov. 2011.

[2] R. Marquardt and A. Lesnicar, “A new modular voltage source invertertopology,” in Proc. EPE 2003, pp. 2–4.

[3] M. Glinka, “Prototype of multiphase modular-multilevel-converter with2 MW power rating and 17-level-output-voltage,” in Proc. IEEE PESC

2004, pp. 2572–2576.

[4] M. Glinka and R. Marquardt, “A new ac/ac multilevel converter family,”IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662–669, Jun. 2005.

[5] M. Hagiwara and H. Akagi, “PWM control and experiment of modularmultilevel converters,” in Proc. IEEE PESC 2008, pp. 154–161.

[6] M. Hagiwara and H. Akagi, “Control and experiment of pulsewidth-modulated modular multilevel converters,” IEEE Trans. Power Electron.,vol. 24, no. 7, pp. 1737–1746, Jul. 2009.

[7] M. Hagiwara, K. Nishimura, and H. Akagi, “A medium-voltage motordrive with a modular multilevel PWM inverter,” IEEE Trans. Power

Electron., vol. 25, no. 7, pp. 1786–1799, Jul. 2010.

[8] H. Peng, M. Hagiwara, and H. Akagi, “Modeling and analysis ofswitching-ripple voltage on the dc link between a diode rectifier anda modular multilevel cascade inverter (MMCI),” IEEE Trans. Power

Electron., vol. 28, no. 1, pp. 75–84, Jan. 2013.

[9] M. Hagiwara, I. Hasegawa, and H. Akagi, “Start-up and low-speedoperation of an adjustable-speed motor driven by a modular multilevelcascade inverter (MMCI),” IEEE Trans. Ind. Appl., vol. 49, no. 4,pp. 1556–1565, Jul./Aug. 2013.

[10] K. Sekiguchi, P. Khamphakdi, M. Hagiwara, and H. Akagi, “A grid-level high-power BTB (Back-To-Back) system using modular multilevelcascade converters without common dc-link capacitor,” IEEE Trans. Ind.

Appl., vol. 50, no. 4, pp. 2648–2659, Jul./Aug. 2014.

[11] Y. Okazaki, M. Hagiwara, and H. Akagi, “A speed-sensorless start-up method of an induction motor driven by a modular multilevelcascade inverter (MMCI-DSCC),” IEEE Trans. Ind. Appl., vol. 50, no. 4,pp. 2671–2680, Jul./Aug. 2014.

[12] P. Khamphakdi, K. Sekiguchi, M. Hagiwara, and H. Akagi, “A trans-fomerless back-to-back (BTB) system using modular multilevel cascadeconverters for power distribution systems,” IEEE Trans. Power Electron.,vol. 30, no. 4, pp. 1866–1875, Apr. 2015.

[13] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo,B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advancesand industrial applications of multilevel converters,” IEEE Trans. Power

Electron. vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[14] M. A. Perez, S. Bernet, J. Rodriguez, S. Kouro, and R. Lizana, “Circuittopologies, modeling, control schemes, and applications of modularmultilevel converters,” IEEE Trans. Power Electron. vol. 30, no. 1, pp. 4–17, Jan. 2015.

[15] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard, and P. Barbosa, “Oper-ation, control, and applications of the modular multilevel converter: areview,” IEEE Trans. Power Electron. vol. 30, no. 1, pp. 37–53, Jan.2015.




14

[16] K. Ilves, L. Harnefors, S. Norrga, and H.-P. Nee, “Analysis and operationof modular multilevel converters with phase-shifted carrier PWM,” IEEETrans. Power Electron. vol. 30, no. 1, pp. 268–283, Jan. 2015.

[17] B. Li, R. Yang, D. Xu, G. Wang, W. Wang, and D. Xu, “Analysis ofthe phase-shifted carrier modulation for modular multilevel converters,”IEEE Trans. Power Electron. vol. 30, no. 1, pp. 297–310, Jan. 2015.

[18] Q. Tu, Z. Xu, and L. Xu, “Reduced switching-frequency modulationand circulating current suppression for modular multilevel converters,”IEEE Trans. Power Del. vol. 26, no. 3, pp. 2009–2017, Jul. 2011.

[19] M. Saeedifard and R. Iravani, “Dynamic performance of a modularmultilevel back-to-back HVDC system,” IEEE Trans. Power Del. vol. 25,no. 4, pp. 2903–2912, Oct. 2010.

[20] J. Mei, B. Xiao, K. Shen, L. M. Tolbert, and J. Y. Zhen, “Modularmultilevel inverter with new modulation method and its application tophotovoltaic grid-connected generator,” IEEE Trans. Power Electron.

vol. 28, no. 11, pp. 5063–5073, Nov. 2013.[21] S. Fan, K. Zhang, J. Xiong, and Y. Xue, “An improved control system for

modular multilevel converters with new modulation strategy and voltagebalancing control,” IEEE Trans. Power Electron. vol. 30, no. 1, pp. 358–371, Jan. 2015.

[22] R. Darus, J. Pou, G. Konstantinou, S. Ceballos, R. Picas, and V. G.Agelidis, “A modified voltage balancing algorithm for the modular mul-tilevel converter: evaluation for staircase and phase-disposition PWM,”IEEE Trans. Power Electron. vol. 30, no. 8, pp. 4119–4127, Aug. 2015.

[23] A. Hassanpoor, S. Norrga, H.-P. Nee, and L. Angquist, “Evaluation ofdifferent carrier-based PWM methods for modular multilevel convertersfor HVDC application,” in Proc. IEEE IECON 2012, pp. 388–393.

[24] X. Shi, Z. Wang, L. M. Tolbert, and F. Wang, “A comparison ofphase disposition and phase shift PWM strategies for modular multilevelconverters,” in Proc. IEEE ECCE 2013, pp. 4089–4096.

[25] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, “Modulation, losses,and semiconductor requirements of modular multilevel converters,”IEEE Trans. Ind. Electron. vol. 57, no. 8, pp. 2633–2642, Aug. 2010.

[26] A. Hassanpoor, L. Angquist, S. Norrga, K. Ilves, and H-. P. Nee,“Tolerance band modulation methods for modular multilevel converters,”IEEE Trans. Power Electron. vol. 30, no. 1, pp. 311–326, Jan. 2015.

[27] M. S. A. Dahidah, G. Konstantinou, and V. G. Agelidis, “A review ofmultilevel selective harmonic elimination PWM: formulations, solvingalgorithms, implementation and applications,” IEEE Trans. Power Elec-

tron. vol. 30, no. 8, pp. 4091–4106, Aug. 2015.[28] Q. Tu and Z. Xu, “Impact of sampling frequency on harmonic distortion

for modular multilevel converter,” IEEE Trans. Power Del. vol. 26, no. 1,pp. 298–306, Jan. 2011.

[29] S. Du, J. Liu, and T. Liu, “Modulation and closed-loop-based dc capac-itor voltage control for MMC with fundamental switching frequency,”IEEE Trans. Power Electron. vol. 30, no. 1, pp. 327–338, Jan. 2015.

[30] K. Ilves, L. Harnerfors, S. Norrga, and H-. P. Nee, “Predictive sortingalgorithm for modular multilevel converters minimizing the spread inthe submodule capacitor voltages,” IEEE Trans. Power Electron. vol. 30,no. 1, pp. 440–449, Jan. 2015.

[31] P. M. Meshram and V. B. Bhorgate, “A simplified nearest level con-trol (NLC) voltage balancing method for modular multilevel converter(MMC),” IEEE Trans. Power Electron. vol. 30, no. 1, pp. 450–462, Jan.2015.

[32] D. Siemaszko, “Fast sorting method of balancing capacitor voltages inmodular multilevel converters,” IEEE Trans. Power Electron., vol. 30,no. 1, pp. 463–470, Jan. 2015.

[33] H. Fujita, S. Tominaga, and H. Akagi: “Analysis and design of a dcvoltage-controlled static var compensator using quad-series voltage-source inverters,” IEEE Trans. Ind. Appl., vol. 32, no. 4, pp. 970–978,Jul./Aug. 1996.


Documents

Theory and Experiment on an Optimal Carrier Frequency of a Modular Multilevel …iranswitching.ir/wp-content/uploads/2016/01/Theory-and... · 2016-01-28 · ular multilevel cascade