The Von Neumann Model

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The Von Neumann ModelThe Von Neumann Model

• Proposed in 1946Proposed in 1946

• Two main ideas:Two main ideas:• components of an architecturecomponents of an architecture• how instructions are processedhow instructions are processed



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Basic ArchitectureBasic Architecture

• memorymemory

• processorprocessor• inputinput• outputoutput• control unitcontrol unit

contains instructions that comprisecontains instructions that comprise a programa program

executes the instructionsexecutes the instructions

orders the execution of the instructionsorders the execution of the instructions

an an instructioninstruction is a unit of work is a unit of work



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OrganizationOrganization



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LC-2 OrganizationLC-2 Organization



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MemoryMemory

• Recall the 2Recall the 222 by 3 memory of Ch. 3 by 3 memory of Ch. 3• more realistically, many PCs aremore realistically, many PCs are

• 222828 address space (256 MB) address space (256 MB)• 8 bit addressability8 bit addressability

• LC-2 is 2LC-2 is 21616 by 16 by 16



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Special RegistersSpecial Registers

• MAR: memory address registerMAR: memory address register• location to be read/writtenlocation to be read/written

• MDR: memory data registerMDR: memory data register• data value to be read/writtendata value to be read/written

• what has to be asserted for a value to be what has to be asserted for a value to be written?written?



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Contents of Memory/RegistersContents of Memory/Registers

00 0 1 000 0 1 001 1 1 101 1 1 110 0 0 110 0 0 111 0 0 011 0 0 0

MemoryMemory

MARMAR MDRMDR WEWE

0 0 10 0 1 1 1 11 1 1 0 0

0 1 00 1 0 1 1 01 1 0 1 1

Causes memory to beCauses memory to be read intoread into MDRMDR

Causes memory to beCauses memory to be written fromwritten from MDRMDR

00 0 1 000 0 1 001 1 1 101 1 1 110 1 1 010 1 1 011 0 011 0 0 00



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Processing UnitProcessing Unit

• may contain specialized functional unitsmay contain specialized functional units• LC-2 ALU has only ADD, AND, NOT LC-2 ALU has only ADD, AND, NOT

operationsoperations

• size of information processed by ALUsize of information processed by ALU

is the is the word lengthword length of the computer of the computer• LC-2 has 16 bit word lengthLC-2 has 16 bit word length



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RegistersRegisters

• temporary storage used by CPU for temporary storage used by CPU for intermediate values of computationsintermediate values of computations

• DEC Alpha has 32 registersDEC Alpha has 32 registers• LC-2 has 8 (R0-R7)LC-2 has 8 (R0-R7)



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Input/outputInput/output

• peripherals that allow computer to be peripherals that allow computer to be connected to the outside worldconnected to the outside world

• get data/programs in and outget data/programs in and out• input: keyboard, mouse, scanners, disksinput: keyboard, mouse, scanners, disks• output: monitor, printers, disksoutput: monitor, printers, disks

• floppy, hard drives, zip disks, CDsfloppy, hard drives, zip disks, CDs



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Control UnitControl Unit

• keeps track of current instruction in a keeps track of current instruction in a program and current step in executing an program and current step in executing an instructioninstruction

• coordinates activities between componentscoordinates activities between components• registersregisters

• IR: holds current IR: holds current instructioninstruction• PC: holds PC: holds addressaddress of next instruction of next instruction



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Discuss LC-2 as an Example ofDiscuss LC-2 as an Example ofa Von Neumann Architecturea Von Neumann Architecture

• some registers not yet discussedsome registers not yet discussed• KBSR: status of keys struckKBSR: status of keys struck• KBDR: value of key struckKBDR: value of key struck• CRTSR: status of monitorCRTSR: status of monitor• CRTDR: value to be written on monitorCRTDR: value to be written on monitor



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Central ideas of VN architectureCentral ideas of VN architecture

• Instructions and data are both sequences of Instructions and data are both sequences of bits stored in memorybits stored in memory

• One instruction at a time is executed One instruction at a time is executed (sequentially)(sequentially)



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Instruction ProcessingInstruction Processing

• 2 parts:2 parts:• opcodeopcode: what is to be done: what is to be done• operands: what data is manipulatedoperands: what data is manipulated

• LC-2 instruction:LC-2 instruction:• [15:12] [15:12] opcodeopcode• [11:0] how to locate operands[11:0] how to locate operands

• How many distinct operations in LC-2?How many distinct operations in LC-2?



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ADD ExampleADD Example

• opcode for ADD is 0001opcode for ADD is 0001• ADD requires values to be pre-stored in ADD requires values to be pre-stored in

registers, then the result is stored in a registers, then the result is stored in a registerregister

• Operands from register2 and register 3, Operands from register2 and register 3, result put in register 1result put in register 1

opcode register 1 register 2 not used register 3opcode register 1 register 2 not used register 3

15………12 11……………9 8……….….6 5…..……..3 2………...015………12 11……………9 8……….….6 5…..……..3 2………...0



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LDR ExampleLDR Example

• load register with a value from memoryload register with a value from memory• causes value of 2nd register to be added causes value of 2nd register to be added

to offset value, and value at that location to offset value, and value at that location is stored in 1st registeris stored in 1st register

• opcode for LDR is 0110opcode for LDR is 0110

opcode register 1 register2 offsetopcode register 1 register2 offset

15………12 11……………9 8…..…….6 5………….0..15………12 11……………9 8…..…….6 5………….0..



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LDR cont’dLDR cont’d

15………12 11……………9 8……………….6 5………………….….015………12 11……………9 8……………….6 5………………….….0

0110 010 011 0001100110 010 011 000110

value (2nd register + offset) stored in 1st registervalue (2nd register + offset) stored in 1st register

contents of memory in location (R3 + 6) goes into R2contents of memory in location (R3 + 6) goes into R2

called called base + offsetbase + offset addressing mode addressing mode

addressing modeaddressing mode: describes the computation needed to: describes the computation needed toyield values for operandsyield values for operands



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The Instruction CycleThe Instruction Cycle

• Sequence of steps carried out by control Sequence of steps carried out by control unit to execute instructionsunit to execute instructions

• called called phasesphases• 6 phases, all may not be used by each 6 phases, all may not be used by each

instructioninstruction



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Fetch-Decode-Execute CycleFetch-Decode-Execute Cycle

1.1. fetchfetch: gets next instruction from : gets next instruction from memory into IRmemory into IR

MAR PCMAR PC

MDR contents of memory at MDR contents of memory at location given in location given in

MARMAR

IR MDRIR MDR

PC PC + 1PC PC + 1



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Fetch-Decode-Execute CycleFetch-Decode-Execute Cycle

2.2. decodedecode:: in LC-2, a 4 to 16 decoder in LC-2, a 4 to 16 decoder looks at the 4 opcode bits and asserts the looks at the 4 opcode bits and asserts the appropriate output line to indicate the appropriate output line to indicate the instruction to be executedinstruction to be executed

3.3. evaluate addressevaluate address: if a memory address is : if a memory address is to be accessed (as in LDR) this phase to be accessed (as in LDR) this phase computes the addresscomputes the address

not needed in ADDnot needed in ADD



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Fetch-Decode-Execute CycleFetch-Decode-Execute Cycle4.4. fetch fetch operands: obtains values of operands: obtains values of

operandsoperands

5. execute: carries out instruction in 5. execute: carries out instruction in ALUALU

6. store result: write result to designated6. store result: write result to designateddestinationdestination

LDR gets value from memory into a registerLDR gets value from memory into a register

ADD gets values from registersADD gets values from registers

not needed in LDRnot needed in LDR

increment PC, go to 1increment PC, go to 1



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Changing the Execution OrderChanging the Execution Order

• 2 issues:2 issues:• how to alter the execution order?how to alter the execution order?• how to stop at the end of a program?how to stop at the end of a program?

• have to change the PC before the next have to change the PC before the next fetch phasefetch phase



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Instruction TypesInstruction Types• 3 kinds of instructions:3 kinds of instructions:

• operate (e.g., ADD)operate (e.g., ADD)• move data (e.g., LDR)move data (e.g., LDR)• control instruction (e.g., JMPR)control instruction (e.g., JMPR)

• control instructions load the PC control instructions load the PC during the execute phaseduring the execute phase



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JMPR ExampleJMPR Example

• puts an address in the PCputs an address in the PC• useful for executing loops or skipping arounduseful for executing loops or skipping around• uses base + offset addressinguses base + offset addressing• JMPR opcode is 1100JMPR opcode is 1100

opcode not used register1 offsetopcode not used register1 offset15………12 11……………9 8……………….6 5……………….015………12 11……………9 8……………….6 5……………….0



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Tying It All Together:Tying It All Together:Example AlgorithmExample Algorithm

1. Initialize a counter to 12 and a sum to 0.1. Initialize a counter to 12 and a sum to 0.

2. If counter is 0, go to step 7.2. If counter is 0, go to step 7.

3. else get next data item;3. else get next data item;

4. add item to sum;4. add item to sum;

5. decrement counter;5. decrement counter;

6. Output “sum is:” sum.6. Output “sum is:” sum.

7. End7. End



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Machine Language ExampleMachine Language Example

30003000 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0

30013001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0

30023002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0

30033003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0

3004 3004 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 00 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

30053005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0

30063006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0

30073007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1

30083008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1

30093009 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0

LEA R1, x3100LEA R1, x3100

AND R3, 0AND R3, 0

AND R2, 0AND R2, 0

ADD R2, 12ADD R2, 12

BRz R2, x300ABRz R2, x300A

LDR R4, M[R1]LDR R4, M[R1]

ADD R3, R4ADD R3, R4

ADD R1, 1ADD R1, 1

ADD R2, -1ADD R2, -1

BRnzp x3004BRnzp x3004

Corresponding Assembly LanguageCorresponding Assembly Language

opcodesopcodes



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C++ ExampleC++ Example

// assumes an array holding 12 integers// assumes an array holding 12 integers

// has been declared and initialized// has been declared and initialized

int sum = 0;int sum = 0;

for (int i = 0; i < 12; i++)for (int i = 0; i < 12; i++)

sum = sum + array[i];sum = sum + array[i];

LEA R1, x3100LEA R1, x3100AND R3, 0AND R3, 0AND R2, 0AND R2, 0ADD R2, 12ADD R2, 12BRz R2, x300ABRz R2, x300ALDR R4, M[R1]LDR R4, M[R1]ADD R3, R4ADD R3, R4ADD R1, 1ADD R1, 1ADD R2, -1ADD R2, -1BRnzp x3004BRnzp x3004



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Example continuedExample continued

31003100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

31013101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

31023102 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

31033103 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

31043104 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

31053105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

31063106 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

31073107 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

31083108 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

31093109 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

310A310A 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1

310B310B 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

310C310C 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1

Data memory containing 12 values to sumData memory containing 12 values to sum Register s usedRegister s used

R1 – address of R1 – address of data valuedata value

R2 – number of R2 – number of data values left data values left to addto add

R3 – Sum of values R3 – Sum of values which have been which have been addedadded

R4 – current value R4 – current value to add to the sumto add to the sum



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Contents of Registers, first time thru the loopContents of Registers, first time thru the loop (in hexadecimal(in hexadecimal))

After After instruction instruction 30053005

3100R1R1

R2R2

R3R3

R4R4

000C

0000

0001

After After instruction instruction 30083008

3101R1R1

R2R2

R3R3

R4R4

000B

0001

0001



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Contents of Registers, 2Contents of Registers, 2ndnd time thru the loop time thru the loop (in hexadecimal(in hexadecimal))

After After instruction 3005instruction 3005

3101R1R1

R2R2

R3R3

R4R4

000B

0001

0002


3102R1R1

R2R2

R3R3

R4R4

000A

0003

0002



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Contents of Registers, 3Contents of Registers, 3rdrd time thru the loop time thru the loop (in hexadecimal)(in hexadecimal)


3102R1R1

R2R2

R3R3

R4R4

000A

0003

0003


3103R1R1

R2R2

R3R3

R4R4

0009

0006

0003



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Contents of Registers , 12Contents of Registers , 12thth time thru the loop time thru the loop (in hexadecimal)(in hexadecimal)


310CR1R1

R2R2

R3R3

R4R4

0001

0042

000D


310DR1R1

R2R2

R3R3

R4R4

0000

004E

000D



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Foundation for ProgrammingFoundation for Programming• When you write C++ programs next When you write C++ programs next

quarter, you know they are translated to quarter, you know they are translated to assembly language by a compilerassembly language by a compiler

• then translated to machine language to then translated to machine language to be executed by the hardwarebe executed by the hardware

• hardware consists of functional units in hardware consists of functional units in Von Neumann architectureVon Neumann architecture

• functional units are made up of gatesfunctional units are made up of gates• gates are implemented by transistorsgates are implemented by transistors

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The Von Neumann Model