The VLSI Systems Center - BGU AMS – Test Manual by Slava Fleshel 309284222

The VLSI Systems Center - BGUThe VLSI Systems Center - BGU

AMS – TestAMS – TestManual Manual

by Slava Fleshel 309284222by Slava Fleshel 309284222


TopicsTopics CautionsI. Getting StartedII. Start building the TestIII. Open “Analog environment”

IV. Setting Analog EnvironmentV. Run the SimulationVI. Failures & Solutions


CAUTIONSCAUTIONSIn the design, cell names, net names

except primitive cells should be ALL lowercaselowercase (minuscule)!!

Also it should not contain the “escapedescaped” characters (+,=,-,&…)!!

If you have big design, do not save all nets on all hierarchies it can cause a serious problems, and the simulation would not run!!


Getting StartedGetting Started I. First you should check that all

directories you need for the test and have cell’s in them are written in the “Library Path Editor”, a spatially you shouldn’t forget the directory of “Connect rules” if needed. In fig’ 1 shown the example of how can “Library Path Editor” look.


Figure 1 :Figure 1 :


II. Now you can start building the Test. a. Create “schematic view” of the cell you want

to simulate and create in it your test bench. b. Now go to “Library Manager” and push

create a new view:


The menu “Create New File” will appear:

Choose “Tool” to be an “Hierarchy-Editor” and check that “View Name” changed to “config”, then click “ok”. The Hierarchy Editor will appear.

c. In order to use Hierarchy Editor you need to set up few thinks: Set view to schematic (you can use, to do so, the

browse button, fig-2). Set the “global bindings”:


Figure 2:


1. “Library List”: Hear you should insert all libraries, that you make

use of there ingredients (like:tsmc18sc – for standard cells you use in the design, or analogLib – for supply's that you use in the test). It is very important not to forget any of libraries, cause the Hierarchy Editor will not find the cell that in its library!!! (Figure 3)

2. “View List”: First you should check which view’s it possible to use

in your design and than insert all the possibilities to “View List” (for example: functional – you will use it in digital parts of the design). It is very important not to forget any of view’s, cause the Hierarchy Editor will not find the cell that use this view!!! (Figure 3)

3. “Stop List”: Insert the views that you don’t want to see in

Hierarchy Editor.


Figure 3

back


After doing all this your Hierarchy Editor configuration window will look like this:

Now just click “ok” . That is the Hierarchy Editor you will finally Now just click “ok” . That is the Hierarchy Editor you will finally get:get:


Now just save it and close every thing!


III. Open the “config” view from Library Manager and choose to open Hierarchy EditorHierarchy Editor with with Schematic. When it opened go to “Tools” in Schematic. When it opened go to “Tools” in schematic and choose an “Analog schematic and choose an “Analog environment”:environment”:


The icon of Analog Environment will appear:

IV. Setting Analog Environment:1. Choose the simulator you want to work with:

In icon of Analog Environment go to “setup” -> “simulator/directory/host…”, the window

“Choose simulator/directory/host…” will pop up:


Then click “ok”

Choose “ams” simulator, your project directory, and host mode:


After you click “ok” you can notice that in schematic view now appears new field “AMS”

and in the right upper corner of Analog Environment will be written “Simulator :“ams”


2. Choosing the correct “Connect rules”: In Analog Environment go to “setup” ->

“Connect rules”:

The icon of “Select Connect Rules” will pop up:


If the rule that appears there not the correct one, you should delete it by choosing the rule and pushing delete button :


Then make sure you in “Built-in” mode and push “Customize…” button, the customization menu will pop up:


Choose there the relevant rule, check the parameters of it and click “ok”, it will bring you back to “connect rule” menu:


Click the “Add” button the rule you have chosed will appear in the window below. Now click “ok” to save your choice.


3. Definition of the simulation models for your design:

in “Analog Environment” choose “Setup” -> "Model Libraries”:


The “Model Libraries setup” will appear:

Through “browse” button choose the Model Library you desire. Also you can enable and disable any library you need/don’t need in any time. The disabled one will appear with “#” at the left side. Click “ok” when it’s done.


4. The Analyses definition: In Analog Environment choose “Analyses” ->

“Choose…”

The “Choosing Analyses” menu will pop up:


In this menu choose the needed Analysis (in our case it is ”tran”), and in the field of “Stop Time” insert the duration of the simulation. Enable your analysis and click “ok”.


In Analog Environment you can confirm that the analysis you’ve chosen is correct, it written in “Analyses” window:


5. Variables Definition: In Analog Environment choose “Variables” ->

“Copy From Cellview” :

When it will finish copying, you will notice in the left bottom corner named “Design Variables” all the variables from your design (if you have any):


In our case it “Vin”. To define it’s voltage you can double click it, or in Analog Environment choose “Variables” -> “Edit” the Edit window will appear:


In the “Value (Expr)” field insert your value and click “change”, the value will appear in it’s field. Click “ok” when finished.


6. Plot interest: if you need to plot and/or to save any net

in your schematic, you need to choose : “Outputs” -> “To Be Plotted” -> “Select on Schematic”:


Now you can choose any net you want to be plotted at yours design, it’ll look like this:

You can save the net thru “outputs”-> “setup” and choose the save button of every net you want to save


Anyway you can decide to save all the nets in any hierarchy. To do so, in Analog Environment go to “Outputs”-> “Save All…”:

The save menu will pop up:


Hear you can decide to save all nets in some levels (hierarchies), like the nets, and the currents. In this case we save: all nets in 3 upper levels and all currents in 2 upper levels. When you complete to configure it press “ok”.


7. Solver definition: In Analog Environment choose

“Simulation” -> “Solver”:

The “Solver” window will pop up:


Choose your solver to be “UltraSim” and click “ok”.


8. Run Options: First of all you can see that in the window

of Analog Environment the simulator indication now says ams(UltraSim). Now you choose “Simulation”-> “Run Options…”:

The pop up of “Run Options” window will appear now:


Select “All” against “Compile” & “Elaborate” “Incremental” to compile and elaborate all your design every time you doing netlist, check that you in the “Batch” mode and click “ok”. Also in “CIW” go to “tools”-> “AMS”-> “Options…”:


The Options menu will appear:

In “Check and Save” category – mark :”AMS check, netlist and Compile AMS netlist. Click “Apply” when finished.


Now in the same menu go to “Compiler” and provide path to “hdl.var” you using. For edit “hdl.var” press the “Edit…” button, press “ok” when finished.


9. The advantage of AMS that it provides you opportunity to run analog and digital parts in different precision. More precisely you can run every part of your design with different accuracy and speed. That's how you do it:a. First of all you decide, how precise will the simulator

calculate, for all your design. To configure it go in “Analog Environment” to “Simulation”-> "Options”-> “FastSPICE(UltraSim)…”


The menu of “UltraSim options” will appear:


In “Simulation mode” field open the menu:


Hear you can decide the accuracy of calculation for all design together:

•Digital Fast (DF) – the fastest but least accurate.• Spice (S) – most accurate but the slowest.•The rest, like another 4 stages of accuracy and speed, that you can decide which one will be the best for your design. {In our design I have chosen “MS”, it is the accuracy I want for my analog part of the design.{


b. Second is to configure every part or cell separately, to do so, go to “Hierarchy Editor”-> “View” and

choose “Properties”:

This will open in H.E. additional properties. The property you need to see it’s “sim_mode” , it’s can be empty or like here contain some value.


Click the right button on the “sim_mode” against the needed cell (one of the top_level cells):

Go to “Set “sim_mode”cell Property”.Now you can choose a needed “sim_mode”:The empty field is a“sim_mode” that wechoose in “a” for all thedesign and the rest isthe sim_modes we wantto provide locally. (in ourcase we choose (df) fora digital part of the design).


After that we will see “df” against “controller” in blue and it’s necessary to do the update to Hierarchy Editor

So press the updatebutton that now appears with exclamation mark .


The update menu will pop up. Select your design and press “ok”.

After it'll finish theUpdate, all sub cells of that specific cell (controller in our case)will become “df” also,but will be written in black, so you could separate which is the top hierarchy from all.You can see how itlooks in the next slide.


Now the cell “controller” will run in “digital fast” mode. The same you can do with any cell you choose!


10. Netlister: to set the global signalsglobal signals first you should create a net list of

your design. To do so go in Analog Environment to “simulation”-> “Options”-> “Netlist”->”Recreate”:

If in CIW you’ll see that the process finished unsuccessful you should “check&save” the Schematic and update the Hierarchy Editor, than try to create the “Netlist” again (it’s very important to remember which part of your design was changed from last “check&save” so you could find it quicker).


After the Netlist created the CIW should look like this:

Only now you can proceed and edit Global Signals of your design.


Now you can set the global signals.global signals. Go in Analog Environment to “Options”-> “Netlister…”:

The “Netlister Options” window will pop up:


Push the “Global Signals…” button. The Global Signals menu will appear:


The signals that’s appears hear should be only global power or ground. If it’s a ground signal choose it and select ground button, then click “Change”.


Now all ground signals appears with “Yes” in “Ground” field.

If you have global nets with same value, you can alias those nets, to do so click, holding “Ctrl”, on both signals with left button of the mouse, “Alias” menu will become available, so just click it. In the left side of aliased nets will appear “/-- & \--”. In the same way you can Unalias the nets. When you finish click “ok”.


11.Save the state:It is recommended to save the state you prepared till here to prevent doing it every time you need to run this simulation! To do so, go in Analog Environment to “Session”-> “Save State…”

The save menu will appear:


Insert the name for this state, also you can provide a description to remember better the differences between the states. Click “ok” when finished.


V. Run the Simulation:1. To run the simulation go to “Simulation”-> “Netlist

and Run”, or press on the green traffic light. If the netlist already was provided and no changes were made you can just run the simulation without Netlisting by clicking on “Run”, or yellow traffic light:


2. Following the simulation run: you can follow the run by several ways:

a. log window that pops up.b. CIW that gives you the completed stages.

If every thing runs ok that's how should it look:3.

Knownfailures incompilation stage


4.

Knownfailures inelaboration stage


5.

Knownfailures insimulation stage


6.


7. When the simulation is complete the plot window will pop up, showing you the graphs that hade been plotted from the lines you have chosen. It looks something like this:


Compilation FailuresCompilation Failures1.


Elaboration FailuresElaboration Failuresa. Ncelab: *E, CUCFUN: instance’ ‘ of the unit ‘ ’ is unresolved in ‘ ’

2.

The solution to this failure:The solution to this failure:Probably one or several files disabled or don’t exist in your model library. You can enable or insert it like it described on page 22


Simulation FailuresSimulation Failuresa. Ncsim: *E, RNALER: simulation terminated due to analog error.

3.

The solution to this failure:The solution to this failure:That failure is probably happens because exaggerated use of resources (CPU, Memory). The solution is to try to shutter the resource usage. My recommendation is to save less levels of outputs, that was described in page 32. Or try to lower the accuracy level like on pages

40 – 48 .


The The End End


II. Start building the Testa. Create “schematic view”b. Create “Config view”c. Configuration of “Hierarchy Editor”

Back to Topics


IV. Start building the Test1. Choose the simulator2. Choose “Connect rules”3. Definition of the simulation models4. The Analyses definition5. Variables Definition6. Plot interest7. Solver definition8. Run Options9. Simulation accuracy definition 10. Netlister11. Save the state Back to Topics


9. Simulation accuracy definitiona. Accuracy Definition For All The Designb. Accuracy Definition For Every Cell

Back to Topics


VI. Failures & Solutions:1. Compilation Failures

a. D

2. Elaboration Failuresa. D

3. Simulation Failuresa. Ncsim: *E, RNALER: simulation terminated due to analog error.

Back to Topics

Documents

The VLSI Systems Center - BGU AMS – Test Manual by Slava Fleshel 309284222