The Verilog Language

8/10/2019 The Verilog Language

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The Verilog Language

Originally a modeling language for a very efficientevent-driven digital logic simulatorLater pushed into use as a specification language

for logic synthesisNow, one of the two most commonly-usedlanguages in digital hardware design (VHDL is theother)

Virtually every chip (FPGA, ASIC, etc.) isdesigned in part using one of these two languages

Combines structural and behavioral modeling

styles


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How Verilog Is Used

Virtually every ASIC is designed using eitherVerilog or VHDL (a similar language)Behavioral modeling with some structuralelementsSynthesis subset

Can be translated using Synopsys Design Compileror others into a netlist

Design written in VerilogSimulated to death to check functionalitySynthesized (netlist generated)Static timing analysis to check timing


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Structural Modeling

When Verilog was first developed (1984) mostlogic simulators operated on netlistsNetlist : list of gates and how theyre connected

A natural representation of a digital logic circuitNot the most convenient way to express testbenches


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Comparison

Structural: Logic isdescribed in terms ofVerilog gate primitivesExample:not n1(sel_n, sel);and a1(sel_b, b,sel_b);and a2(sel_a, a, sel);or o1(out, sel_b,sel_a);

Dataflow: Specify

output signals interms of inputsignals

Example:assign out = (sel &a) | (~sel & b);

STRUCTURAL DATAFLOW


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sel

b

aout

sel_n

sel_b

sel_a

n1a1

a2

o1

sel

b

a

outsel_n

sel_b

sel_a

Structural modelling Dataflow modelling


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Behavioral contd..

Behavioral: Algorithmically specify the behavior ofthe design

Example:if (select == 0) begin

out = b;end

else if (select == 1) beginout = a;end

a

b

sel

outBlack Box 2x1 MUX


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Dataflow modelling

Uses continuous assignment statementFormat: assign [ delay ] net = expression;Example: assign sum = a ^ b;

Delay: Time duration between assignmentfrom RHS to LHS

All continuous assignment statements executeconcurrently

Order of the statement does not impact thedesign


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Data flow modelling contd..

Example:

`timescale 1ns/100ps

module HalfAdder (A, B, Sum, Carry);input A, B; output Sum, Carry;assign #3 Sum = A B;assign #6 Carry = A & B;

endmodule


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Contd..

Delay can be introducedExample: assign #2 sum = a ^ b; #2 indicates 2 time -unitsNo delay specified : 0 (default)

Associate time-unit with physical time`timescale time-unit/time-precisionExample: `timescale 1ns/100 ps

Timescale

`timescale 1ns/100ps1 Time unit = 1 nsTime precision is 100ps (0.1 ns)10.512ns is interpreted as 10.5ns


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Two Main Components ofVerilog

Concurrent, event-triggered processes(behavioral)

Initial and Always blocksImperative code that can perform standard data

manipulation tasks (assignment, if-then, case)Processes run until they delay for a period of time orwait for a triggering event

Structure (Plumbing)Verilog program build from modules with I/OinterfacesModules may contain instances of other modulesModules contain local signals, etc.

Module configuration is static and all run concurrently


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Data types

Net Types: Physical Connection betweenstructural elements

Register Type: Represents an abstract storage

element.Default Values

Net Types : zRegister Type : x

Net Types: wire, tri, wor, trior, wand, triand,supply0, supply1

Register Types : reg, integer, time, real, realtime


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Two Main Data Types

Nets represent connections between thingsDo not hold their valueTake their value from a driver such as a gate or othermodule

Cannot be assigned in an initial or always block

Regs represent data storageBehave exactly like memory in a computerHold their value until explicitly assigned in an initial oralways blockNever connected to somethingCan be used to model latches, flip-flops, etc., but do notcorrespond exactlyShared variables with all their attendant problems


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Data types contd..

Net Type: Wirewire [ msb : lsb ] wire1, wire2,

Example

wire Reset; // A 1-bit wirewire [6:0] Clear; // A 7-bit wire

Register Type: Regreg [ msb : lsb ] reg1, reg2,

Example reg [ 3: 0 ] cla; // A 4-bit registerreg cla; // A 1-bit register


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Restricted data types

Data Flow and Structural ModelingCan use only wire data typeCannot use reg data type

Behavioral ModelingCan use only reg data type (within initial andalways constructs)Cannot use wire data type


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Memories

An array of registers

reg [ msb : lsb ] memory1 [ upper : lower ] ;

Examplereg [ 0 : 3 ] mem [ 0 : 63 ];// An array of 64 4-bit registers

reg mem [ 0 : 4 ];// An array of 5 1-bit registers


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Compiler directives

`define (Similar to #define in C) used to defineglobal parameter

Example:`define BUS_WIDTH 16

reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;`undef Removes the previously defined directive

Example:`define BUS_WIDTH 16

reg [ `BUS_WIDTH - 1 : 0 ] System_Bus;

`undef BUS_WIDTH


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Four-valued Data

Verilogs nets and registers hold four -valued data

0, 1Obvious

ZOutput of an undriven tri-state driverModels case where nothing is setting a wires value

X

Models when the simulator cant decide the value Initial state of registersWhen a wire is being driven to 0 and 1 simultaneouslyOutput of a gate with Z inputs


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Operators

Arithmetic(Unary )RelationalBitwiseLogicalEquality


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STRUCTURALMODELING


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Nets and Registers

Wires and registers can be bits, vectors, andarrays

wire a; // Simple wiretri [15:0] dbus; // 16-bit tristate bus tri #(5,4,8) b; // Wire with delay reg [-1:4] vec; // Six-bit register trireg (small) q; // Wire stores a small

charge integer imem[0:1023]; // Array of 1024 integers reg [31:0] dcache[0:63]; // A 32-bit memory


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Modules and Instances

Basic structure of a Verilog module:

module mymod(output1, output2, input1, input2);

output output1;output [3:0] output2;input input1;input [2:0] input2; endmodule

Verilog convention listsoutputs first


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Instantiating a Module

Instances of

module mymod(y, a, b);

look like

mymod mm1(y1, a1, b1); // Connect-by-position

mymod (y2, a1, b1),(y3, a2, b2); // Instance names

omitted mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-by-name


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Gate-level Primitives

Verilog provides the following:

and nand logical AND/NAND or nor logical OR/NORxor xnor logical XOR/XNORbuf not buffer/inverter bufif0 notif0 Tristate with low enablebifif1 notif1 Tristate with high enable


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Delays on Primitive Instances

Instances of primitives may include delays

buf b1(a, b); // Zero delaybuf #3 b2(c, d); // Delay of 3buf #(4,5) b3(e, f); // Rise=4, fall=5buf #(3:4:5) b4(g, h); // Min-typ-max


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User-Defined Primitives

Way to define gates and sequential elementsusing a truth tableOften simulate faster than using expressions,collections of primitive gates, etc.Gives more control over behavior with X inputsMost often used for specifying custom gate

libraries


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An UDP can contain only one output and up to 10inputs.Output port should be the first port followed byone or more input ports.

All UDP ports are scalar, i.e. Vector ports are notallowed.UDPs can not have bidirectional ports.The output terminal of a sequential UDP requires

an additional declaration as type reg.It is illegal to declare a reg for the output terminalof a combinational UDP


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A Carry Primitive

primitive carry(out, a, b, c);output out;input a, b, c;table

00? : 0;0?0 : 0;?00 : 0;11? : 1;1?1 : 1;

?11 : 1;endtableendprimitive

Always have exactly oneoutput

Truth table may includedont-care (?) entries


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A Sequential Primitive

Primitive dff( q, clk, data);output q; reg q;input clk, data;table// clk data q new-q

(01) 0 : ? : 0; // Latch a 0(01) 1 : ? : 1; // Latch a 1 (0x) 1 : 1 : 1; // Hold when d and q both 1 (0x) 0 : 0 : 0; // Hold when d and q both 0 (?0) ? : ? : -; // Hold when clk falls

? (??) : ? : -; // Hold when clk stable endtableendprimitive


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Continuous Assignment

Another way to describe combinational functionConvenient for logical or datapath specifications

wire [8:0] sum;wire [7:0] a, b;wire carryin;

assign sum = a + b + carryin;

Define bus widths

Continuous assignment:permanently sets thevalue of sum to bea+b+carryinRecomputed when a, b, orcarryin changes


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tb

`include "udp_body.v" module udp_body_tb(); reg b,c;

wire a;udp_body udp (a,b,c); initial begin$monitor(" B = %b C = %b A = %b",b,c,a); b = 0; c = 0;#1 b = 1;


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#1 b = 0; #1 c = 1; #1 b = 1'bx;

#1 c = 0; #1 b = 1; #1 c = 1'bx;

#1 b = 0;#1 $finish;endmodule


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output

B = 0 C = 0 A = 0 B = 1 C = 0 A = 1B = 0 C = 0 A = 0

B = 0 C = 1 A = 1B = x C = 1 A = 1 B = x C = 0 A = x

B = 1 C = 0 A = 1 B = 1 C = x A = 1B = 0 C = x A = x


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Initial statement is used for initialization ofsequential UDPs. This statement begins withthe keyword 'initial'. The statement that follows

must be an assignment statement that assignsa single bit literal value to the output terminalreg


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primitive udp_initial (a,b,c); output a; input b,c; reg a; // a has value of 1 at start of sim initial a = 1'b1; table

// udp_initial behaviourEndtable endprimitive


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symbols interpretation logic

? 0,1,X ? Means the variablecan be 0 or 1 or X

b 0,1 Same as ?, but X is not

includedf (10) Falling edge on an input

r (01) Rising egde on an input

p (01) or( 0X) or (X1) or(1z) or (z1)

Rising edge including Xand Z

n (10) Or(1x) or(x0) or(0z)or (z0)

Falling edge including xand Z

* (??) All transitions

- No change No change


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Level sensitive sequential

primitive udp_latch(q, clk, d) ; output q;

input clk, d;reg q;

table //clk d q q+0 1 : ? : 1 ;0 0 : ? : 0 ;

1 ? : ? : - ;endtableendprimitive


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Edge sensitive UDPs

In level-sensitive behavior, the values of the inputsand the current state are sufficient to determinethe output value.

Edge-sensitive behavior differs in that changes inthe output are triggered by specific transitions ofthe inputs.

All transitions that should not affect the output

must be explicitly specified. Otherwise, they willcause the value of the output to change to x. If theUDP is sensitive to edges of any input, thedesired output state must be specified for alledges of all inputs


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edge

primitive udp_sequential(q, clk, d); output q; input clk, d; reg q;

table // obtain output on rising edge of clk // clk d q q+ (01) 0 : ? : 0 ; (01) 1 : ? : 1 ; (0?) 1 : 1 : 1 ; (0?) 0 : 0 : 0 ;


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// ignore negative edge of clk (?0) ? : ? : - ; // ignore d changes on steady clk ? (??) : ? : - ; endtable endprimitive


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With initial block

primitive udp_sequential_initial(q, clk, d); output q;input clk, d; reg q;initial begin q = 0; endtable


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BEHAVIORALMODELING


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Initial and Always Blocks

Basic components for behavioral modelinginitial

begin imperative statements

end

Runs when simulation startsTerminates when control reachesthe endGood for providing stimulus

alwaysbegin

imperative statements end

Runs when simulation startsRestarts when control reaches theendGood for modeling/specifyinghardware


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Initial and Always

Run until they encounter a delay

initial begin#10 a = 1; b = 0;

#10 a = 0; b = 1;end

or a wait for an event

always @(posedge clk) q = d;always begin wait(i); a = 0; wait(~i); a = 1; end


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Procedural Assignment

Inside an initial or always block:

sum = a + b + cin;

Just like in C: RHS evaluated and assigned toLHS before next statement executes

RHS may contain wires and regsTwo possible sources for data

LHS must be a reg cont. assignment may set wire values


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Contd..

If a procedure block contains more than onestatement, those statements must be enclosedwithin

Sequential begin - end blockParallel fork - join block

When using begin-end, we can give name tothat group. This is called named blocks.


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Two Procedural Constructs

initial Statementalways Statement

initial Statement : Executes only oncealways Statement : Executes in a loopExample:

initial begin

Sum = 0;Carry = 0;

end

always @(A or B) beginSum = A ^ B;Carry = A & B;

end


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module initial_fork_join();reg clk,reset,enable,data;initial begin$monitor("%g clk=%b reset=%b enable=%b data=%b",$time, clk, reset, enable, data);

fork#1 clk = 0;#10 reset = 0;#5 enable = 0;#3 data = 0;

join#1 $display ("%g Terminating simulation", $time);$finish;end


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Imperative Statements

if (select == 1) y = a;else y = b;

case (op)2b00: y = a + b; 2b01: y = a b;2b10: y = a ^ b; default: y = hxxxx;

endcase


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Delay

Inter-Assignment DelayExample:Sum = A ^ B;#2 Carry = A & B;

Delayed execution

Intra-Assignment DelayExample:

Sum = A ^ B;Carry = #2 A & B;Delayed assignment

Edge sensitive Event Controls


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Edge sensitive Event Controls

Delays execution of the next statement until the specifiedtransition on a signal.syntax : @ (< posedge >|< negedge > signal) < statement >;

module edge_wait_example();reg enable, clk, trigger;always @ (posedge enable)begintrigger = 0;// Wait for 5 clock cyclesrepeat (5) begin

@ (posedge clk) ;endtrigger = 1;

end

Level Sensitive Even Controls (


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Level-Sensitive Even Controls (Wait statements )

Delays execution of the next statement until evaluates to truesyntax : wait (< expression >) < statement >;

Eg:wait (data_ready == 1) #1 data = data_bus;


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Discrete-event Simulation

Basic idea: only do work when somethingchangesCentered around an event queue

Contains events labeled with the simulated time atwhich they are to be executed

Basic simulation paradigmExecute every event for the current simulated time

Doing this changes system state and may scheduleevents in the futureWhen there are no events left at the current timeinstance, advance simulated time soonest event in the

queue


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Event

Event ControlEdge Triggered Event ControlLevel Triggered Event Control

Edge Triggered Event Control@ (posedge CLK) //Positive Edge of CLK

Curr_State = Next_state;

Level Triggered Event Control@ (A or B) //change in values of A or B

Out = A & B;


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For Loops

A increasing sequence of values on an output

reg [3:0] i, output;

for ( i = 0 ; i


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While Loops

A increasing sequence of values on an output

reg [3:0] i, output;

i = 0;while (I


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Modeling A Flip-Flop With Always

Very basic: an edge-sensitive flip-flop

reg q;

always @(posedge clk)q = d;

q = d assignment runs when clock rises:exactly the behavior you expect


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Blocking vs. Nonblocking

Verilog has two types of proceduralassignment

Fundamental problem:In a synchronous system, all flip-flops samplesimultaneouslyIn Verilog, always @(posedge clk) blocks run insome undefined sequence


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A Flawed Shift Register

This doesnt work as youd expect:

reg d1, d2, d3, d4;

always @(posedge clk) d2 = d1;always @(posedge clk) d3 = d2;always @(posedge clk) d4 = d3;

These run in some order, but you dont knowwhich


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Non-blocking Assignments

This version does work:

reg d1, d2, d3, d4;

always @(posedge clk) d2


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Nonblocking Can Behave Oddly

A sequence of nonblocking assignments dontcommunicatea = 1;

b = a;c = b;

Blocking assignment:a = b = c = 1

a


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Conditional statements

if StatementFormat:if (condition)

procedural_statementelse if (condition)

procedural_statementelse

procedural_statementExample:

if (Clk)Q = 0;

elseQ = D;


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Contd..

Case StatementExample 1:

case (X)2b00: Y = A + B; 2b01: Y = A B;

2b10: Y = A / B; endcase

Example 2: case (3b101


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Contd..

Variants of case Statements: casex and casez

casez z is considered as a dont care

casex both x and z are considered as dontcares

Example:casez (X)

2b1z: A = B + C; 2b11: A = B / C;

endcase


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VERILOG AND LOGICSYNTHESIS

h


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Logic Synthesis

Verilog is used in two waysModel for discrete-event simulationSpecification for a logic synthesis system

Logic synthesis converts a subset of the Veriloglanguage into an efficient netlistOne of the major breakthroughs in designing logicchips in the last 20 yearsMost chips are designed using at least some logicsynthesis

h


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Logic Synthesis

Takes place in two stages:

Translation of Verilog (or VHDL) source to a netlistRegister inference

Optimization of the resulting netlist to improvespeed and area

Most critical part of the process Algorithms very complicated and beyond the scope ofthis class: Take Prof. Nowicks class for details

l i il i G


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Translating Verilog into Gates

Parts of the language easy to translateStructural descriptions with primitives

Already a netlist

Continuous assignmentExpressions turn into little datapaths

Behavioral statements the bigger challenge

Wh C B T l d


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What Can Be Translated

Structural definitionsEverything

Behavioral blocksDepends on sensitivity list

Only when they have reasonable interpretation ascombinational logic, edge, or level-sensitive latchesBlocks sensitive to both edges of the clock, changes onunrelated signals, changing sensitivity lists, etc. cannot besynthesized

User-defined primitivesPrimitives defined with truth tablesSome sequential UDPs cant be translated (not latches orflip-flops)

Wh I T l d


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What Isnt Translated

Initial blocksUsed to set up initial state or describe finite testbenchstimuliDont have obvious hardware component

DelaysMay be in the Verilog source, but are simply ignored

A variety of other obscure language featuresIn general, things heavily dependent on discrete-eventsimulation semantics

Certain disable statements Pure events

R i I f


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Register Inference

The main trick

reg does not always equal latch

Rule: Combinational if outputs always dependexclusively on sensitivity list

Sequential if outputs may also depend onprevious values

R i I f


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Register Inference

Combinational:

reg y;always @(a or b or sel)

if (sel) y = a;else y = b;

Sequential:

reg q;always @(d or clk)if (clk) q = d;

Sensitive to changes onall of the variables it reads

Y is always assigned

q only assigned when clkis 1


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R i t I f


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Register Inference

The solution is to always have a default case

always @(a or b)

case ({a, b})2b00: f = 0; 2b01: f = 1; 2b10: f = 1;

default: f = 0;endcase

f is always assigned


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Simulation-synthesis


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yMismatches

Many possible sources of conflict

Synthesis ignores delays (e.g., #10), butsimulation behavior can be affected by themSimulator models X explicitly, synthesis doesnt Behaviors resulting from shared-variable-likebehavior of regs is not synthesized

always @(posedge clk) a = 1;New value of a may be seen by other @(posedge clk)statements in simulation, never in synthesis

C d t VHDL


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Compared to VHDL

Verilog and VHDL are comparable languagesVHDL has a slightly wider scope

System-level modelingExposes even more discrete-event machinery

VHDL is better-behavedFewer sources of nondeterminism (e.g., no sharedvariables)

VHDL is harder to simulate quickly

VHDL has fewer built-in facilities for hardwaremodelingVHDL is a much more verbose language

Most examples dont fit on slides

Documents

The Verilog Language