The VeloPix ASIC - CERNcds.cern.ch/record/2228222/files/LHCb-TALK-2016-342.pdfThe VeloPix ASIC 30.9.2016 Tuomas Poikela & VeloPix design and testing team TWEPP 2016, Karlsruhe, Germany

The VeloPix ASIC

30.9.2016Tuomas Poikela

& VeloPix design and testing teamTWEPP 2016, Karlsruhe, Germany

30.9.2016 VeloPix TWEPP 2016 2

Overview● A quick VELO upgrade overview● Chip architecture● First measurements● Summary & future plans


The LHCb VELO upgrade

Artist's i

mpression of

new VELO

624VeloPixASICs

TWEPP 2016 : Sneha Naik “On-detector electronics for the LHCb VELO Upgrade”


VeloPix ASIC moduleData rates per ASIC (Gbps)

The hottest chips 5.1 mm from the beam

Data per chip: ~15.1 Gbps, 2.9 Tbps for VELO

The module installation during the CERNLong Shutdown 2 (LS2) 2019/2020.

Highly non-uniform radiationwithin the hottest chip: From 50 to 400 Mrad.

Hybrid pixel readout chip:Bonded to a sensor.


Quick comparisonFeature VeloPix (2016) Timepix3 (2013)

Readout type Continuous, trigger-less, binary

Continuous, trigger-less, ToT

Timing resolution/range 25 ns, 9 bits 1.5625 ns, 18 bits

Power consumption < 1.5 W cm-2 < 1.0 W cm-2

Pixel matrix, pixel size 256 x 256, 55 um x 55 um

256 x 256, 55 um x 55 um

Radiation hardness 400 Mrad, SEU tolerant -

Peak hit rate 800 Mhits/s/ASIC50 khits/s/pixel

80 Mhits/s/ASIC

Sensor type Planar silicon, e- collection Various, e- and h+ collection

Max. data rate 20.48 Gbps 5.12 Gbps

Technology 130 nm CMOS, tech A 130 nm CMOS, tech B


Project overview● Design started in June 2013 (after

Timepix3 submission)● Change of technology (130nm → 130nm)

● The chip was submitted May 26th 2016, wafers received on 31st August

● Fabricated (and diced) chips back at CERN on 7th September

● Production testing later this year (624 chips)

● Irradiation campaign in the future with sensors bonded

VeloPix wafers


Chip architecture128 double columns (14.08 mm)

256

row

s (1

4.08

mm

)

SP63SP63

SP62SP62

SP61SP61

SP0SP0

SP1SP1

SP2SP2

SP63SP63

SP62SP62

SP61SP61

SP0SP0

SP1SP1

SP2SP2

SP63SP63

SP1SP1

SP2SP2

SP63SP63

SP62SP62

SP61SP61

SP0SP0

SP1SP1

SP2SP2

PixelHitProcessorPixelHit

Processor

SP0SP0

SP63SP63

SP62SP62

SP61SP61

EoCEoC EoCEoC EoCEoC EoCEoC EoCEoC

routerrouterDACsDACs PLLPLL

SLOW CONTROLSLOW CONTROL TIMING, FAST CTRLTIMING, FAST CTRL

2.3

mm

Super pi xel

GW

TG

WT

GW

TG

WT

The pixel matrix:256 x 256 pixels128 x 64 super pixels (2x4 pixels each)

Architecture:Packet-based, 8 pixels/packet + 9 bit time stamp

Leads to 30% reduction in data rate

Data-driven, 20Mpackets/s / double column- Timepix3 rate: 1.2 Mpackets/s

SP61SP61

SP62SP62

10-b

it To

A @

40

MH

z

SP0SP0


Front-end architecture

Global Threshold Vthr

Front-end (Analog)LeakageCurrentcompensation

Preamp

Inputpad

1 pixel

V1 V2

Counters &

Latches

4-bit LocalThreshold

Front-end (Digital)

Synch.&

Clock gating

ToTProcessor

6-bitLFSR

Clock(40/80 MHz)

Super pixel (Digital)

Common for 8 pixels

Data nodeData node

To the next node

Validevent

FIFO

BX ID

CL

OC

Km

anag

erC

LO

CK

man

ager

4 fFMaskbit

Shutter

10 b

its

6

Test bit

Injected charge:Qin=Ctest (V2 - V1)

Test pulse

Synchro noushandsha ke

Ctest

5 fF

8

Testpulse


Double column datapath

FIFO Node

NodeFIFO

FIFO Node

NodeFIFO

64 FIFOs0 1

RegisterRegister

Arbiter

Arbiter

PreviousNode

FIFOData

Size = 2packets Up to 20

Mpackets/s

NextNode

8 digitalFront-ends8 digitalFront-ends

8 analogFront-ends8 analogFront-endsSe

nsor

Super pixelcolumn

Analog pixelcolumn

Digital pixelcolumn

Super pixel packet:

hitmap 8bAddr 6b ToA 10b

Timestamping @ 40 MHz

30.9.2016 VeloPix TWEPP 2016 10

Periphery datapath

64 EoCs 64 EoCs

LeftData Fabric

RightData Fabric

Cen

ter

Nod

e

Pixel Matrix

FIFO

19.20 Gbps19.20 Gbps

Data Node

Router/Scramblers/Framing

4.8 Gbps per bus

4x 5.12 GbpsGWT link Data

out160 Mpackets/s/node

64x up to 20 Mpackets/s 64x up to 20 Mpackets/s

30.9.2016 VeloPix TWEPP 2016 11

TMR/RadHard design● Manual triplication

(except configuration registers)

● Pixel data flip-flops (FF) unprotected

● Full TMR in FSM & configuration FFs, pixel config latches

● No on-chip SRAM!● NMOS ELT transistors

used in analog front-end

● Std cell library characterized at 400 Mrad, High-Vt NMOS

● Corner used for syn/PnR: slow process, VDD 1.08V, 400 Mrad, 25°C

30.9.2016 VeloPix TWEPP 2016 12

First debugging results

SPIDR-readout system developed at Nikhef

VeloPix

TWEPP 2016: Bas Van Der HeijdenSPIDR, a General-Purpose Readout System for Pixel ASICs

30.9.2016 VeloPix TWEPP 2016 13

First signs of life

VeloPix responding to the first slow control command

30.9.2016 VeloPix TWEPP 2016 14

Tests performed so far

PLL locked, running at 320 MHz

Slow control responds, register R/Waccess works

The pixel matrix resettable, readableand writable

Analog & Digital front-ends respond to test pulses correctly

Shutter/test pulse logic works.

Packet latency (low rate) corresponds toexpected

Timing and fast control working

30.9.2016 VeloPix TWEPP 2016 15

First measurements

● Power:➢ Analog➢ Digital (IDLE), matrix

clocking, time stamp bus● DAC (work as expected)● GWT eye diagram

● S-curves using analog test pulse

● Noise● Threshold variation● Super pixel packet

latency

30.9.2016 VeloPix TWEPP 2016 16

Power consumption (1.2V)● Analog: 387 mA, 476 mW● Digital:

1. After chip power up: 374 mW2. Matrix clock enabled: 694 mW3. ToA counter enabled: 718 mW

Clock: +320 mW

ToA bus power +24 mW

AnalogDigital Pe-ripheryDigital Matrix

Total: 1.2 W (0.52 W/cm2)(Meets < 1.5 W/cm2)

TODO: Measurement with high rate

30.9.2016 VeloPix TWEPP 2016 17

GWT Eye diagram @ 5.12GbpsFirst test runs of VeloPix GWT.2 links running at the same time.

Very first measurements!BER/jitter to be verified.

30.9.2016 VeloPix TWEPP 2016 18

Measurements with test pulse

Global Threshold Vthr

Front-end (Analog)LeakageCurrentcompensation

Preamp

Inputpad

V1 V2

4-bit DAC

Synch.&

Clock gating

4 fFMaskbit

Test bit

Injected charge:Qin=Ctest (V2 - V1)

Ctest 5 fFTestpulse

Test pulse

Ton

Test pulse

#pulses

ToffCounten

Pixel 255

Pixel 254

Pixel 1

Pixel 0

Pixel 255

Pixel 254

Pixel 1

Pixel 0

TP Generator

mask#pulsesT

on

Tof

Tphase

Slowcontrol

30.9.2016 VeloPix TWEPP 2016 19

Digital: ToT mode

Test pulse

Ton

Ton

= 4 + Pixel X % 32

30.9.2016 VeloPix TWEPP 2016 20

Analog test pulses in one pixel0.0154 ke-/DAC

LSB => 1 DAC

LSB = 0.38 mV => 24.6 mV/ke-

14-bit DAC Code

25 test pulses

Ene

rgy

(ke-

)14-bit DAC Code

30.9.2016 VeloPix TWEPP 2016 21

Test pulses in 32 pixelsD

AC

Cod

e

Energy (ke-)

30.9.2016 VeloPix TWEPP 2016 22

Electronic noise (preliminary)

30.9.2016 VeloPix TWEPP 2016 23

Threshold equalization (preliminary)

DAC Code

Cou

nts

30.9.2016 VeloPix TWEPP 2016 24

Summary of pixel measurements

Digital pixel front-end fully functional.Responds correctly in ToT and Photon counting modes.All measurements without sensor.

30.9.2016 VeloPix TWEPP 2016 25

Super pixel packet latency (low rate)

Super pixels onTop of the column haveHigher latency.

0 10 20 30 40 50 60 70 800

0.2

0.4

0.6

0.8

1

1.2

Latency greater than (# clock cycles @ 40 MHz)

% o

f all

pack

ets (

x 10

0%)

Counter

SP

BX ID

T0

T1

Latency: T1 - T0

10

All packets have latency > 0

All packets haveLatency < 70

Matches simulations. Indicates time stampingworking as expected.

30.9.2016 VeloPix TWEPP 2016 26

Summary● VeloPix ASIC, designed in 130nm CMOS, presented● First silicon for debugging 7th September ● First results show the chip is alive and eyes open:

➢ Power 1.2 W/ASIC, DACs working, pixels functional➢ Pixel: Gain ~25 mV/ke-, ENC 63 e-, no systematics➢ GWT serializer working, time stamping works

● Debugging and fine-tuning will continue in the following weeks:➢ Full DAQ chain tests, GWT BER and jitter➢ PLL characterization

● Production testing later this year at CERN

30.9.2016 VeloPix TWEPP 2016 27

Thank you!● List of contributors:

➢ ASIC designers: Jan David Schipper, Vladimir Gromov, Sandeep Miryala, Xavi Llopart, Rafael Ballabriga, Winnie Wong, Tuomas Poikela

➢ Support, readout and testing: Jerome Alozy, Martin van Beuzekom, Henk Boterenbrood, Bas van der Heijden, Jan Buytaert, Marco Daldoss, Edgar Lemos Cid,

➢ IP Blocks: Stefano Michelis, Pedro Miguel Vicente Leitao, Rui De Oliveira

+ many others I forgot to mention...

30.9.2016 VeloPix TWEPP 2016 28

Spares

30.9.2016 VeloPix TWEPP 2016 29

Power routing and bump padsDigital

Bumppads

Powerrails

Analog

Supe

r pi

xel =

2 x

4 p

ixel

s

Documents

The VeloPix ASIC - CERNcds.cern.ch/record/2228222/files/LHCb-TALK-2016-342.pdfThe VeloPix ASIC 30.9.2016 Tuomas Poikela & VeloPix design and testing team TWEPP 2016, Karlsruhe, Germany