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The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
State Machines
Anselmo Lastra
2 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Topics
• How to design machines that go through a sequence of events
• Basically close this loop
3 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Lab Preview
• Digital lock• You’ll need clock• Will provide code for slowing
clock♦ Next slide♦ There are better ways to change clock
speed. Will discuss later.
4 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Counter
module cntr(output out, input clk);
reg [31:0] count;
always @ (posedge clk) count <= count + 1;
assign out = count[22];
endmodule
What does this do?
5 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Button and Debouncing
• Button normally high• Mechanical switches can
“bounce”♦ Go H and L a number of times
• We’ll want to♦ debounce♦ synchronize
6 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Flip-Flop for pushbutton
module button_test( output q, input btn, input clk );
reg q;
always @ (posedge clk)begin
if(btn == 1)q <= 1;
elseq <= 0;
end
endmodule
What is this?
7 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Simple Module to Begin With
module led_on(output s6, input button, input clk);
wire clkb; //opt
cntr C1(clkb, clk);button_test B1(s6, ~button, clkb);
endmodule
• clk to board clock, P88• button to pushbutton, P93
• Why ~button?• s6 to one of LED segments
8 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Things to Think About
• Can I press button and not light LED?• What happens if I hold button down
for a long time?• What effect will changing period of
clkb have?♦ On LED♦ On button debouncing
• What does it mean to “press the button”?♦ Think carefully about this
9 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Analysis of Sequential Circuits
• Earlier we learned how to analyze combinational circuits
• Now extend to synchronous sequential♦ Include time
• We’ll use state tables and state diagrams
10 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Input Equations
• Can describe inputs to FF with logic equations
)( BXAXDA
XADB
XBAY )(
11 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Time is Implied
• Note that last circuit used the♦ Previous state to determine next state♦ State and inputs to determine outputs
• Synchronous circuit• When are transitions?
• So timing is discrete
12 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
State Table
• Just truth table with state added
)( BXAXDA XADB XBAY )(
13 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Another Table
• Same info, different layout style
14 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Sequential Circuit Types
• Moore model – outputs depend on states
• Mealy model – outputs also depend on inputs
15 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
State Diagram
• Alternative representation for state table
• Moore-> State/OutputInputs
16 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Mealy Model
• Output depends on input and state Input/Output
17 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
State Table vs. Diagram
• Same information• Table is perhaps easier to fill in
from description• Diagram is perhaps easier to
understand♦ You can label states with English
description
18 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Design Procedure
• Take problem description and refine it into a state table or diagram
• Assign codes to the states• Write Verilog♦ See example in a moment♦ Designing with gates and FFs more
involved because you have to derive input and output functions
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Good Place to go off on a Tangent
20 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Example – Sequence Recognizer
• Circuit has input, X, and output, Z
• Recognizes sequence 1101 on X♦ Specifically, if X has been 110 and next
bit is 1, make Z high
21 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
How to Design States
• States remember past history• Clearly must remember we’ve
seen 110 when next 1 comes along
• Tell me one necessary state
22 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Beginning State
• Some state, A• If 1 appears, move to next state
BInput / Output
23 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Second 1
• New state, C• To reach C, must have seen 11
24 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Next a 0
• If 110 has been received, go to D
• Next 1 will generate a 1 on output Z
25 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
What else?
• What happens to arrow on right?
• Must go to some state.• Where?
26 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
What Sequence?
• Here we have to interpret problem
• We’ve just seen 01♦ Is this beginning of new 1101?♦ Or do we need to start over w/ another 1?
• They decide that it’s beginning (01…)
27 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Cover every possibility
• Well, must have every possibility out of every state
• In this case, just two: X = 0 or 1• You fill in other cases
28 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Fill in
29 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Answer From Book
30 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
State Minimization
• When we make state diagram, do we need all those states?
• Some may be redundant• State minimization procedures
can be used♦ We won’t cover now
31 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
How to code in Verilog
• Instead of learning how to hand design (Sections 4-6 and 4-7)
• Learn how to code this in Verilog
32 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Verilog Case Statement
• Similar to sequence of if/then/else case (expression)
case: statements; other case: statements; default: statements; // optional
endcase
• Example in a moment
33 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Parameter – Just Shorthand
module seq_rec_v(CLK, RESET, X, Z);input CLK, RESET, X;output Z;reg [1:0] state, next_state;
parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;
Notice that we’ve assigned codes to the states – more later
34 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Next State
always @(X or state)begin
case (state) A: if (X == 1)
next_state <= B; else
next_state <= A; B: if(X) next_state <= C;else next_state <=
A; C: if(X) next_state <= C;else next_state <=
D; D: if(X) next_state <= B;else next_state <=
A;endcase
end
The last 3 cases do same thing.Just sparse syntax.
35 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
On Reset or CLK
always @(posedge CLK or posedge RESET)beginif (RESET == 1)
state <= A;else
state <= next_state;end
Notice that state only gets updatedon posedge of clock (or on reset)
36 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Output
always @(X or state)begincase(state)
A: Z <= 0;B: Z <= 0;C: Z <= 0;D: Z <= X ? 1 : 0;
endcaseend
37 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Synthesis of Latches
• Sometimes unexpected latches created
• always will try to synthesize FFif (select) out <= A;♦ To save old value if select != 1
• If cover all possibilities, no FFif (select) out <= A;
else out <= B;
38 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Comment on Book Code
• Could shorten• Don’t need next_state, for example
♦ Can just set state on clock♦ Note that the two are a little different in function
• Don’t need three always clauses♦ Although it’s easier to have combinational code
to set output be separate
• Template helps synthesizer♦ Check to see whether your state machines were
recognized
39 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Read
• 7-1 and 7-11• Lab♦ I’d suggest spending time thinking
about the lock
40 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
Today
• Simple state machines♦ How to code them in Verilog
• Next Week♦ More on state machine styles♦ Registers♦ Counters♦ Info for next lab
• VGA timing
41 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
42 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
BACKUP
43 The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
One Shot
• Help me analyze this one
• What does it do?