The Timepix chip family · 2019-10-01 · Measured ENC ~110 e-rms Threshold dispersion before equalization ~400 e-rms ... 14th September 2005 Reduce min threshold 118 µs dynamic

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1

Medipix Symposium [18th September 2019]

The Timepix chip family

Xavier Llopart

18th September 2019

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Medipix2: Mpix2MXR20 (2005)

CSA

Disc

THH

14-bit

Shift

Register

Input

Ctest

Testbit

Test Input

Mask

3-bit THH Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8-bits PCR

Polarity

Analog

DDL

Shutter

3-bit THL Adj

Disc

THL

Digital

Overflow

Control

14111 µm

Measured pixel gain 10.7 mV/ke-

Measured ENC ~110 e- rms

Threshold dispersion before equalization ~400 e- rms

Threshold dispersion after equalization ~95 e- rms

Minimum detectable charge ~900 e-

On-chip threshold DAC step ~413 µV or ~40 e-

On-chip threshold DAC INL over the full range <2 LSB (80 e-)

Voltage DACs Temperature dependence 5.6 e-/°C

Pixel counter depth-Overflow control 11810-Yes

Maximum serial readout clock ~180 MHz

Pixel static power consumption ~8 µW

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Medipix2 Collaboration

• U INFN Cagliari• CEA-LIST Saclay• CERN Genève• U Erlangen• ESRF Grenoble• U Freiburg• U Glasgow• IFAE Barcelona• Mitthoegskolan• MRC-LMB Cambridge• U INFN Napoli• NIKHEF Amsterdam• U INFN Pisa• FZU CAS Prague • IEAP CTU in Prague • SSL Berkeley

http://medipix.web.cern.ch/MEDIPIX/

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From Mpix2MXR20 to Timepix

• First Idea by J. Visschers (NIKHEF): “Count arrival time by adding a clock in pixel”

• Design requested and funded by EUDet Collaboration:

– EUDet collaboration finished in 2010 AIDA

• Main features requested:

– Change counter function from particle counting to arrival time measurement(clock tick counting) to provided depth dimension in gas detectors

– Keep Timepix as similar as possible to Medipix2 series in order to benefit from large prior effort in R/O hardware and software

• Operating modes:

– Particle counting

– Arrival time:

• 10ns resolution @100MHz

• 118.1 µs dynamic range @100MHz

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From Mpix2MXR20 to Timepix

14th September 2005

Reduce min threshold

118 µs dynamic range

6 months design

Keep geometry as Mpix2

e- collection only (!?)

Spark reduction (!?)

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Timepix Operation Modes

• Particle counting

Open shutter Close shutter Open shutter Close shutter Open shutter Close shutter

• Time over threshold• Arrival Time

• TOT mode was added during the design phase:• Linear response up to ~300 Ke-/pixel

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First TOT measurements with a Medipix2 chip (I)

Medipix2: ADC using oscillating Front-End:• Discharging in amplifier is too fast (Ikrum) overshoots• Several overshoots can cross threshold level several

counts per single event.• Count depends on amplitude ADC in each pixel

Tests:• Tests with Medipix2 varying Ikrum• Temperature of the device held low (10°C) to decrease

noise• Alpha particle source used (alpha energy ~5MeV).• Up to 6 counts per pixel per event

Vthl

Jan JakůbekMedipix Meeting CERN, 21st September 2005

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First TOT measurements with a Medipix2 chip (II)

Medipix2: ADC by high frequency shutter:• Counter is incremented if

– signal is higher then threshold – and shutter is opened

• This condition can be valid several times during single pulse

• Number of counts depends on amplitude ADC• Response can be linear if constant current is used for

discharging.• Principle is similar to Wilkinson ADC type.

Tests:• Medipix2 with 5MHz on shutter input irradiated by

cosmic rays.• Playing with Ikrum parameter• Up to 10 counts per event.

=> Resolution of 7-8 bits is possible at 100MHz

Disadvantage:• Slightly higher noise

1 2 3 4 5 6 7

Threshold

Jan JakůbekMedipix Meeting CERN, 21st September 2005

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On-pixel Asynchronous state machine

Use of the discriminator output to gate the pixel clock No digital power consumption if no hit

Use of the clock to generate a glitch free counting signal

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Timepix pixel schematic (2016)• Improved CSA gain by adding a cascode in the OTA

• There is a single threshold with one 4-bit threshold adjustment DAC.

• Each pixel can be configured independently in three different operation modes (P0 and P1):

– Arrival time mode

– Energy mode (TOT)

– Event counting

• In acquisition mode there is a counting clock (Ref_Clk) distributed to the entire pixel matrix which is synchronised with the discriminator output (HIT)

CSA

DiscTHR

14 bits

Shift

Register

Input

Ctest

Testbit

Test Input

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8-bits PCR Polarity

Ref_Clk

Timepix

Synchronization

Logic

Ref_Clkb

P0

P1

Shutter

OvControl

Clk_Read

Shutter_int

Analog Digital

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Mpix2MXR20 Timepix Layout

Mpix2MXR20 (2005) pixel layout Timepix (2006) pixel layout

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Timepix (2006) chip architecture

IO

Logic

LVDS

In

LVDS

Out32-bit CMOS Output

256-bit Fast Shift Register

358

4-b

it P

ixel

Co

lum

n-0

358

4-b

it P

ixel

Co

lum

n-0

Bandgap + 13 DACs

16120

m

14111 m

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-2

55

358

4-b

it P

ixel

Co

lum

n-2

55

14080

m (

pix

el a

rray

)

• Chip architecture almost identical to Mpix2MXR20

• In acquisition mode chip an external clock is used as a time reference (up to 100 MHz)

• 256x256 55µm square pixels

• Analog Power -> 440mW

• Digital Power (Ref_Clk=50MHz) → 220mW

• > 36M Transistors

• Medipix2 and Timepix was designed as a system on chip design:

– On-chip digital global biasing:

• 14 DACs + Bandgap

– Simple control logic

– Serial readout (@100MHz) → 9.17 ms

– Parallel readout (@100MHz) → 287 µs

• Send to foundry on June 2006

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Gaseous detectors

• Use of Timepix to measure the arrival time or energy of deposited primary electrons in a gas volume

• No bump-bonded detector

Gas chamber

Anode

Drift volume

Grid

Amplification

Protection layer

CMOS chip

1.2mm

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Timepix with 3-GEM detector

• DESY testbeam in November 2006 (A.Bamberger, U. Renz, M.Titov, X. Llopart)

• Checked-board pattern (TOT and TIME)

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0

50

100

150

200

250

300

Jun-06 Jul-07 Jul-08 Jul-09 Jul-10 Jul-11 Jul-12 Jul-13 Jul-14 Jul-15 Jul-16 Jul-17 Jul-18 Jul-19

# w

afe

rs13 years of Timepix Production

299 wafers produced:• 31395 chips• > 2 billon pixels• 6.3 m2 active area

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Medipix3 Collaboration (from 2005)

• University of Canterbury, Christchurch, New Zealand

• CEA, Paris, France

• CERN, Geneva, Switzerland,

• DESY-Hamburg, Germany

• Albert-Ludwigs-Universität Freiburg, Germany

• University of Glasgow, Scotland, UK

• Leiden University, The Netherlands

• NIKHEF, Amsterdam, The Netherlands

• Mid Sweden University, Sundsvall, Sweden

• IEAP, Czech Technical University, Prague, Czech Republic

• ESRF, Grenoble, France

• Universität Erlangen-Nurnberg, Erlangen, Germany

• University of California, Berkeley, USA

• VTT, Information Technology, Espoo, Finland

• KIT/ANKA, Forschungszentrum Karlsruhe, Germany

• University of Houston, USA

• Diamond Light Source, Oxfordshire, England, UK

• Universidad de los Andes, Bogota, Colombia

• University of Bonn, Germany

• AMOLF, Amsterdan, The Netherlands

• Technical University of Munich, Germany

• Brazilian Light Source, Campinas, Brazil

22 members

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Timepix3 motivation

• Main driving requirements:

1. Simultaneous TIME (TOA) and CHARGE (TOT) information per pixel

2. Minimize dead time → Event-by-event readout and 0-supressed

3. Monotonic TOT in both detection polarities

4. Improve time measurements resolution

• Experience gained in the design of the Medipix3 chip (2009):

– Technology (130nm CMOS)

– Building blocks recycled (CERN’s HD Standard Cell library, DACs, …)

• Designed by CERN, Nikhef and Bonn University with the support of the Medipix3 Collaboration

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Timepix Timepix3

Timepix (2006) Timepix3 (2013)

Pixel arrangement 256 x 256

Pixel size 55 x 55 µm²

Technology 250nm CMOS 130nm CMOS

Acquisition modes1) Charge (TOT)2) Time (TOA)3) Event counting (PC)

1) Time (TOA) AND Charge (TOT)2) Time (TOA)3) Event counting (PC) AND integral charge (iTOT)

Readout Type 1) Frame based1) Data driven (DD) < 40 Mhits/s/cm2

2) Frame based (FB)

Zero suppressed readout NO YES

Dead time per pixel > 300µsreadout time of one frame

> 475nsPulse measurement time + packet transfer time

Minimum timing resolution 10ns 1.562ns

On-chip Power pulsing (PP) NO YES

Minimum detectable charge ~750e- >500e-

Technology IBM 250 nm CMOS IBM 130 nm CMOS

~600x

6.4x

1.5x

Programmable turn ON/OFF time

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Timepix3 Pixel Schematic

Global threshold (LSB= ~10e-)

Front-end (Analog)

LeakageCurrentcompensation

Preamp

Inputpad

1 pixel

VCO@640MHz

Super pixel (Digital)

Controlvoltage

Common for 8 pixels

640MHz

TpA TpB

TestBit MaskBit

Front-end (Digital)

Counters &

Latches

clock(40MHz)

Time stamp

14

-bits

Synchronizer&

Clock gating

OP Mode

4-bit LocalThreshold

~50mV/ke-

TOA (14-bit) FTOA (4-bit)TOT (10-bit)TOA & TOT

TOA (14-bit) FTOA (4-bit)TOA

iTOT (14-bit) PC (10-bit)PC & iTOT3fF

3fF

Deserializer[1x31]

Super pixel FIFO

[2x31]

Data outto EOC

37

-bit

s

clock(40MHz)

Token arbitration

31

-bit

s

han

dsh

ake

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Tpeak < 25ns

Pixel Operation in TOA & TOT [DD]

TOT (10 bits) =4

Preamp Out

Disc Out

Clk (40MHz)

FTOA (4 bits)=7VCO Clk (640MHz)

TOT Clk (40MHz)

TOA (14-bit) 16383X TOA (14 bits)=16383

16384 0 2 3 41638316382 1

Pixel Readout Starts (475ns→ 19 clock cycles)

Global TOA (14-bit)

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Pixel Operation in PC and iTOT [FB]

Preamp Out

Clk (40MHz)

Shutter

Pixel readoutcan start in

Data Driven orFrame based

Disc Out

3 0 PC (14 bits)=31 2PC (10-bit)

50 iTOT (14 bits)=51 2 3 4iTOT (14-bit)

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Trigger-less event-by-event data driven and zero-supressed readout

• Achievable count rate: – uniformly distributed events → ~40 Mhits/s/cm2 @5.12Gbps

• Full matrix readout: ~800 µs @5.12Gbps

Acquisition time

Address[16-bit]0xB Data[28-bits]

Data Packet (48 bits)

48bit 48bit 48bit 48bit 48bit 48bit

End of Command (48 bits)

Shutter

Qin

DataOut

ChipID [32b]0x71 0xB0

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Maximum Event ReadoutData Driven Readout

0

10

20

30

40

50

60

70

80

90

1 2 3 4 5 6 7 8

MH

itsP

rocc

ess

ed

/s

number of active links @640Mbps and 8b10b ON

20MHz40MHz60MHz80MHz>86MHz

Sys Clock

85.3 Mhits/s

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14100 µm

16

21

0 µ

m

Se

ns

itiv

e A

rea

(1

40

80

µm

)

Active Periphery (1260 µm)

Pad extenders (870 µm)

Timepix3 (2013)

Double column:2x256pixels64 super pixels

55 µm

55 µ

m

Super Pixel (SP):• 2x4 pixels• 110x220 μm2

Full Pixel Matrix:256x256 pixels128 double columns

8192 VCOs (640MHz)177 Mtransistors

Active Periphery

Pad Extenders:Removed if TSV

Analog Front-End:• 13x55 μm2

• <25% pixel area

VCO (FTOA):• 9.6x20 μm2

• < 0.8% SP area

IO Pad on digital area:• Careful shielding• Pad is ½ of Timepix

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Particle detection using Timepix3

Precise arrival time information (1.56ns steps) provides depth of interaction within the sensor layer

Ar 150 GeV/c

[p-on-n 500 µm sensor]

Cosmic ray

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From Timepix and Timepix3 Timepix2Timepix2 (2018)

Technology 130nm - 8metal



Sensitive area 1.98 cm2

Front End

e- collectionLeakage current compensation optimal (IDET>IKRUM)Non-monotonicity of the ToT vs Qin

h+ collectionLeakage current limited (IDET<IKRUM/2)Logarithmic gain mode

Pixel Readout

Single FrameTOT 10bits and TOA 18bits 1st hitTOT 14 bits and TOA 14bits

CRW

2x TOT 10bits and PC 4bits2x TOT 14bits2x TOA 10bits or 14bits2x PC 10 or 14 bits

Readout Type1 serial link < 100 Mbps 32 bit parallel < 3.2 Gbps

Timing resolution/range > 10ns / 2.620 ms @ 100MHz

Medipix2 collaboration funded project

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Timepix2 pixel schematic

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Timepix2 (2018)

• Simultaneous ToT and ToA

• Separate ToT and ToA clock

• Readout dead-time-free modes

• Fast clear

• Digital and analogue test pulses

• Digital and analogue pixel masking

– ROI

– coarse pitch bump bonding

• Adaptive frontend gain

• Reduced threshold dispersion

• Digital diagnostics modes

• Test points in analogue frontend

• Matrix occupancy monitor

• Digital-only pixels with wirebond input

• Serial port (full frame)

• 32b Parallel port (full frame)

• Serial port (zero column suppression)

• Serial communication with daisy-chaining (as in Medipix2/Timepix)

• IO compatible with TSVs

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14140 µm

16

36

6 µ

m

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Medipix4 Collaboration (from 2016)

• CEA, Paris, France

• CERN, Geneva, Switzerland,

• DESY-Hamburg, Germany

• Diamond Light Source, Oxfordshire, England, UK

• IEAP, Czech Technical University, Prague, Czech Republic

• JINR, Dubna, Russian Federation

• NIKHEF, Amsterdam, The Netherlands

• University of California, Berkeley, USA

• University of Houston, USA

• University of Maastricht, The Netherlands

• University of Canterbury, New Zealand

• University of Oxford, England, UK

• University of Geneva, Switzerland

• IFAE, Barcelona, Spain

• University of Glasgow, UK

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15 members

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Timepix3 Timepix4Timepix4: A 4-side tillable large single threshold particle detector chip

with improved energy and time resolution and with high-rate imaging

capabilities Timepix3 (2013) Timepix4 (2019)

Technology 130nm – 8 metal 65nm – 10 metal

Pixel Size 55 x 55 µm 55 x 55 µm

Pixel arrangement3-side buttable

256 x 2564-side buttable

512 x 448

Sensitive area 1.98 cm2 6.94 cm2

Re

ado

ut

Mo

de

s Data driven(Tracking)

Mode TOT and TOA

Event Packet 48-bit 64-bit

Max rate 0.43x106 hits/mm2/s 3.58x106 hits/mm2/s

Max Pix rate 1.3 KHz/pixel 10.8 KHz/pixel

Frame based(Imaging)

Mode PC (10-bit) and iTOT (14-bit) CRW: PC (8 or 16-bit)

Frame Zero-suppressed (with pixel addr) Full Frame (without pixel addr)

Max count rate ~0.82 x 109 hits/mm2/s ~5 x 109 hits/mm2/s

TOT energy resolution < 2KeV < 1Kev

Time resolution 1.56ns ~200ps

Readout bandwidth ≤5.12Gb (8x SLVS@640 Mbps) ≤163.84 Gbps (16x @10.24 Gbps)

Target global minimum threshold <500 e- <500 e-

3.5x

8x

5x8x

10x

33%

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Sensor

ASIC

PCB

4-side buttable: Motivation

• Build large area detectors by combining smaller modules

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Sensor

ASIC Pixel Matrix

ASIC Periphery

FC

Wire Bonding

PCB

FC

BGA

ASIC

PCB

Sensor

TSVs

4-side buttable: Challenge

• The through-silicon vias (TSVs) are the key technology for this paradigm shift

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A large 4-side buttable detector

• Advantages:

– Build large area detectors without dead area

– Better power distribution on chip (TSV) Larger single ASICs

– Mechanically more robust (no wire-bonds)

• Disadvantages:

– Periphery hidden or integrated in the pixels RDL between sensor and pixel input

• RDL Increase input capacitance and crosstalk (~30-50fF)

– Top metal layers “blocked” No MiMCaps, Inductors…

– Devices are only available after TSV processing (no wire-bonds)

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On-chip pad to pixel RDL

• Use of 10 metal option (1p9m + RDL): – Equalized Cin for all pixels ~46 fF

increase in Cin for a 460 µm periphery

– Shielding of RDL layers to minimize/eliminate cross-coupling

• RDL routing over analog pixel circuitry and periphery M7 used as shield

y = 0.0999x + 0.3542

0

10

20

30

40

50

60

70

80

0 100 200 300 400 500 600 700

Ave

rage

C [

fF]

Periphery Height [um]

average_b(worst)

average_b(best)

average_b(typ)

Linear (average_b(typ))

0

10

20

30

40

50

60

0 32 64 96 128 160 192 224 256

fF

row

equalizednot equalized

~0.1fF/µm

[0.1/1.2/GNDA]

384 µm periphery 55 µm/52 µm

pixel

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Timepix4 arrangement• 512 x 448 of 55 x 55 µm pixels

• 3 peripheries with TSV (Through-Silicon-Vias):– TOP, BOTTOM: Data Readout (10 Gbps Serializers)

– CENTRAL: Analog Blocks (DACs, ADC, Band-Gaps…)

• Edge peripheries also with ~1mm Wire Bond Pads:

– This can be diced-off to achieve a 100% sensitive area (4-side buttable)

• Interface to DAQ:– Through 3xTSVs

– Through 2xWB• 1xWB possible for low power applications

• Control architecture allows to operated Timepix4 from any of the 3 peripheries:

– i2C protocol

– Custom Slow Control protocol

• Fast readout requires at least 1 serial link enabled in each edge periphery

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Timepix4 Floorplan

• Chip size 28.16mm x 24.64 mm (no Wirebonds)

• 512 x 448 229376 pixels

• Pixel size 55µm x 55µm

• Analog Periphery ( 920 µm):

– BandGap + Temperature sensor

– Biasing DACs

– Monitoring ADC

– PLL for time reference

– Analog supply

– Digital supply

• 2 x Digital Periphery ( 460 µm):

– 8 x 10.28 Gbps serializers (configurable)

– PLL(s)

– Analog supply

– Digital supply

• 2 x Pixel matrix (13.28 mm x 24.64mm):

– 256 x 448 pixels 55 µm x 51.4 µm

– 5.68% smaller than 55 µm x 55 µm

– RDL to compensate up to 460.8 µm

36

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Timepix4 Pixel Schematic

Global threshold

Front-end

LeakageCurrentcompensation

Preamp

Inputpad

1 pixel

VCO@640MHz

Super pixel

Controlvoltage

8 pixels

640MHz

TpA TpB

TestBit MaskBit

Front-end

Counters &

Latches

Time stamp

16

-bits

Synchronizer&

Clock gating

OP Mode


~50mV/ke-

2.5fF

3fF

SyncReadout

Data outto EOC

8-b

its

clock(40MHz)

8-b

its

VDDA

VSSA

VIN

VBIKRUMN

M2a

CL

M2b

M0a

M1g

M1f

0

1 SelVOUTINT

VDDA

Polarity OR LogGainEn

VBILSP

VOUTPRE

CF/2

VFBK VOUTPRE

VDDA

VSSAIKRUM

IBLS

0

1 Sel

VDDA VBILSP

CSA

CSA BIASING (Periphery)

FEEDBACK

M6

M7a M7b

M0b

x2

IKRUM

IKRUM/2

IKRUM

M1b,c

VIN VOUTPRE

VBSCASC

VBS

M1

M0VIN

M3a

M2aVBSCASC

VBS M3a

M2a

VOUTINT

VBIKRUMN

M2c,dVFBK

DECOUPLING

0

1Sel

VDDA

LowGain

VOUTPRE

CF

VIN

CF/2VIN VOUTINT

VBRCM8

M9

LogGainEn

VIN

LogGainEn

VOUTPRE

VSSA

VDDA

ADAPTIVE GAIN

W/L=10/2

(C=260fF)

W/L=1/15

COFF=0.46fF

CON=260fF

VOUTINT COMP


VOUTINT

VOUTPRE

Open if LogGainEn=1

OR PolarityBit=1 (Positive

Polarity)

Closed if

LogGainEn=1

Additional feedback capacitance

VOUTINT COMP

LogGainEn

Compensation capacitance


PolarityBit=0 (NEGATIVE POLARITY)

Closed if

LogGainEn=1

0

1 Sel

VSSA

LowGain

4

8-bits

ADB

32 pixels

8

Clocklocal

bits

ADDR 9

ToA 16

ufToA_r 4

ufToA_f 4

fToA_r 5

fToA_f 5

ToT 12

Pileup 1

SPG

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65534X TOA (16 bits)=65534

Tpeak < 25ns

Pixel Operation in TOA & TOT [DD]

TOT (10 bits) =4

Preamp Out

Disc Out

Clk (40MHz)

VCO Clk (640MHz)

TOT Clk (40MHz)

TOA (16-bit)

65535 0 2 3 46553465533 1Global TOA (16-bit)

FTOA_R (4 bits)=7 FTOA_F (4 bits)=11

0XUFTOA_Start (4-bits)

8XUFTOA_Stop (4-bits)

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Edge Periphery

55 µm

EOC

TSV

Edge Periphery 460.8 µmPixel Matrix

10 Gbps

Serializer

TSV

TSV

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Digital (dynamic) Power Consumption [data-driven]

• Expected power consumption density to be ~20 % less of Timepix3:– Digital power consumption 25% less

• Improved clock distribution (DDLL)

• 130nm 65nm

– Analog consumption is ~5% more• Minimize jitter < 50ps

• Compensate increase in input capacitance

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

1 10 100 1000 10000 100000

W/c

m2

Pixel Hit Rate [Hz]

Total Power

DIG Power

ANA Power

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

1 10 100 1000 10000 100000

W/c

m2

Pixel Hit Rate [Hz]

Total Power

DIG Power

ANA Power

Timepix3 Timepix4

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24

70

0 µ

m

Timepix4 (2019)

Array 512 x 448

Pixels 229376

APLL 19

ADLL 16

10 Gbps serializers 16

On-pixel VCO 28672

DDLL Columns 448

Biasing DACs 13

ADC 1

Transistors in pixel ~6000

Transistors in chip ~1.5 b

29960 µm

41

55 µ

m

51.4

µm

55 µm

AN

AL

OG

DIG

ITA

LV

CO

VC

OA

DB

Sta

tio

n

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Timepix babies in HEP

• Velopix (2016):– Triger-less upgrade from LHCb VELO

– 130nm technology

– 256x256 55 µm pixels

– Binary information

– 20 Gbps data bandwitdth

– 800 Mhits/s/ASIC

• CLICpix1 (2013) and CLICpix2 (2016):– 65nm technology

– 25 µm pixel

– TOA and TOT

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0.01

0.1

1

10

0 100 200 300 400 500 600 700

Tra

ns

isto

r D

en

sit

y p

er

pix

el [T

ran

sis

tors

/µm

2]

CMOS process [nm]

Medipix Family of ASICs developed @CERN

Medipix1 (1998)

Timepix (2006)

Timepix3 (2013)

Medipix3RX (2009)

Timepix4 (2019)

Timepix2 (2018)

Medipix2MXR20 (2005)

Medipix4 (2020?)

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Conclusions

The Timepix family of chips has stimulated innovation for particle tracking over the last 13 years:

– Timepix (2006) measure time or charge in a portable/low power highly pixelated detector

– Timepix3 (2013) allowed us to measure event-by-event simultaneously time and charge with a time resolution of 1.5 ns

– Timepix2 (2018) extended the energy dynamic range measurement with a highly configurable pixel and readout architecture

– Timepix4 (2019) will give us a 4-side buttable chip with 229K pixels each on able to measure 200 ps arrival time resolution in a x4 larger sensitive area

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Thank you !

Medipix Collaboration meeting in Prague 2008

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SPARE

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Vertex Locator Upgrade

• bla

LHCb will be upgraded in 20192020 very tight planning

• Vertex detector surrounding collision region– In vacuum– Close to the beam: 5.1 mm

• From silicon strips to pixels• New R/O chip VeloPix, derived from Timepix3• In total 624 ASICs, ~41 Mpixels• Trigger-less readout (~2.9 Tbits/s) “The VeloPix ASIC test results” E. Lemos (poster)

“The LHCb Vertex Locator Upgrade” E. Lemos (talk)

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From Timepix3 Velopix

Timepix3 (2013) VeloPix (2016)



Peak hit rate 80 Mhits/s/ASIC800 Mhits/s/ASIC50 khits/s/pixel

Readout type Continuous, trigger-less, TOT Continuous, trigger-less, binary

Timing resolution/range 1.5625 ns, 18 bits 25 ns, 9 bits

Total Power consumption <1.5 W < 3 W

Radiation hardness 400 Mrad, SEU tolerant

Sensor type Various, e- and h+ collection Planar silicon, e- collection

Max. data rate 5.12 Gbps 20.48 Gbps

Technology IBM 130 nm CMOS TSMC 130 nm CMOS

10x

4x

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VeloPix Chip Architecture

• Pixel matrix:– 256 x 256 pixels– 128 x 64 super pixels (2x4 pixels each)– @40MHz

• Packet-based architecture:– 8 pixels/packet + 9 bit time stamp 30%

reduction in data rate

• Data-driven readout:– 20 Mpackets/s/double column

• 40, 80, 160 and 320 MHz TMR clock domains in the periphery

• 1 to 4 configurable serializers (GWT)

• Similar to the GBT frame

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VeloPix pixel schematic

1 pixel

Global threshold (LSB= ~15e-)

Front-end (Analog)LeakageCurrentcompensation

Preamp

Inputpad

TpA TpB

TestBit


4fF

5fF

Common for 8 pixels

ClockManager

24

-bit

s

Super pixel (Digital)

Data Node

24

-bit

s

24

-bit

s

10

-bits

FIFO (2x18)8

Addr (6-bit) TOA (10-bit) Hitmap (8-bit)

BXID To the nextSuperPixel

Synch

ron

ou

s h

and

shake

Synch

ron

ou

s h

and

shake

From previousSuperPixel

6-bits

Synchronizer&

Clock gating

Front-end (Digital)

Shu

tter Clock

(40/80 MHz)

6-bit LFSR:Counter

Shift RegisterTP

uls

e

6-bit TMRPixel memory

6-bits

6-b

its

ValidEvent

Dat

aIO

TOT Filter0 >0ns1 >25ns2 >50ns3 >75ns

MaskBit

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VeloPix (2016)

14.14 mm

Analog front-end

16 x 55 um²

Double column:2x256 pixels64 super pixels

Full matrix:128 Double columns

~190 Mtransistors

Pixel & Superpixel

Logic (HD Library)

16

.6 m

m

Active Periphery

2.4

mm

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VeloPix wafers

VeloPix Project Overview

• Design started in June 2013 (after Timepix3 submission)

• Velopix1 was submitted as an engineering run on May 2016

• First wafers received on 31st August 2016

• Design work very well, but:– Found an unexpected SEL (Single Event Latch-up)

sensitivity in the pixel matrix– SET (Single Event Transient) in the SLVS receivers)– High speed links (5.12 Gbps) showed excess jitter:

• From the PLL• Internal supply VDD-GND bouncing due to not

sufficient power internal decoupling

• Velopix2 submitted on August 2017 All good

• Velopix2 is currently being integrated in the experiment

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Expected Timepix4 Yield

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0 100 200 300 400 500 600 700 800 900

Yie

ld [

%]

die size [mm2]

Timepix3/Medipix3Yield=73%

0

50

100

150

200

250

300

350

400

450

500

550

600

650

0 100 200 300 400 500 600 700 800 900

die

s p

er

12

" w

afer

die size [mm2]

diesgood_die

Timepix3/Medipix3192/261 good dies

Timepix4Yield=37%

Timepix426/71 good dies

Based in the foundry yield model for

perfect dies

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Analog (static) power supply distribution

1 WB 2WB 3TSV

Nominal Analog Power [10 µA/pixel]

Vdrop [max-min] 68 mV 19.6 mV 6.9 mV

Imax pad 118 mA 60 mA 57 mA

Low Analog Power [1 µA/pixel]

Vdrop [max-min] 6.8 mV 1.96mV 0.69mV

Imax pad 11.8 mA 6 mA 5.7 mA

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Readout systems

• Many different readout systems available:

I/O interfaceTimepix

portfps # chips Power

Fitpix (UTEF) 1 x USB2.0 Serial ≤80fps ≤16 in daisy chain1 chip: USB or external (~1W)

>1 chip: external

Maxipix (ESRF) ESRF prop Parallel ≤1400fps 1, 2x2, 5x1 External (~30W)

eX Series (xray-Imatek)

GBit EthernetUSB2.0

Parallel ≤3440fps 1, 2x2, 2x4 External (24W)

STPX-(ASI) GBit Ethernet Serial ≤120fps 1, 2x2,8x8

RASPIX

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Optical High-Speed Imaging

Ceramic HeaderInterface PCB

e-

Medipix

Photon

Vacuum tube Photocathode LNS20

High Voltage

5-10kV

Single Photon counting

Pixelated detector

Unprecedented frame rates

Successor to the EMCCD?

K. Smith, V. O’Shea and co-workers, Glasgow, GB

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APPLICATIONS

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Timepix Applications• New Tracking Technologies

– LHCb Upgrade

– CLIC detectors

– Solid state Detector Development

• TPC instrumentation

– EUDET

• Emission Channeling Crystal Lattice Experiments

– ISOLDE

• Image Intensifiers / Optical Photon Detectors

– Adaptive Optics

– Bioimaging

– LHCb RICH

• ToF Mass Spectrometry

– Proteomic Imaging at AMOLF and Oxford

• Imaging Mass Spec

– Functional Cellular Biology at Kiev

• Photo Electron Emission Microscopy and Low Energy Electron Micrsocopy

• Neutron Monitoring at CNGS

• Space Dosimetry

• Education - CERN@School

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Documents

The Timepix chip family · 2019-10-01 · Measured ENC ~110 e-rms Threshold dispersion before equalization ~400 e-rms ... 14th September 2005 Reduce min threshold 118 µs dynamic