The Synthesis of Cyclic Combinational Circuits Marc D. Riedel and Jehoshua Bruck California Institute of Technology Email: {riedel, bruck}@paradise.caltech.edu

The Synthesis of The Synthesis of Cyclic Combinational Circuits Cyclic Combinational Circuits

Marc D. Riedel and Jehoshua Bruck

California Institute of Technology

Email: {riedel, bruck}@paradise.caltech.edu

Combinational Circuits

The outputs depend only on the present values of inputs.

time tinputs

1x

2x

mx

CombinationalCircuit

),,( 11 mxxf ),,( 12 mxxf

),,( 1 mn xxf

time (t+Δt)outputs

}1,0{}1,0{:, mjfj}1,0{, ixi

Generally acyclic (i.e., feed-forward) structures.


y

x

y

x

y

x z

z

z1f

2f

Generally acyclic (i.e., feed-forward) structures.


0

1

0

1

0

1

1

1

1

0

0

1

1

1

0

1

0

0

Circuits With Cycles

a b c

1f 2f 3f

May depend on timing.May have unstable/unknown outputs.

Circuits With Cycles

01 1

? ? ?

0: non-controlling for OR1: non-controlling for AND

May depend on timing.May have unstable/unknown outputs.

Cyclic Combinational Circuits

Cyclic circuits can be combinational.

Example due to Rivest (1977):

a b c a b c

f1 f2 f3 f4 f5 f6


b c b c

f1 f2 f3 f4 f5 f6

1 1




b c b c

f1 f2 f3 f5 f6

1 1

1




b c b c

f1 f2 f3 f5 f6

a a

f4




b c b c

f1 f2 f3 f4 f5 f6

0 0




b c b c

f2 f3 f4 f5 f6

0 0

0




There is feedback is a topological sense, but not in an electrical sense.

b c b c

f2 f3 f4 f5 f6f1

a a




There is feedback is a topological sense, but not in an electrical sense.

b c b ca a

)( cba )( bac )( cab cab cba bac



3 inputs, 6 fan-in two gates.An equivalent acyclic circuit requires 7 fan-in two gates.


b c b ca a





b c b ca a




n inputs,2n fan-in two gates (n odd).An equivalent acyclic circuit requires 3n – 2 fan-in two gates.

Prior Work

F(X) G(X)e.g., add e.g., shift

Stok (1992) observed cycles in designs that reuse functional units:

Malik (1994), Shiple et al. (1996), Edwards (2003) proposed techniques for analyzing cyclic combinational circuits.

X

G(F(X))

Y

F(G(Y))

Synthesis of Cyclic Combinational Circuits

• We propose a general methodology: optimize by introducing cycles in the substitution/minimization phase.

• We demonstrate that optimizations are significant and applicable to a wide range of circuits.

Example: 7 Segment Display

Inputs a

b

c

d

e

f

g

Output

1001

0001

1110

0110

1010

0010

1100

0100

1000

00000123 xxxx

9

8

7

6

5

4

3

2

1

0

Example: 7 Segment Display

g

f

e

d

c

b

a

)(

)(

))((

))((

))((

)(

))((

20321

10102321

2012103210

102213321

210203321

21310

302321320

xxxxx

xxxxxxxx

xxxxxxxxxx

xxxxxxxxx

xxxxxxxxx

xxxxx

xxxxxxxxx

a

b

c

d

e

f

g

Output

Substitution/Minimization

Basic minimization/restructuring operation: express a function in terms of other functions.

Substitute b into a:

(cost 9)a ))(( 302321320 xxxxxxxxx

(cost 8)

Substitute c into a:(cost 5)

Substitute c, d into a:(cost 4)

a )( 323212 bxxxxxbx

a cxxcx 321

a dccx 1

Acyclic Substitution

g

f

e

b

a

c

d

Select an acyclic topological ordering:

g

f

e

d

c

b

a

g

f

d

c

b

a

edcaxx 21

dccx 1

xxxxxxxxx 102213321 ))((

dxxxxxx 102320 )(

cdxx 10 )(


Cost (literal count): 37


e 3cxb d

ba f



Nodes at the top benefit little from substitution.

g

f

d

c

b

a

edcaxx 21

dccx 1

xxxxxxxxx 102213321 ))((

dxxxxxx 102320 )(

cdxx 10 )(

e 3cxb d

ba f

Cyclic Substitution

Try substituting every other function into each function:

Not combinational!Cost (literal count): 30

0

1

ex

dccx

fba

geex

bcdx

gxaxex

egxxax

2

3

321

202 f

g

f

d

c

b

a

e

Cyclic Substitution

g

f

e

d

c

b

a


Combinational solution:

x e0

bxa 3

gxxxax 1023 )(

axxex 321 )( exxxxxx 312320 )(

cxxcx 301

xxxfx 1023 )( f

Cyclic Substitution


Combinational solution:

topological cycles

g

f

e

d

c

b

a

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0


ba

ga

e

e

e

c

1

no electrical cycles

Cyclic Substitution

g

f

e

d

c

b

a

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

= [0,0,1,0]:

g

f

e

d

c

b

a


ba

ga

e

e

e

c

1

1

1

0

1

1

1

0

Cyclic Substitution


x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,0,1,0]:

g

f

e

d

c

b

a


ba

ga

e

e

e

c

1

1

1

0

1

1

1

0

a

b

c

d

e

f

g

Cyclic Substitution

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,0,1,0]:

g

f

e

d

c

b

a


ba

ga

e

e

e

c

1

1

1

0

1

1

1

0

a

b

c

d

e

f

g

Cyclic Substitution

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,0,1,0]:

g

f

e

d

c

b

a


ba

ga

e

e

e

c

1

1

1

0

1

1

1

0

a

b

c

d

e

f

g

Cyclic Substitution

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,0,1,0]:

g

f

e

d

c

b

a


Cyclic Substitution

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,1,0,1]:

g

f

e

d

c

b

a


Cyclic Substitution

ba

a

a

1

0

c

f

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,1,0,1]:


g

f

e

d

c

b

a


1

0

1

0

1

1

1

Cyclic Substitution

ba

a

a

1

0

c

f

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f


Inputs x3, x2, x1, x0 = [0,1,0,1]:

g

f

e

d

c

b

a


a

b

c

d

e

f

g

Cyclic Substitution

1

0

1

0

1

1

1ba

a

a

1

0

c

f

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,1,0,1]:

g

f

e

d

c

b

a


Cyclic Substitution

1

0

1

0

1

1

1ba

a

a

1

0

c

f

a

b

d

e

f

g

x e0

bxa 3

gxxxax 1023 )(


cxxcx 301

xxxfx 1023 )( f

Inputs x3, x2, x1, x0 = [0,1,0,1]:

c

Analysis

• Efficient, symbolic framework for analysis (BDD-based).• Analysis is integrated with synthesis phase.• For details see:

“Cyclic Combinational Circuit: Analysis for Synthesis,”

IWLS’03, available at http://www.paradise.caltech.edu/ETR.html

Combinationality Analysis:ensure that there are no sensitized cycles.

Timing Analysis:find the length of sensitized paths.

Analysis

Synthesis

Strategy:

• Allow cycles in the substitution phase of logic synthesis. • Find lowest-cost combinational solution.

21213

321321

312321

)(

)(

)(

xxxxxc

xxxxxxb

xxxxxxa

Collapsed:

Cost: 17

321

1321

323

xxaxc

cxxxxb

xxbxa

Solution:

Cost: 13

“Break-Down” approach

• Exclude edges• Search performed outside space

of combinational solutions

cost 12

cost 13 cost 12

cost 13combinational

cost 14

Branch and Bound

“Build-Up” approach

• Include edges• Search performed inside space

of combinational solutions

cost 17

cost 16cost 15not combinational

cost 14

Branch and Bound

cost 13best solution

Implementation: CYCLIFY Program

• Incorporated synthesis methodology in a general logic synthesis environment (Berkeley SIS package).

• Trials on wide range of circuits– randomly generated– benchmarks– industrial designs.

• Consistently successful at finding superior cyclic solutions.

Benchmark Circuits

Cost (literals in factored form) of Berkeley SIS Simplify vs. Cyclify

Circuit # Inputs # Outputs Berkeley Simplify Caltech Cyclify Improvementdc1 4 7 39 34 12.80%ex6 8 11 85 76 10.60%p82 5 14 104 90 13.50%t4 12 8 109 89 18.30%bbsse 11 11 118 106 10.20%sse 11 11 118 106 10.20%5xp1 7 10 123 109 11.40%s386 11 11 131 113 13.70%dk17 10 11 160 136 15.00%apla 10 12 185 131 29.20%tms 8 16 185 158 14.60%cse 11 11 212 177 16.50%clip 9 5 213 189 11.30%m2 8 16 231 207 10.40%s510 25 13 260 227 12.70%t1 21 23 273 206 24.50%ex1 13 24 309 276 10.70%exp 8 18 320 262 18.10%

(best examples)

Benchmarks

Example: EXP circuit

Cyclic Solution (Caltech CYCLIFY): cost 262

Acyclic Solution (Berkeley SIS): cost 320

cost measured by the literal count in the substitute/minimize phase

Discussion

• Should think of combinational circuits as cyclic, in general.

• Most circuits can be optimized with cycles.

• Optimizations are significant.

• General methodology for synthesis.• Efficient, symbolic framework for analysis.

Cyclic Combinational Circuits:

Paradigm shift:

Future Directions

• Extend ideas to a decomposition and technology mapping phases of synthesis.

• Address optimization of cyclic circuits for delay, power, fault tolerance.

Documents

The Synthesis of Cyclic Combinational Circuits Marc D. Riedel and Jehoshua Bruck California Institute of Technology Email: {riedel, bruck}@paradise.caltech.edu