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8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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THE SCAN-PATH TECHNFOR TESTABLE SEQUEN
CIRCUIT DESIGN
Presented by, Lavanyashree B. J LVS07 VLSI Design & Embe
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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NDEX
Combinational and sequential circuits
Scan path technique
Modified sequential circuit
Raceless D-type flip flop
Configuration of logic card
Advantages and Disadvantages
LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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COMBINATIONAL AND SEQUENTIALCIRCUITS
Complexity testing sequential circuits due to
feedback loops
lacement of the circuit in a kno!n state"
#iming problems in general
LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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SCAN PATH TECHNIQUE
$n %&'() *ippon electric company introduced a design for testabiltechniques called +SCA* A#, "
Scan is ability to shift into or out of any stat
Scan-path design is to reduce test generation complexity for circui
containing storage devices and feedback path !ith combinational l
#he philosophy is to divide conquer !ith the purpose to .
%" Set any internal state easily
/" 0bserve any state through a distinguishing sequence
LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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Mo"i#" $nral s%untial
circuit has folloin$ 'ro'rtis(
» )ircuit can asily b st toany "sir" intrnal stat
»)ircuit has "istin$uishin$ s%unc
Continued..
Fig1: A sequential circu
LVS07,VLSI &EMBEDDED SYSTEMS
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Continued..
1hen
C23 *ormal mode
C2% Shift Register
4ses double thro! s!itch
Double #hro!-S!itch has a
contact that can be connected
to either of t!o other
contacts"
Fig2: A realization for tthrow Switch
+
B
)
LVS07,VLSI &EMBEDDED SYSTEMS
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Continued..
Fig3: odi!ed sequenticircuit
Procedure for testing circuit is
%" Set C2% to s!itch circuit to
shift register mode
/" Check operation as shift register
by scan in inputs )scan-outoutputs and clock
5" Set initial state of shift register
6" Set C23 to return to normal
mode
(" Apply test input pattern to
combinational logic7" Set C2% ting state to return to
shift register mode
'" Shift out final state !hile setting
the starting state for the next
test"
8" 9o to step 6LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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Continued..
Fig ! R"ce#ess f#i$ f#o$ %it& sc"n $"t&
R"ce#ess D't($e f#i$ f#o$
Nor)"# o$er"tion!
C/2% C%23
So data is latched to D
1hen C%2%
0utput of :% is latched
Sc"n in o$er"tion!
C/23#est input is applied at
1hen C/2%
0utput of :% is latched
Scan-out
LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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Configur"tion of Logic c"rd
•,ere flip flops are connected
as shift register
• ;ach card has one scan path"
Fig *! Configur"tion of #ogi
Scan-in
Continued..
LVS07,VLSI &EMBEDDED SYSTEMS
8/16/2019 The Scan-path Technique for Testable Sequential Circuit Design - Copy
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Ad"antages and Disad"antages
Advantages.
< Design automation
< ,igh fault coverage= helpful in diagnosis
< ;asy to generate test pattern
Disadvantages.
< :arge test data volume and long test time
< Requires extra pins or gates for transformation
LVS07,VLSI &EMBEDDED SYSTEMS
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THAN+ ,O
LVS07,VLSI &EMBEDDED SYSTEMS