The PANDA Microvertex Detector · A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 ... With a second magnet provides angular coverage for the most forward angles. 1T dipole. p

A. Rivetti VIPS workshop-Pavia, April 23rd, 2010

The PANDA Microvertex

Detector: Present Design and Opportunities for 3D Integration Technologies

Angelo Rivetti –

INFN-Sezione di TorinoOn behalf of the PANDA MVD group


Strong Interaction Studies with AntiprotonsStrong Interaction Studies with Antiprotons

Darmstadt, GermanyDarmstadt, Germany

FAIRFAIR

Facility for Antiproton and Ion Research

antiProton

ANnihilation

at DArmstadt

PANDA @ FAIR


p

Hydrogen Pellet Target

Luminosity Luminosity Momentum Resolution (Momentum Resolution (δδp/pp/p))

High luminosity High luminosity modemode 2x1032 cm-2s-1 ~10-4 (stochastic cooling)

High resolution High resolution modemode 1031 cm-2s-1 ~10-5 (electron cooling < 8 GeV/c)

HESRHESR

= = HHigh igh EEnergy nergy SStorage torage RRingingMomentum: Momentum: 1.5 1.5 GeV/cGeV/c

--

15 15 GeV/cGeV/c

p

Center of

mass energy:

√s = 5.5 GeV

Antiproton beam


Enhanced forward emission for light targets and distribution over full polar angle for particles momenta below 1 GeV/c.

Combination of colliding beam and fixed target geometry.

Simulated particle distribution


12m

4m

Target SpectrometerSurrounds the interaction region.Solenoidal

2T magnet.

Forward

SpectrometerWith a second magnet provides angular coverage for the most

forward

angles. 1T dipole

p

The PANDA detector complex


Four barrels:-

Two Inner

layers: pixels.-

Two outer

layers: strips.Six forward disks:-

4 pixels + 2 mixed disks.

Read-Out channels and area coverage:

Pixels : 12M channels, 0.14 m2.Strips : 200k channels, 0.5 m2.Strips are double sided

The MVD is the closest detector to the interaction point The MVD is the closest detector to the interaction point

Primary function: vertexingPrimary function: vertexing

Additional task: dE/dx

for dE

up to 2.3 MeVAdditional task: dE/dx

for dE

up to 2.3 MeV

The MicroVertex

Detector (MVD)


Pixel detector specifications

Baseline technology : hybrid pixel detectors.A dedicated front-end chip under development in 0.13 μm.Custom front-end development motivated by high track density (12.3

MHz/cm2) and trigger-less operation.

Pixel cell specificationsPixel cell specifications

Pixel Pixel SizeSize 100100μμm x 100m x 100μμmm

NoiseNoise LevelLevel 200 e200 e‐‐ rmsrms

Linear Linear dynamicdynamic rangerange Up Up toto 100fC100fC

PowerPower consumptionconsumption < 20< 20μμWW

Input Input polaritypolarity SelectableSelectable

LeakageLeakage insensitiveinsensitive Up Up toto 50 nA50 nA

Pixel cell specificationsPixel cell specifications

Pixel Pixel SizeSize 100100μμm x 100m x 100μμmm

NoiseNoise LevelLevel 200 e200 e‐‐ rmsrms

Linear Linear dynamicdynamic rangerange Up Up toto 100fC100fC

PowerPower consumptionconsumption < 20< 20μμWW

Input Input polaritypolarity SelectableSelectable

LeakageLeakage insensitiveinsensitive Up Up toto 50 nA50 nA

ASIC specificationsASIC specifications

TriggerTrigger SelfSelf triggeringtriggering

Active areaActive area O(1cmO(1cm22))

Data rateData rate O(0.8 O(0.8 GbitGbit/sec.)/sec.)

Radiation toleranceRadiation tolerance ˜̃ 10101414 nneqeq /cm/cm22

Simultaneous time stamping andSimultaneous time stamping andcharge measurementcharge measurement

Good time resolution Good time resolution rmsrms 1.8 ns (at 160 MHz 1.8 ns (at 160 MHz clock) clock) withwith 22∙∙101077 annann/s/s

ASIC specificationsASIC specifications

TriggerTrigger SelfSelf triggeringtriggering

Active areaActive area O(1cmO(1cm22))

Data rateData rate O(0.8 O(0.8 GbitGbit/sec.)/sec.)

Radiation toleranceRadiation tolerance ˜̃ 10101414 nneqeq /cm/cm22

Simultaneous time stamping andSimultaneous time stamping andcharge measurementcharge measurement

Good time resolution Good time resolution rmsrms 1.8 ns (at 160 MHz 1.8 ns (at 160 MHz clock) clock) withwith 22∙∙101077 annann/s/s


100

100 μμ mm

100

100 μμmm

Pixel module

concept

Geometrical constraints dictates the use of four differentmodule size.

Red circles=parts that might benefit from a 3D approach

Module controller or more cables…


Pixel module

types

Minimal set of modules to have adequate coverageSame width, four different lengths


Pixel sensors

Baseline choice: epitaxial silicon substratep-in-n sensor implementationepitaxial thickness: 50-100 μm.Inert substrate: 50 μm.Alternative: oxygen enriched silicon


In each

pixelThe

control

logic

receives

the

signal

from

the

comparator

and

stores

the

value

on

the

time

stamp

bus

(Gray

encoded)

at

the

rising

and

falling edge in two 12 bit registers.It is present also a 12 bit configuration register.SEU tolerant logic (based on the DICE cell)

Each

column

The

readout

logic

made

in

a

fixed

priority scheme

to

read

the timestamps

of

the

pixel

cells

and

to

read/write

the

configuration

bits.

Master clock @160 MHzMaster clock @160 MHz

Pixel read-out


The analog Front-End generates a pulse whose width is proportional to the charge injected by the sensor.

ToTo

the the digitaldigital

partpart

ToT

Front-end

cell

Single Pixel Power dissipation of 15 μW from a 1.2 V power supply.


Chip prototyping: ToPiX

2.0

31 032 6395 6496 127

31 032 6395 6496 127

31 031 0

128 pixel column length: 12.8 mm.

384 pixel cell

in four columns:

• Two folded columns with 128 pixels.• Two short column with 32 pixels.

• Simplified end‐of‐column logic.

• Sixteen pixels with wire bonding pad.

ToPix 2.0 is a reduced scale prototype front-end chip for the hybrid pixel sensors.It has been designed in a CMOS 0.13 μm technology and tested.

The final version of ToPiX will consist of a matrix of 116x110 cells with a pixel size 100 μmx100 μm, thus covering a 1.28 cm2 active area.


Pulse shape reconstruction using ToTinformation for different loads at the input.

Some experimental results

0.8

0.7

0.6

0.5

0.4

0.3

Thre

shol

d vo

ltage

(V)

543210Time (µs)

Unbonded Wire-bonded to pixel Wire-bonded to board, 1pF cap

400

300

200

100

0

0.200.150.100.050.00TOT (clk) * tail slope (V/clk)

Topix2Am241 (γ 60keV)

ch 019 ch 020 ch 023

Americium 60 keV signal in 300 thick μm standard silicon (pixel size 300 μm x 300 μm)


Signal to noise ratio is limited by parasitics capacitance due the external connections. Bonding pad+wirebonding+protection diodes.

Epitaxial

sensor 50 μm thick, size: 125μm x 325 μmSource: Am241, γ

at 60keVEpitaxial

sensor 50 μm thick, size: 125μm x 325 μmSource: Am241, γ

at 60keV

Tests with an epi-sensor


Silicon microstrip


Silicon microstrip modules


Silicon microstrip modules


AnalogAnalog DigitalDigital

100

100 μμ mm

70+30 70+30 μμmm

Do we need extra-dimensions?

Each cell incorporates:Front-end amplifierLeakage compensation5 bit DACs for threshold tuningComparator12 bits configuration registerOne register for leading edgeOne register for trailing edge

In the present implementation, most of the space reserved to the analog part, but…

3D approach mostly interesting for the pixel part of the MVD


DICE cell in 0.13μm technology improves SEU resistance,

but not as much as for previous technologies.Improved radiation hardness=more space for the digital

part and less for the analog one, with adverse affect on

matching

Test performed

at Laboratori Nazionali Legnaro, using

Silicon

Radiation

(SIRAD) facility

Ions

used

in the beam

test: 16O, 19F, 28Si, 35Cl, 58Ni, 79Br

Weibull

distribution

Dice cell

SEU performance


A two tiers approach?

In the present design only 2/3 (1/2 in the next prototype) of the pixel area is available for the routing of the analog power rails.

No room for local tuning of the feed-back current (no space for DACs and registers) ⇒ relatively large ToT spread (12% rms).

Further reduction in density in the next prototype due to the (necessary) migration to a different flavor of the process.

Need to make some compromise on analog performance and on the possibility of adding very desirable features (e.g. protection against “monster hits”).

In 1D

Obvious partitioning: One tier for the analog and one for the digital part. Analog tier: preamplifier, comparator, DACS.Digital tier: all the rest…Room for more sophisticated digital processing: no controller chip and less cables!Room for significant amount of on chip decoupling capacitors…

In 2D


In summary…

The MVD is a compact but complex detector designed by a relatively small collaboration (compared to LHC detectors).

Rely on well established technologies and minimize custom developments.

In the R&D phase monitoring other developments that may bring significant advantages in term of cost/performance.

3D integration particularly appealing for the hybrid pixel part.Points that will be of interests

Cheap alternatives to bump bondingThinner electronics/sensorsBetter front-end electronics (increased functionality due

to multi-layers chips)

Documents

The PANDA Microvertex Detector · A. Rivetti VIPS workshop-Pavia, April 23rd, 2010 ... With a second magnet provides angular coverage for the most forward angles. 1T dipole. p