The MAXQTM Family of High Performance Microcontrollers · Dallas Semiconductor - MAXIM 12 MAXQ Benefits zSingle Cycle Execution zNo Instruction Pipeline Single Cycle Relative Branching

The MAXQTM Family of High Performance Microcontrollers

The MAXQTM Family of High Performance Microcontrollers

Kris ArdisSenior Software Engineer

Dallas Semiconductor/MAXIMhttp://www.maxim-ic.com/MAXQ

Microprocessor Summit[MPS-920]Booth 826

March 7, 2005

Kris ArdisKris ArdisSenior Software EngineerSenior Software Engineer

Dallas Semiconductor/MAXIMDallas Semiconductor/MAXIMhttp://www.maximhttp://www.maxim--ic.com/MAXQic.com/MAXQ

Microprocessor SummitMicroprocessor Summit[MPS[MPS--920]920]Booth 826Booth 826

March 7, 2005March 7, 2005

Dallas Semiconductor - MAXIM 2

What’s Our Strategy?What’s Our Strategy?High Growth

Product DifferentiationHigh performanceLow power‘Q’uiet for Analog integration

High Growth High Growth

Product DifferentiationProduct DifferentiationHigh performanceHigh performanceLow powerLow power‘‘QQ’’uietuiet for Analog integrationfor Analog integration

Large Serviceable MarketLarge Serviceable MarketLarge Serviceable Market

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2002 2003 2004 2005

8-bit805116-bit P

rice


16-bit Instruction Word16-bit Instruction Word

Classical ‘MOVE’ operationByte literal source capabilityModule[Index]=

RegisterMemory AccessTriggered Hardware Operation

Classical Classical ‘‘MOVEMOVE’’ operationoperationByte literal source capabilityByte literal source capabilityModule[Index]=Module[Index]=

RegisterRegisterMemory AccessMemory AccessTriggered Hardware OperationTriggered Hardware Operation


Example Transfer MapExample Transfer Map


Instruction Decode & TransferInstruction Decode & Transfer

TRANSPORTNETWORK

TRANSPORTNETWORK


Direct MOVE OperationsDirect MOVE Operations

MOVE DP[0], A[0]

TRANSPORTNETWORK

MOVE DP[0], A[0]

TRANSPORTNETWORK


Indirect MOVE OperationIndirect MOVE Operation

MOVE @DP[0], A[0]

TRANSPORTNETWORK

MOVE @DP[0], A[0]

TRANSPORTNETWORK


Triggered Hardware OperationsTriggered Hardware Operations

MOVE A[4], #55h

#55h TRANSPORTNETWORK

MOVE A[4], #55h

#55h TRANSPORTNETWORK


Indirect + Triggered HardwareIndirect + Triggered Hardware

MOVE @++DP[0], A[0]

++

TRANSPORTNETWORK

MOVE @++DP[0], A[0]

++

TRANSPORTNETWORK


MAXQ Instruction – revisitedMAXQ Instruction – revisited

Symmetric source, destination rangesLarger register space accessibleInstruction set extension

Symmetric source, destination rangesSymmetric source, destination rangesLarger register space accessibleLarger register space accessibleInstruction set extensionInstruction set extension


Prefix Usage ExamplePrefix Usage Examplemove DP[0], #1234hmove DP[0], #1234hmove DP[0], #1234h

move PFX[0],#12h

move DP[0],#34h

Prefix register

Prefix register

DP[0] register


MAXQ BenefitsMAXQ Benefits

Single Cycle ExecutionNo Instruction Pipeline

Single Cycle Relative BranchingHarvard Memory Map

Pseudo-VonNeumannLarge Register Space

Useable for General Purpose Registers and PeripheralsInstruction Set Expansion Capability‘Q’uiet Environment for Analog IntegrationLow Power

Single Cycle ExecutionSingle Cycle ExecutionNo Instruction PipelineNo Instruction Pipeline

Single Cycle Relative BranchingSingle Cycle Relative BranchingHarvard Memory MapHarvard Memory Map

PseudoPseudo--VonNeumannVonNeumannLarge Register SpaceLarge Register Space

Useable for General Purpose Registers and PeripheralsUseable for General Purpose Registers and PeripheralsInstruction Set Expansion CapabilityInstruction Set Expansion Capability‘‘QQ’’uietuiet Environment for Analog IntegrationEnvironment for Analog IntegrationLow PowerLow Power

Features of the MAXQ CoreFeatures of the MAXQ Core


Working AccumulatorsWorking Accumulators

Direct, Indirect, or Implicit AccessAuto-inc/dec/modulo controlsALU ops implicitly target Acc

Direct, Indirect, or Implicit AccessDirect, Indirect, or Implicit AccessAutoAuto--inc/inc/decdec/modulo controls/modulo controlsALU ops implicitly target AccALU ops implicitly target Acc


Data PointersData Pointers

Two standard DP[n]One frame pointer FP=BP[Offs]Auto-inc/dec supportSelectable word or byte access modes

Two standard DP[n]Two standard DP[n]One frame pointer FP=BP[Offs]One frame pointer FP=BP[Offs]AutoAuto--inc/inc/decdec supportsupportSelectable word or byte access modesSelectable word or byte access modes

DP[0]

DP[1]

BP OFFS

@ (++/--)DP[n]@ BP[(++/--)OFFS]

@ DP[n](++/--)@ BP[OFFS(++/--)]

+

16-bit 8-bit

DataMemory

WBS0WBS1WBS2

SDPS1:0


Loop CountersLoop Counters

move LC[0], #16 ; load loop counterloop: ;----------

; loop code;----------djnz LC[0], loop ; dec counter, jump <>0

move LC[0], #16 ; load loop countermove LC[0], #16 ; load loop counterloop: ;loop: ;--------------------

; loop code; loop code;;--------------------djnzdjnz LC[0], loopLC[0], loop ; ; decdec counter, jump <>0counter, jump <>0

Two 16-bit LC[n] registers availableReduced loop overhead Two 16Two 16--bit LC[n] registers availablebit LC[n] registers availableReduced loop overhead Reduced loop overhead


Built-In Debug SupportBuilt-In Debug Support

6 breakpoints supported in hardwareROM assisted routines for debug register and memory access

6 breakpoints 6 breakpoints supported in supported in hardwarehardwareROM assisted ROM assisted routines for debug routines for debug register and memory register and memory accessaccess

MAXQ PerformanceMAXQ Performance


One benchmark: MIPSOne benchmark: MIPSAt 20 MHz, MAXQ2000 approaches 20 MIPSDoes this mean anything?

NOHeavily instruction set architecture dependent

Which machine is better?Machine 1 (20MHz) Machine 2 (10MHz)MOVE Rn, #55h MOVE Reg, #55hMOVE Reg, Rn

MIPS requirement is application and algorithm dependent

YESIf we assume similar instruction set architectures

At 20 MHz, MAXQ2000 approaches 20 MIPSAt 20 MHz, MAXQ2000 approaches 20 MIPSDoes this mean anything?Does this mean anything?

NONOHeavily instruction set architecture dependentHeavily instruction set architecture dependent

Which machine is better?Which machine is better?Machine 1 (20MHz)Machine 1 (20MHz) Machine 2 (10MHz)Machine 2 (10MHz)MOVE MOVE RnRn, #55h, #55h MOVE MOVE RegReg, #55h, #55hMOVE MOVE RegReg, , RnRn

MIPS requirement is application and algorithm dependentMIPS requirement is application and algorithm dependent

YESYESIf we assume similar instruction set architecturesIf we assume similar instruction set architectures


Normalized MIPS/MHzNormalized MIPS/MHz

Calculate Average MIPS/MHz= average # instructions executed / clock= total instruction count / total cycle count

Penalize poor instruction set efficiency= Avg MIPS/MHz / total instruction count

MAXQ approaches 1 MIPS/MHz

Calculate Average MIPS/MHzCalculate Average MIPS/MHz= average # instructions executed / clock= average # instructions executed / clock= total instruction count / total cycle count= total instruction count / total cycle count

Penalize poor instruction set efficiencyPenalize poor instruction set efficiency= = AvgAvg MIPS/MHz / total instruction countMIPS/MHz / total instruction count

MAXQ approaches 1 MIPS/MHzMAXQ approaches 1 MIPS/MHz


Computing MIPS/mAComputing MIPS/mA

mA/MHz: Metric for Dynamic Current ConsumptionCritical assumption of ~0 static currentUse Common Supply Voltage (e.g. 3V)Use datasheet typical or extrapolate from datasheet characterization data

MIPS/mA considers instruction set efficiency and consumptionMAXQ2000: industry best 5.1 mA at 20 MIPS, ~4 MIPS/mA

mAmA/MHz: /MHz: Metric for Dynamic Current ConsumptionMetric for Dynamic Current ConsumptionCritical assumption of ~0 static currentCritical assumption of ~0 static currentUse Common Supply Voltage (e.g. 3V)Use Common Supply Voltage (e.g. 3V)Use datasheet typical or extrapolate from Use datasheet typical or extrapolate from datasheet characterization datadatasheet characterization data

MIPS/MIPS/mAmA considers instruction set efficiency considers instruction set efficiency and consumptionand consumptionMAXQ2000: industry best 5.1 MAXQ2000: industry best 5.1 mAmA at 20 MIPS, at 20 MIPS, ~4 MIPS/~4 MIPS/mAmA

MAXQ PeripheralsMAXQ Peripherals


Existing MAXQ PeripheralsExisting MAXQ PeripheralsTimer/Counters

Capture, compare, gating and PWM outputUARTSPI1-Wire LCD Controller

Up to 132 segment driver (33x4), Internal LCD bias resistors Piezo-electric Horn DriverAnalog-to-Digital Converters

16-bit 20.8ksps Sigma-Delta

Timer/CountersTimer/CountersCapture, compare, gating and PWM outputCapture, compare, gating and PWM output

UARTUARTSPISPI11--Wire Wire LCD Controller LCD Controller

Up to 132 segment driver (33x4), Internal LCD bias resistors Up to 132 segment driver (33x4), Internal LCD bias resistors PiezoPiezo--electric Horn Driverelectric Horn DriverAnalogAnalog--toto--Digital ConvertersDigital Converters

1616--bit 20.8ksps Sigmabit 20.8ksps Sigma--Delta Delta


More MAXQ PeripheralsMore MAXQ Peripherals

CAN Controller9V RegulatorAnalog ComparatorFlash/EEPROM Controller for IAPHardware Multiplier

Signed/unsigned operations, Multiply-accumulate/subtract

CAN ControllerCAN Controller9V Regulator9V RegulatorAnalog ComparatorAnalog ComparatorFlash/EEPROM Controller for IAPFlash/EEPROM Controller for IAPHardware MultiplierHardware Multiplier

Signed/unsigned operations, MultiplySigned/unsigned operations, Multiply--accumulate/subtractaccumulate/subtract


Released: MAXQ2000Released: MAXQ2000

LCD Controller supports 132 segmentsHardware MAC3 timers, 2 UARTs, SPI, 1-Wire32k x 16 flash1k x 16 RAM

LCD Controller LCD Controller supports 132 supports 132 segmentssegmentsHardware MACHardware MAC3 timers, 2 3 timers, 2 UARTsUARTs, , SPI, 1SPI, 1--WireWire32k x 16 flash32k x 16 flash1k x 16 RAM1k x 16 RAM


MAXQ2000 Evaluation KitMAXQ2000 Evaluation Kit4½ 7-segment LCDRS232 shifterAll I/O availablePushbuttons tied to external interruptsLED Bank16 MHzMAX1407 ADC/DACJTAG Debug Board and connector

44½½ 77--segment LCDsegment LCDRS232 shifterRS232 shifterAll I/O availableAll I/O availablePushbuttons tied to Pushbuttons tied to external interruptsexternal interruptsLED BankLED Bank16 MHz16 MHzMAX1407 ADC/DACMAX1407 ADC/DACJTAG Debug Board JTAG Debug Board and connectorand connector


Coming soon: MAXQ7654Coming soon: MAXQ7654

CAN 2.0B Controller12-bit ADC/DACSPI4 timersHardware MAC64k x 16 flash1k x 16 RAM

CAN 2.0B ControllerCAN 2.0B Controller1212--bit ADC/DACbit ADC/DACSPISPI4 timers4 timersHardware MACHardware MAC64k x 16 flash64k x 16 flash1k x 16 RAM1k x 16 RAM


Coming soon: MAXQ3210/2Coming soon: MAXQ3210/2

9V Regulator (3210 only)1k x 16 EEPROM16-bit timer64 x 16 Data EEPROMComparatorLow Battery Detection Piezoelectric Horn Driver (3210 only)

9V Regulator (3210 9V Regulator (3210 only)only)1k x 16 EEPROM1k x 16 EEPROM1616--bit timerbit timer64 x 16 Data EEPROM64 x 16 Data EEPROMComparatorComparatorLow Battery Detection Low Battery Detection Piezoelectric Horn Piezoelectric Horn Driver (3210 only)Driver (3210 only)


Coming Soon: MAXQ3120Coming Soon: MAXQ312016k x 16 flash256 x 16 RAM16-bit ∆Σ ADC (> 20 ksps @ 8MHz)112 segment LCD driverHardware MAC2 UARTs, 3 TimersRTC

16k x 16 flash16k x 16 flash256 x 16 RAM256 x 16 RAM1616--bit bit ∆Σ∆Σ ADC (> 20 ADC (> 20 kspsksps @ 8MHz)@ 8MHz)112 segment LCD 112 segment LCD driverdriverHardware MACHardware MAC2 2 UARTsUARTs, 3 Timers, 3 TimersRTCRTC


Future DirectionsFuture Directions

Leverage existing expertise: Security, NetworkMAXIM Analog Expertise + Dallas High Performance MicrosApplication Targeted IntegrationLarger address spaces

Leverage existing Leverage existing expertise: Security, expertise: Security, NetworkNetworkMAXIM Analog MAXIM Analog Expertise + Dallas Expertise + Dallas High Performance High Performance MicrosMicrosApplication Targeted Application Targeted IntegrationIntegrationLarger address Larger address spacesspaces


World Class ToolsWorld Class Tools

Rowley CrossWorksCrossConnect DebuggerHighly Optimized C Compiler

IAR Systems Embedded WorkbenchC/C++ CompilerC-SPY Debugger

MAX-IDEFree assembler and debugger

Rowley Rowley CrossWorksCrossWorksCrossConnectCrossConnect DebuggerDebuggerHighly Optimized C CompilerHighly Optimized C Compiler

IAR Systems Embedded WorkbenchIAR Systems Embedded WorkbenchC/C++ CompilerC/C++ CompilerCC--SPY DebuggerSPY Debugger

MAXMAX--IDEIDEFree assembler and debuggerFree assembler and debugger

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The MAXQTM Family of High Performance Microcontrollers · Dallas Semiconductor - MAXIM 12 MAXQ Benefits zSingle Cycle Execution zNo Instruction Pipeline Single Cycle Relative Branching