The MARCO/DARPA Gigascale Silicon Executive Advisory Group … · 2001. 10. 11. · Page 3 The MARCO/DARPA Gigascale Silicon Research Center for Design & Test: Form Executive Advisory

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The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test: Form

Executive Advisory Group Review23 September 1999

11

�� Describe & verify product behaviorDescribe & verify product behavior

�� Describe product architecturesDescribe product architectures�� Explore HW/SW design tradeoffsExplore HW/SW design tradeoffs

ss Map behavior to architectureMap behavior to architecturess Use performance simulationUse performance simulationss Perform communication refinementPerform communication refinement

�� Integrated flow to implementation Integrated flow to implementation

SystemSystemBehaviorBehavior

SystemSystemArchitectureArchitecture

MappingMapping

Flow To ImplementationFlow To Implementation

CommunicationRefinement

BehaviorBehaviorSimulationSimulation

PerformancePerformanceSimulationSimulation

21

3

4

The Essence of Polis/Felix/VCC Project: Virtual The Essence of Polis/Felix/VCC Project: Virtual Component CoComponent Co--designdesign

1988:1988:

22

TheThe next level of Abstraction …next level of Abstraction …

abst

ract

Transistor ModelCapacity Load

1970’s

cluster

abst

ract

Gate Level ModelCapacity Load

1980’s

RTL

cluster

abst

ract

SDFWire Load

1990’s

IP Blocks

cluster

abst

ract

IP Block PerformanceInter IP Communication Performance Models

RTLClusters

SWModels

Year 2000 +

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33

Architectural ChoicesArchitectural Choices

µP

Prog Mem

MACUnit

AddrGenµP

Prog Mem

µP

Prog Mem

Satellite

ProcessorDedicated

Logic

Satellite

Processor

Satellite

Processor

GeneralPurpose

µP

Software

DirectMapped

Hardware

HardwareReconfigurable

Processor

ProgrammableDSP

Flex

ibili

tyFl

exib

ility

1/Efficiency (power, speed)1/Efficiency (power, speed)

44

OMAP™ Block DiagramOMAP™ Block Diagram

I-MMU D-MMU

I-Cache

RISC Core

MMU

I-CacheInternal

RAM/ROM

DSP Core+

Appl Coprocessors

DMA

Memory & Traffic Controller

ProgramMemory SDRAM

PeripheralsLCD Controller, Interrupt Handlers, Timers, GPIO, UARTs, ...

uuARM9 coreARM9 core

uu16KB I16KB I --cachecache

uu8KB D8KB D--cachecache

uu22--way set way set

associativeassociative

uu150 MHz150 MHz

uuC55x DSP coreC55x DSP core

uu16KB I16KB I --cachecache

uu8KB RAM set8KB RAM set

uu22--way set way set associativeassociative

uu200 MHz200 MHz

D-Cache

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55 66

Hardware Platforms Not Enough!Hardware Platforms Not Enough!

uuHardware platform Hardware platform has to be abstractedhas to be abstracted

uuInterface to the application software is the Interface to the application software is the “API”“API”

uuSoftware layer performs abstraction:Software layer performs abstraction:

ss Programmable cores and memory subsystem “hidden” Programmable cores and memory subsystem “hidden” by RTOS and compilersby RTOS and compilers

ss I/O subsystem with Device DriversI/O subsystem with Device Drivers

ss Network with Network Communication SoftwareNetwork with Network Communication Software

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77

Software PlatformsSoftware Platforms

Output DevicesInput devicesHardware Platform

I OHardware

Software

network

Software Platform

Application SoftwarePlatform API

API

RTO

S

BIOS

Device Drivers Net

wor

kCo

mm

unic

atio

n

Compiler

88

MiddlewareJavaTV, TVPAK, OpenTV, MHP/Java, proprietary ...

Applications

NexperiaNexperia HardwareHardware

Streaming andStreaming andPlatform SoftwarePlatform Software

Ker

nel:

pSO

S, W

in-C

E, J

avaO

S

NexperiaNexperia--DVP SoftwareDVP Software

uuNexperiaNexperia™ ™ --DVP Software ArchitectureDVP Software Architecture

ss Supports multiple Supports multiple OSsOSs and and middleware softwaremiddleware software

ss Abstracts platform functionality via Abstracts platform functionality via consistent APIsconsistent APIs

uuNexperiaNexperia™™--DVP Streaming SoftwareDVP Streaming Software

ss Encapsulates implementation of Encapsulates implementation of streaming media components streaming media components (hardware and software)(hardware and software)

uuNexperiaNexperia™ Platform Software™ Platform Software

ss OS independent device drivers for onOS independent device drivers for on--chip and offchip and off --chip deviceschip devices

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99

HW layerHW layer

SW Platform layer(> 60% of total SW)SW Platform layerSW Platform layer(> 60% of total SW)(> 60% of total SW)

Application Platform layer(≅ 10% of total SW)

Application Platform layerApplication Platform layer((≅ ≅ 10% of total SW)10% of total SW)

µControllers Library

OSEKRTOS

OSEKCOM

I/O drivers & handlers(> 20 configurable modules)

Application Programming Interface

Boot Loader

Sys. Config.

Transport

KWP 2000

CCP

ApplicationSpecificSoftware

Speedom

eterT

achometer

Water tem

p.

Speedom

eterT

achometer

Odom

eter---------------

ApplicationLibraries

Nec78kNec78k HC12HC12HC08HC08 H8S26H8S26 MB90MB90

SW Platform Reuse> 70%

of total SW

SW SW Platform Platform ReuseReuse> 70%> 70%

of total SWof total SW

CustomerLibraries

MOSAIC SW Architecture & Components for Automotive Dashboard and Body Control

1010

PlatformsPlatforms

PlatformDesign -Space

Exploration

PlatformSpecification

Architectural Space

Application Space

Application Instance

Platform Instance

SystemPlatform

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1111

PlatformsPlatforms

uuA platform is, in general, an abstraction that covers a A platform is, in general, an abstraction that covers a

number of possible refinements into a lower level. number of possible refinements into a lower level. For For

every platform, there is a view that is used to map the every platform, there is a view that is used to map the

upper layers of abstraction into the platform and a view upper layers of abstraction into the platform and a view

that is used to define the class of lower level abstractions that is used to define the class of lower level abstractions

implied by the platform. implied by the platform.

1212

PlatformsPlatforms

Platform

Mapping Tools

Platform

Platform stack{

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1313

ApplicationApplication example:example:

uuAutomotive PowerAutomotive Power--Train Control Design: from car manufacturer Train Control Design: from car manufacturer

specs to software design to architecture selection to IC specs to software design to architecture selection to IC implementationimplementation

uuProject in collaboration with Cadence, MagnetiProject in collaboration with Cadence, Magneti--Marelli, ST Marelli, ST

Microelectronics, AccentMicroelectronics, Accent

1414

PowerPower--Train Control SystemTrain Control System

uu Electronic device controlling an internal combustion engine and Electronic device controlling an internal combustion engine and a gearboxa gearbox

uu The goalThe goal

ss offer appropriate driving performance (e.g. torque, comfort, safoffer appropriate driving performance (e.g. torque, comfort, safety)ety)

ss minimize fuel consumption and emissions minimize fuel consumption and emissions

uu Relevant characteristics Relevant characteristics

ss strictly coupled with mechanical partsstrictly coupled with mechanical parts

ss hard realhard real--time constraintstime constraints

ss complex algorithms for controlling fuel injection, spark ignitiocomplex algorithms for controlling fuel injection, spark ignition, throttle position, gear n, throttle position, gear shift … shift …

ss 135,000 lines of C code with no comments135,000 lines of C code with no comments

uu First Step was to reFirst Step was to re--design software with methodology to map into different design software with methodology to map into different

hardware platforms with little effort!hardware platforms with little effort!

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1515

System SpecificationsSystem Specifications

1616

Fast Negat iveForce Transient

min f(D, M f u e l)

τ < τm a x

Force Tracking

Fast Posi t iveForce Transient

S p e e d T r a c k i n g

n = n ( . ) n = n ( . )

Idle & T r a s m O n

.

G > 0 | t >τ

. .G < G

B| B = 1

.G < 0 | t > τ

. .G > G

A

G > 0

G = 0

T > 0

T=0 T=0

( G > 0 ) & ( T > 0 )

T=0

f I( n ) = 0 & G = 0

fI(n,G) > 0

.G = 0 & C = 1

.

G > 0|B = 1

T > 0

T = 0

O U T P U T :

n - E n g i n e S p e e dn - E n g i n e S p e e dFF G G - Generated ForceVV GG - Vehicle Speed - Vehicle Speed

n=n(G)

FG

= 0

Rpm Trackingn= argmin(M

fuel)

Idle

FG

= 0

VG

= VG

(.)

Stopn = 0

FG = 0

Startup

FG = 0

n= .

G > 0G = 0

( n < nm i n

) | ( K = O f f ) n > nstartup

K = S t a r t

(n < nmin ) | ( K = O f f )

FG = FG( G , T , n )FG

= FG( G , T , n )

m a x Dτ < τ

m a x

m i n τ

FG

= FG(G,T,n)

M fuel < M m a x ; D> D m i n

T>0 &G = 0

INPUTS:

G - G a s P e d a lG - G a s P e d a lT - Clutch Pedal & Gear StickT - Clutch Pedal & Gear StickB - Brake PedalB - Brake PedalC - Cruise ControlC - Cruise Control

K - K e y

D - Comfort

fI( n ) = 0

& G = 0

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1717

GoalGoal

uuDevelop guaranteed properties control algorithms for all Develop guaranteed properties control algorithms for all

powerpower--train modestrain modes

uuImplement control strategies on embedded controllers Implement control strategies on embedded controllers

“optimally” with respect to production cost, design time, “optimally” with respect to production cost, design time,

reliability, safetyreliability, safety

1818

Model of PowerModel of Power--traintrain

Manifold

(continuous system)

Engine sub-system

Drive-line

(continuous system with changing dynamics)

Throttle opening angle

Spark timing Torque

Manifold pressure

Clutch Insertion/Release

Gear change

Vehicle Speed

Simple?

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1919

CTSCTS

CTSCTS

Engine and DriveEngine and Drive--lineline

2020

Engine and DriveEngine and Drive--lineline

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2121

Single Cylinder Hybrid ModelSingle Cylinder Hybrid Model

2222

uuMeanMean--Value Model: accurate over a longer time Value Model: accurate over a longer time

windowwindow

ss regulation control problemsregulation control problems

ss low performance transient problemslow performance transient problems

uuHybrid Model: cycle accurateHybrid Model: cycle accurate

ss transient control problems transient control problems

ss stability of delaystability of delay--sensitive control algorithmssensitive control algorithms

ss high performance control algorithmshigh performance control algorithms

Hybrid Model vs MeanHybrid Model vs Mean--Value ModelValue Model

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2323

Output DevicesInput devices

Hardware Platform

I O

Hardware

network

DUAL-CORE

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

DUAL-CORE

Architectural Space (Performance)

Application Space (Features)

PlatformsPlatforms

Platform Instance

Application Instances

System Platform(no ISA)

Platform Design Space Exploration

PlatformSpecification

Platform API

Software Platform


Hardware Platform

I O

Hardware

network

HITACHI

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

HITACHI

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n


Hardware Platform

I O

Hardware

network

ST10

RTO

S

BIOS

Device Drivers

Net

wor

k C

omm

unic

atio

n

ST10

Application Software

Application Software

2424

JanusJanus--PARADES 2000 ArchitecturePARADES 2000 Architecture

Interrupt Based Peripherals

ARM7TDMIA

ARM7TDMIB

Peripheral Bus

High Speed Peripheral Bus

ETU CAN SCI

ADC CLB

DMA Based Peripherals

RAMA

RAMB

FLASHA

FLASHB

XBAR

IO s

ub s

yste

m

IRC

Deb

ug U

nit

IRC

PA

RA

DE

S

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2525

The DualThe Dual--Arm ArchitectureArm Architecture

A symmetric dual processor architecture with a highA symmetric dual processor architecture with a high--bandwidth bandwidth interconnection network among processors, memory, and I/O interconnection network among processors, memory, and I/O subsub--systems systems

uu11 Million Tr., 4% more area than single processor solution but 11 Million Tr., 4% more area than single processor solution but twice the performance on applicationtwice the performance on application

uuMost performing architecture for PowerMost performing architecture for Power--train applications, train applications, designed to be redesigned to be re--used over two generations (3used over two generations (3--4 years cycles) 4 years cycles) of system products or moreof system products or more

uuEntirely designed using the methodology in less than 1 3/4 year Entirely designed using the methodology in less than 1 3/4 year from conception (March 99) to first silicon (Jan 01)from conception (March 99) to first silicon (Jan 01)

uu In production by 2002, shipments to car manufacturer 2003In production by 2002, shipments to car manufacturer 2003

2626

DesignDesign “Practice”“Practice”

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2727

Design Science: Build upon solid foundationsDesign Science: Build upon solid foundations

2828

Design of Communication Media

Design of Function Blocks

Design of Architecture Components

Metropolis Infrastructure• Model of computation• Design methodology

- Abstraction levels- Refinement

• Base tools- Design imports- Simulation

Metropolis: Synthesis/Refinement• Compile-time scheduling of concurrency

• Communication-driven hardware synthesis• Protocol interface generation• Latency insensitive protocols

Metropolis: Analysis• Static timing analysis of reactive systems• Invariant analysis of sequential programs• Refinement verification• Three-valued simulation• Delay estimation using object code

ETROPOLIS (20+ from Academia (UCB,CMU) and Industry (Intel, ST,BMW, Cadence))

Documents

The MARCO/DARPA Gigascale Silicon Executive Advisory Group … · 2001. 10. 11. · Page 3 The MARCO/DARPA Gigascale Silicon Research Center for Design & Test: Form Executive Advisory