The Lockheed hybrid system-A giant step · PDF fileThe Lockheed hybrid system-A giant step ... The flexi bility gained from ... *Hybrid computation at LMCS began in 1966 with a

The Lockheed hybrid system-A giant step

by CONRAD K. BEDIENT and LARRY L. DIKE

Lockheed Missiles and Space Company Sunnyvale, California

INTRODUCTION

View of the future

Gazing into our crystal ball we see you seated at the anal'Og computer preparing for a scheduled hybrid run. You alert the digital computer through your remote display. The digital computer recovers from its permanent files the data and source files associated with your run. These files include a description of your problem in equation format, a description of your problem in block diagram format as mechanized on the analo~ computer, the source hybrid problem, and data decks. After. logging on the system, a complete set of hybrid software is available to you. You may run your program all digital using the equation input and the analog mechanizati'On input to verify pro~r analog implementation of your equations. Using the outputs of the digital simulation ranges of variables may be determined for automatic scaling. The digitally simulated analog mechanization can be used for a patchboard and equipment verification of the actual analog connectives. Static checks may also be generated. U sing the outputs of your digi.tal simulation, you can test the various transfer blocks synthesized 'On the analog computer in a dynamic m'Ode.

Using a set of diagnostic software, you interact with the digital computer until your anal'Og computer is set up and y'Our pr'Oblem is debugged. You now request the system t'O load y'Our pr'Oduction program. You select the opti'Ons 'Of the program y'OU desire, and make y'Our producti'On run. All files and data required f'Or the run are maintained on the mass storage device. When your program is not in execution, it is rolled-'Out onto the mass storage where it may be interrogated and modified as though it were in central memory. All source files may be modified both from re-

mote or by update card decks. The system maintains all these files and makes them available to y'OU on request. The digital computer is rerooted from the customer and it furnishes c'Omputing capability as though it were a power source always responding to y'Our demands. The flexibility gained from the display gives you the feeling 'Of having control of the computer ..

This description indicates the developmental direction of the Hybrid Laboratory at Lockheed Missiles and Space Company (LMSC) located at Sunnyvale, Calif'Ornia. The large digital computer system approach to hybrid computing may permit new flexibility and efficiency that will allow a large digital system to be used economically in hybrid facilities. The only thing that seems to stand in the way of such an operation is the development of the software systems to support such a laboratory.

Problems in hybrid computation

When LMSC's system became operational in June 1967, the primary problems of concern were the problems of modifying a batch processing system to allow for real time computation, the sharing of the central processing unit between tW'O hybrid pr'Oblems, and the writing drivers for the linkage equipment-these pr'Oblems although severe were s'Olved and all'Owed the development 'Of hybrid simulations. The principal step into the future was the development 'Of a remote keyb'Oard entry device. This devel'Opment paved the way for· a glimpse of what a future large hybrid system should be.

In debugging a large hybrid problem, batch processing techniques of debugging may be discarded as virtually useless. A hybrid program is a complicated program which cannot normally be

663

From the collection of the Computer History Museum (www.computerhistory.org)

664 Fall Joint Computer Conference, 1968

halted at a point for examination but must continue its dynamic solution. This complicated flow of information between the continuous running analog computer and the serial digital computer requires mOore refined methods of debugging. The size of the codes being written for simulation is large, since these programs are generally an attack at a large complex system which merged the complications of the predecessor multi-rack analog simulations 'with the large digital simulations. The total problem has become fantastically complicated. Large amounts of data must be handled both flowing from the simulation and into the simulation. Large programs and data decks must be handled. The programmer not only faces the task of solving the problem for a single run but also of controlling the job to allow for the proper sequencing of runs. The program must prepare the results from the runs directly for reports so that the number of runs may be increased without the burden of a large amount of data reduction. The development of hybrid codes is a large effort. The hybrid lab which can ~upport two production hybrid jobs has many hybrid jobs under development. The jobs under development must be able to be sandwiched between production runs utilizing both real or simulated equipment. All the debugging techniques for the hybrid jobs must be available for jobs under development.

Use of the digital ,computer

The digital computer should be used efficiently. However, with hybrid simulations the problem is in the operate condition less than 50 % of the time. Although the time must be scheduled, the very nature of the analog computers in simulation techniques make it impossible to . determine when the digital computer will be required.

Yet, when the digital computer is required, it must be furnished immediately, since the basic cost of the system is the analog equipment. Many systems solve this problem by batch background processing. This procedure may have several appealing merits, but it is probably dangerous. The customer's diversified and dissimilar organization goals and interests, . and the increased costs of equipment to support both batch processing and hybrid simulations plus the complications to the system software may compromise the hybrid requirements. Basically in a hybrid lab containing many analog computers even a large digital computer is not the high cost item in the operation; therefore, the main effort should be to use the

digital computer to increase the efficiency of the analog portion of the overall operation.

These are the problenls that face a large hybrid lab. These problems require programming systems completely beyond the capabilities of those currently furnished by hybrid computer equipITlent vendors.

Reading guide

The material presented in this paper has been organized to accommodate both the reader interested in a general description of the Lockheed Missiles and Space Company (LMSC) Hybrid Computer system and the reader interested in studying the system in detail. For a general description of the main features of the system it is suggested that the sections I through III and VII be read. For those who wish to study the system in detail, Sections IV through VI are provided.

We have gazed into the crystal ball of the future. Now let us take a look at the organization and implementation of the LMSC hybrid computer system.

Hardware description of the LMSC hybrid computer system

The hybrid computing system at Lockheed Missiles and Space Company, * Sunnyvale, California consists of the following:

Control Data 6400 digital computer system Two Comcor Intracoms (linkage equipment) Four Comcor Ci-5000 analog computers.

A block diagram of the syste·m is presented in Figure 1.

Digital computer

Figure 2 shows the organization of the Main Frame. At the center is a large floating point

. processor, the central processing unit (CPU). The multi-register organization of the CPU allows fast execution of Fortran programs. The CPU communicates into 32K of 60 bit memory. Surrounding this central memory are 10 peripheral processors (PPs ). These PPs are identical and operate simultaneously and independently as storedprogram· computers. They act as system control

*Hybrid computation at LMCS began in 1966 with a system comprised of a CDC 3200 digital computer system and two EAI 231R analog computers interfaced by means of a Comcor Intracom.


The Lockheed Hybred System-A Giant Step 665

FIGURE l-LMSC hybrid computer system

G

FIGURE 2-0rganization of main frame

computers and as I/O processors with a 1 microsecond memory cycle time. The PPs have an instruction set which includes integer addition and subtraction but not multiplication and division. These PPs each have 4K of 12 bit memory and

may communicate directly with the large central memory or external equipment over 12 bidirectional data channels.

Table I specifies the peripheral equipment associated with the CDC 6400.

Peripheral

Disk file Card Reader Card Punch Line Printer

2 Magnetic Tape Transports

5 Remote Visual Display Units

Main Display Console

Description

74 million characters 1200 cards per minute 250 cards per min ute 136 characters per line,

1000 lines per min ute 800,556, or 200 BPI, 75 inches

per s'ec. Cathode Ray Tube (CRT) dis

play with 20 lines, 50 characters per line and with typewriter keyboard input

2 display screens for the operator of the digital computer

TABLE J-CDC 6400 peripheral equipment

Linkage equipment

The communication link between the CDC 6400 digital computer and the Ci-5000 analog computers is the Intracom which is shown in block diagram form in Figure 3. The LMSC hybrid computing system has two identical Intracoms with each Intracom normally controlling twO' analog computers. Each Intracom is divided into three main systems: I/O, Interrupt, and Analog. gach of these three systems is connected to its own CDC 6400 data channel for communication with the digital computer.

The I/O system iR subdivided into Rix subsystems as follows:

1. I/O interrupt subsyste'm-which contains 24 priority interrupt lines and logic for handling these priority interrupt lines for processing by the Hybrid Input-Output PP prO'gram.

2. Discrete subsystem-which contains 68 discrete read and 68 discrete write lines.

3. D/ A subsystem-which contains 40 digitaIto-analog converters and 8 independent transfer controls.

4. A/D subsystem-which contains an analogto-digital converter with 32 input channels



(can be expanded to 64) and 8 s·ample/hold controls.

5. P.I.G. subsystem-which contains a precision interval generator (real time counter).

6. Intracom mode subsystem-which contains logic for controlling and sla,ving the modes of the Intracom and the analog computers.

The Interrupt. system contains logic for handling to 24 priority interrupt lines (previously mentioned) for processing by the Hybrid Monitor PP which controls the priority subroutines to be executed.

The Analog system contains the logic necess,ary to Ii~k (interface) the ~nalog computer to the digital computer and allows for the following functions to be accomplished:

• Setting or reading a mode • Setting or reading an address register • Reading a DVM • Setting a Reference Dac • Setting a Potentiometer • Reading status conditions of the analog

console.

Each Intracom also contains a patchable logic group which is comprised of the components listed in Table II.

Component Quantity

General purpo.se counter _____________ 36 (4 hit binary or BCD Up/down preset counter) General purpose flip-flop _____________ 72 Variable delay flops _________________ 12 Logic function switches _ _ _ _ _ _ _ _ _ _ _ _ _ 24 Lamp drivers ______________________ 48 System clock (100KC) ______________ 1 Nand gates ________________________ 228 Inverters __________________________ 72

TABLE II-Intracom patchable logic

Analog computer

The analog computing elements aresoUd state and operate over the range of ±100 V. Solid-state

FIGURE 3-Ci-5000 intracom system

DIOITAL COMPUTER

DATA CIlAJfNELS

DIGITAL COMPUTER IIDIULATOR

~

~

r

ANALOG : ANALOG CH4NNELI CONTROL CON- I SUJi-TROLLER: SYBTEM

I

INTERRUPT CH4NNEL CONTROLLER

I/o CH4NNEL COICTROLLER

TO/FROM OTHER INTRACOM

r----- TO/FROM ANALOG COMPUTERS

I h MODE 1'I:1T PAJIII!L

~

I PIG

~r-r--- TJ:IT PANEL

I hr D/A TEIT PANEL

I hf

AID TEST PANEL

INTERRUPT stJlISYSTI:M

MODE SUJIIIYIITJ:M

PUC_OK INTERVAL GENERATOR

DllCUTE IUJlllYllTJ:M

D/A CONVE .. ON IVIIIIYftI:M

TRAJIIntl COIftW)L IUBlYSTJ:II

AID CONVERSDN stJB8YSTEM

r-

r-

I-

-

PATCHABLE LOOIC. r- CONTROL PAJIII!L.

AND r-----PATCHJIOAJID

TO ANALOG COMPUTERS

TO/FROM ANALOG COMPUTERS

FROM ANALOG CO MPUTEJII

PROM 0'I1IS. JllTRACOM


The LO'ckheed Hybred System-A Giant Step 667

switching and digital IO'gic circuitry is used to obtain high-speed cO'mputing operation. Each O'f the Ci-5000 analog computers is comprised of the components listed. in Table III.

Component Quantity

Summing amplifiers _________________ 60 Integrating and/or summing amplifiers_ 60 Inverting amplifiers _________________ 16 ServO' set potentiometers _____________ 144 Digital attenuators (HODADS) ______ 48 Three terminal manual potentiO'meters _ 32 MuLtipliers _________________________ 66

Resolvers sin-cos __________________________ 3 multipliers ____________________ -:-__ 24

Card set function generators _________ 22 Card set surface generator ___ ~_______ 1 D/ A switches ______________________ 30 Comparators _______________________ 30 Relays ____________________________ 24 Function switches __________________ 16· Feedback limiters ___________________ 30

Patchable logic Up-down counters (4 bit) _________ 8 or general purpose flip-flO'Ps ________ 32 Counters (4 bit) _________________ 4 'Shift registers (4 bit) ____________ 4 Delay flops _______________________ 9 Inverters ________________________ 24 Nand Gates ______________________ 48 Cycle counter _____________________ 1 Iterative clocks ___________________ 3

DAC output trunk patchboard terminations _____________________ 20

ADC input trunk patchboard terminatiO'ns _____________________ 16

Recorders __________________________ 3 OscilloSCO'pe ___________________ "":-___ 1

TABLE III-Gi-5000 analog computer components

Hybrid computer system and software capability

The operating system fO'r the' LM:SC hybrid cO'mputer system is CLASH, * a modified and aug-

*The acronym "CLASH" originated by combining the initials of the companies who supplied programming personnel to the LMSC software development: Control Data C:>rporation, Lockheed Missiles and Space Company, Astrodata/COMCOR, Spectrodata. (The "H" originates from Hybrid).

mented version of SCOPE 2.0 which is a standard operating system for' CDC 6400/6600 digital computers.

A measure O'f the effectiveness of the O'pe'rating system is its ability to handle more than one prO'blem and its ability to immediately process background digital wO'rk when there is a break in the hybrid action. An effective display system greatly simplifies prO'gram debugging plus allowing on-line debugging without sacrificing system efficiency. Extensive debugging can be dO'ne O'n a hybrid program utilizing the display system without the digital program being resident in core storage. Programs can be developed rapidly since their development is, in Fortran language with a complete set of library routines allowing flexible communicatiO'n to the linkage and analog equipment. The use O'f the PPs to augment the standard system in recO'rding of data and driving O'f special interface or simulatiO'n equipment enhances the processing capability O'f the system. Continued expansion of the debugging capabilities can take place since these capabilities are largely hnplemented 'On PPs which dO' not reduce the basic computing powe'r of the CPU.

Selection of the digital computer

The main criteriO'n fO'r selection of the digital computer and the design .of the software' system was the digital computer's capability of rapidly executing a scientific "Fortran" prO' gram at high interrupt frequencies, with low digital computer overhead for priority interrupt processing.

The central processO'r within the CDC 6400 digital cO'mputer has the capability of transferring between two. programs by use of an exchange jump cO'mmand. This command can either be issued by the CPU itself, or by a PP. By executing this command, the CPU can be switched between two programs at a very rapid rate. By utilizing this capability in a priority interrupt scheme, LMSC has effected high speed frequency computation O'f the digital portion of a hybrid program at low system overhead.

Parallel computation and 1/0

A powerful feature of the computer is its multipr'Ocessor O'rganizatiO'n. The CPU, with its high speed 60 bit floating point arithmetic, is used for computation. The PPs are used fO'r control and transfer of data in and .out O'f the digital computer. This multi-prO'cessing structure has been implemented in the hybrid system to aIlo'w


008 Fall JO'int CO'mputer CO'nference, 1968

computation within the CPU to' proceed simultaneously with input/output O'f data via the PP (parallel computatiO'n and I/O). This capability alO'ng with the capability of rapidly switching the CPU between priority computatiO'nal levels, allows extremely effective use Oof the CPU.

A computatiO'nal frame normally includes input O'f data from the analO'g cO'mputer, cQmputatiO'n O'n that data, and output O'f the data back to' the analog computer. Two of these functions, the input and output of data, can be dO'ne effectively with PPs. The computatiO'nal portion of the cycle must of course be done by the floating point CPU. If the inputting of data frOom the analog computer is initiated completely without interventiO'n O'f the CPU, then time normally used fO'r cO'ntrol of the I/O channels in a standard system is saved. By assigning a PP to each jO'b, prO'cessing capability can also. be increased. E-ach O'f these PPs can be performing input/O'utput in parallel with one another and with the cO'mputatiO'n being performed within the CPU.

Figure 4 shows the tJ.tilization O'f the GPU and the PPs when we have two hybrid jobs in execution. PrO'gram A and PrO'gram B each have an individual PP, dedicated to the input and O'utput of data, associated with them. If we look at the operatiO'n O'f the processors O'n these programs, we see parallel CPU computatiO'n and I/O transmission. For example between 1 and 2 millisecO'nds both PPs are transferring data while the CPU is processing the highest priO'rity prO'gram. This assignment O'f PPs to' each hybrid jO'b alsO' insures that the computatiO'n will occur sQmeplace within the required frame time. TherefO're if outputs can always be updated at the next frame time, we can guarantee uniform performa.nce

CPU CPU CPU CPU cPU cpu CPU n n n n n n n P ~§J kr§J M §J t!£J§I t!£J§I kJ§J kl @ 11 g A PBOQIIAII A INTE1I1IUPl' 1 FllEQUENCY lOG CPS DUTY CYCLE 1 MILLIIECOND

:. ~~ • @U] n ~ @ ~ ~

PROOIIAII A INTE1I1IUPl' 2 FllEQUENCY 110 CPS DUTY CYCLE' MlLLIIECONDII

CPU CPu nn ~ §J P ~ l!§l Xl §I 10 @

11 g B PROOIIAII B INTElIlIUPT 1 FlIEQUENCY U5 CPS DUTY CYCLE 2 MILLISECONDS

11 CPU

: ~ n A§] §] PIIOGIIAII B INTElIlIUPT 2 FlIEQUENCY 25 CPS DUTY CYCLE 5 MILUSECOND8

CPU CPU CPU ~~LnL-__________________ LnL-______ ~~=Pu~n~

10 15 20

TDIE MILS

FIGURE 4-Parallel comput.ation and I/O

with the job O'perating by itself O'r operating in cO'ncert with the other hybrid jO'b.

The multi-prO'cessing apprO'ach also leaves more time available for the CPU. FO'r example, if we loO'k at the highest priO'rity interrupt, PrO'gram A-if the CPU was required to contrQI the inputs and outputs to the linkage equipment, it WO'uid be required 60 % O'f the time rather than the 20 % shown. This would mean that there would nOot be enO'ugh CPU time to' allQw both hybrid jOobs to run simultaneously.

Automatic roll-out

Continued emphasis in the LMSC hybrid system has been placed O'n the utilizatiO'n O'f the digital cOomputer's small memO'ry. This has resulted in majO'r modifications to' the standard CDC 6400 operating system and major use to be made of the mass storage device. One new feature added to the LMSC system is the automatic rO'll-in and rO'll-Oout capability. This automatic rO'll-out fe'ature is further augmented by the capability O'f using all the debugging features of the display system while a program is in the rolled-Out condition. Whenever a prO'gram cO'mes to' a point where it can no IO'nger cO'ntinue withO'ut prO'grammer assistance, it is automatically rO'lled-Out O'ntO' the mass storage device. As soO'n as the prO'grammer has input to the display device, the system auto-matically rO'lls the job in and it cO'ntinues execution. Rolling hybrid jobs in will automatically roll-out background digital jO'bs thereby immediately making central memory available. However, if two hybrid jobs conflict fO'r 'central memory, the requesting hybrid job is delayed until the amount O'f central memO'ry requested is available. Since hybrid jO'bs are not in executiO'n a large percentage of the time, automatic rO'll-in and roll-out has greatly increased the hybrid system's efficiency.

The display system

The heart of the usability of the LMSC hybrid system is the display system. The hardware of the display syste1m inel udes a controller with five remote visual display units which allow input via a typewriter type keyboard. Each of the remote display units has the capability of displaying 1,000 characters O'n a 50 character by 20 line screen. Regeneration of data on the displays is carried Oout in the display system's controller by using line memories.; thus, the digital computer is only required when an update of the



display is to be made. A peripheral processor, PP no. 6, drives all five displays in a time shared ~anner. A small amount of central memory is also used at control point 6. The display system software consists of a display monitor program, which controls the overall operation of the display syste·m, and a number of tasks which have been implemented to operate under the system. The number of tasks will be increased as new techniques are developed. The display monitor allows for five tasks to be in operation at each of th.e display consoles. The partial results of the five tasks are maintained on the disk for each console; therefore, requests made in one task are not lost when the operator temporarily switches to another task. The tasks available on a display include display directory, job control, variable display and modification, program I/O, source mo.dification, hybrid utility, day file display, preventive maintenance, and engineering aid.

Job contro.l

The jo.b co.ntrol task allows general control over the operating system. All of the features which are available at the main console display are available from this task. Co.ntrol of a program is easily and effectively implemented since the operating system itself was designed to be controlled from a display. This task includes:

• Display of me·mory in octal o.r mnemonic format

• Entering of control cards • Advancing of co.ntrol cards that have been

read in with the job • Breakpointing through a program • Requesting the output files to. be listed

Variable display and modification

The variable display and mo.dification task allows the programmer to display and modify variables by their Fortran name. The symbol table is output by the compiler and is included in the binary deck of the program. When the loader is loading the pro'gram, the symbol table is processed and relo.cated while the prngram and a symbol file is written to. the disk. This symbol file is used by the variable display task to allow any named Fortran variable to. be called up fro.m the remote display. Variables may be displayed in octal, integer, or floating point formats. Simple mathematical functions a:re ava.ilable including add, sub-

tract, multiply, divide, sine, cnsine, and log. Variables may be displayed and modified when the program is in central memory and also when the program is rolled-out on the mass storage device. This latter feature allows the programmer to do extensive debugging without utilizing central memory.

Program Input/Output

The program input/output task allows the programmer to communicate with the remote display as though it were a standard piece of peripheral equipment. In a Fortran program he may make read or write statements which when executed will write out results or re'ad in control information to nr frnm the display. This is the normal way in which program control is maintained in LMSC's hybrid system. The programmer normally selects most of his options by reading in information using the program input/o.utput display task. Whenever a request to. read is made to the display, the display system automatically ro.lls the pro.gram nut onto the mass storage device. When the requested input has been typed in by the progralnmer / operator the display system will roll the program back into core and the CPU will continue execution of the program following the read statem,ent.

Source modification

This task allnws the programmer to make sm'all modifications to his source programs, both data decks and prngram decks. Modificatio.ns to these decks are made by using insert, replace, and delete statements. This feature allows minor program changes without requiring the resubmittal of the program decks.

Hybrid utility

The hybrid utility task displays inform·ation required by the Hybrid Monitor and also results coming from the Hybrid Monitor. The task allo.ws the programmer to display the frequency of each priority interrupt line, the expected length of execution of each priority interrupt line, the actual length of execution for each priority interrupt line, and the number of priority interrupts that have been processed on each interrupt line. Other information which can be displayed includes the exchange package sets for each priority level in the hybrid problem.



Day file

When system errors occur which are critical to the programmer/operator, they are output to him on a display in the form of day file messages. Day file mess·ages include such information as potentiometer did not set, equipment is not in a ready cO'ndition, etc. The messages for all jobs alsO' appear on the main operator display console to inform the digital operator of the current status of the digital computer. The messages which appear on the remote display apply only to the job to which the particular remote display is assigned. .

Preventive maintenance

Preventive maintenance (PM) for the analog computer and Intracom is also controlled using the display system. The preventive maintenance task was implemented to' allow the operation of a set of mainten.ance routines, by technicians who are not familiar with the operation of digital compute~r equipment. When the preventive maintenance task is selected, the directory of the various PM tests available is displayed. The technician may select one of the tests by typing in a two digit number associated with that test by the directory. When the particular test is loaded, the reminder of what setup must be made on the equipment before the test can be run are displayed, for example, what patchboards must be mounted on the equipment, a reminder to place the equipment in digital computer control, or whatever is required for the test.

Engineering aid

The engineering aid task is basically a maintenance support program. This task is also useful when connecting new or additional equipment to the hybrid system. Since the LMSC hybrid system exists in an analysis., design, and evaluation environment, it is periodically required to connect to various pieces of hardware not normally considered as part of the hybrid system. The engineering aid task allows scope type debugging of a piece of equipment, where the instructions to be executed may be keyed in directly on the remote display by the engineer debugging the experimental equipment. The display system uses an additional PP to execute these tests. This capability has allowed new pieces of equipment to be checked without interfering with hybrid system's operation.

Software organization

The software for the digital computer is organized as shown in Figure 5. First we will discuss the organization of central memory as used by the central processing unit (CPU). Then we will discuss the as,signments of the peripheral processing units (PPs) in the system. Finally we will describe how a job is processed by the system.

Organization of central memory

The central memory is divided into two main areas: resident and program. Within the resident are seven control areas for 7 digital programs. These control areas are Called control points. Storage in the program area may be assigned to the control points. An area immediately following the central memory resident is assigned to control point 1; control point 2 immediately follows control point 1 and so forth up through control point 6. The top portion of memory is as..; signed to control point 7. As storage is required at a control point, higher numbered control points are moved upward in memory.

Hybrid control points

Two contrO'I points, numbe,red 1 and 7, are used fO'r hybrid jobs. This assignment is made in order that their storage areas need not be moved as new jobs are entered or deleted from the system.

System control points

Two control points, numbered 2 and 3, are normally used by the system. Control point 2

IIYl\lUD

CTPT7

AVAIL CORE

DISPLAY

CTPT8

NON-IlEAL nNE

CTPTS

NON-REAL TIllE

CTPT4

OUTPUT

CT PT 3

READ

CTPT2

HYBRID

CT PTl

FIGURE 5-Software system organization

ANALOG CONTROL

A-D D-A DISCRETE 10 INTERRUPT

CPU INTERRUPT

CPU INTERRUPT

10 INTERRUPT DIIICRETJ: A-D D-A

ANALOG CONTROL



(READ) contains the software which processes inputs from the card reader. Control point 3 (OUTPUT) contains the software which processes all line printer and card punch files.

N on-hybrid control points

Two control' points, numbered 4 and 5, are used for non-hybrid and non-real time jobs, including those of the straight digital or analog setup type which do not require real time response.

Display control points

A control point, numbered 6, is used to drive the remote display syste'm. This control point is utilized to satisfy the CPU requirements of the display systelTI.

Peripheral processor assignments in the system

Four of the PPs have permanent assignments while the others (6) are termed pool processors. Processors with permanent system assignment

, are loaded when the digital system is initialized and continually perform their assigned functions. Pool processors are assigned to perform certain tasks which may be either system tasks or input/ output tasks. On completion of the task, they are returned to the pool.

\

Processors with permanent system assignment

The Montior Program (MTR) resides in PPo. This monitor program coordinates the operation of the entire hybrid system. It controls the assignment of central memory, coordinates the utilization of the digital computer's data channels by the other PPs, assigns tasks to the pool PPs, and controls the switching of the CPU between the control points of the system by passing exchange jump requests to the hybrid monitor in PP8.

The Dynamic System Display Program (DSD) in PP9 maintains a dynamic system display of all jobs on the main console that are in progress in the system. The CDC 6400 digital computer is unique in the fact that it has no hardware console, either for maintehance or for controlling its programming system. Therefore all of the control of the system must be exercised through a programmable Cathode Ray Tube (CRT') typewriter dis,play.

The DIS 211 progTam in PP6 in conjunction

with the central processor at control point 6 drives the 5 remote displays.

The Hybrid Monitor Program (HYP) resides in PP8. Its function is to control the CPU. It directly switches the CPU real time computations and accepts requests from the MTR program in PPo for switching it between control points when real time requirements are satisfied.

Pool processors

Pool' processors perform most system-tasks and process input/output requests for the CPU. Two pool processor programs HIO and AIO are shown in Figure 5 and discussed below to em-,phasize the fact that they perform communication with the linkage equipment.

The Hybrid Input-Output program (HIO) is loaded when a hybrid program goes into real time and remains resident throughout the real time portion of the program. It processes communication requests as initiated by the CPU or the priority interrupt system in the linkage equipment. These requests are generated by a library of Fortran callable subroutines. At completion of the re,al time portion of the hybrid program the PP is returned to the pool.

The Analog Input-Output (AIO) routine processes all requests for non-real time setup of the analog ,computers. This program proces,ses a buffer of requests generated for it by Fortran callable CPU subroutines. On completion, the PP is returned to the pool.

Job processing

Figure 6 shows the normal flow of jobs in the system. Jobs are entered into the syste'm through the READ control point (2). A PP is periodically

r----------, I READ I I CONTROL POINT : I 2

I : I f--+--f I I I I L _________ J

CONTROL POlNT 1

CONTROL POlNT 1

OUTPUT

CONTROL POINT 3

L,","uoj CARDS

~ ~

OUTPUT

INPUT

NON-REAL TIME JOB

CONTROL POlNT

• CONTROL POlNT

5

FIGURE 6-Job flow



assigned to the READ control point to see if any jobs have been placed in the card reader. If a job has been placed in the card reader the entire deck is read in and placed on the mass storage device. This file of data is then entered into the system directory as an input file with the priority that appeared on the job card. Control points which process jobs are; control points 1 and 7 for hybrid jobs, and control points 4 and 5 for non-hybrid jobs. Determination of whether a job is a hybrid job or not is made from its priority. Jobs with a priority equal to or greater than 60 are assigned to the hybrid control points (1 and 7) and jobs with priorities less than 60 are assigned to non-hybrid control points (4 and 5). Control points which are idle periodically have a PP assigned to the'm to determine whether they can accept a job at the control point. This PP scans the mass storage directory looking for input jobs. The hybrid control points (1 and 7) look for input jobs with priorities equal to or greater than 60 while control points 4 and 5 look for priorities of 60 or less. If an input file is found and the core storage required is less than the core storage currently available, the job is assigned to the control joint and PPs are called up to begin operations as indicated by the job's control cards.

While the job is in execution it may generate punched cards or listable output. This data are written on the mass storage device. When the job is completed, or under control of the remote display syste'm, these files are tagged in the system directories as output files, and are released from the control point at which they were generated. The Output control point, control point 3, processes all of these listable and punched files. Periodically a PP is assigned to the Output control point" in order to search the system file directories for files which are designated as output files. When output files are found, they are printed or punched.

Program organization

The desire to run two hybrid simulations and to be able to do other digital background processing places emphasis on efficient utilization of the digital computer's small 32K core memory. Since the hybrid programs under development have an extended life of operation, they must be developed in such a way as to efficiently utilize core storage. The use of the remote display as the control device in a hybrid program also affects

the program organization. Jobs are loaded into the system and remain in operation on the system throughout the entire work shift. When a hybrid program is to be activated instructions are given to the digital computer through the remote display. A hybrid program therefore must be divided into a number of phases with these phases organized into overlays for more effective core utilization (See Figure 7). Since the real time overlay of a hybrid program is the largest overlay, emphasis must be placed on keeping this overlay as small as possible. This is done by insuring that there are no Fortran input/output statements, analog setup statements, or any other coding which is not absolutely nece'Ssary during the hybrid program's real time phase. Data which are required for the real time overlay preprocessed in the program initialization overlay so. that they can be handled in a binary format during the teal time operation. Data then are generated by the re'al time overlay and written to the mass storage device where they are-later read and processed by the report generation overlay. By not using read and write statements, the large amount of core storage that is used by Fortran run time I/O is conserved and made available

MAIN PROORAM

COMMON STORAGE

OVERLA.Y LOADI!«l

C PI AU .R R R 0 m NP E U E N OI A A N P T GT I LA L 0 R HI ION C R 0 AA ! G D '1' 0 '1' L ML i I N

I 1ST M T G

Z . E E E R E A iTS 0 N T i T L E I R 0 A H T '- I

0 N

FIGURE 7-Storage allocation for main program overlays


to the real time portion of the hybrid program. The main pro'gram cO'ntains co.mmO'n declara

tions fO'r data that must be cO'mmO'n to all overlays, allowing cO'mmunication between them. The main program alsO' cO'ntains calls to the overlay loader fO'r IO'ading the cO'ntrol O'verlay and O'ther overlays which the cO'ntrO'I O'verlay may request (See Figure 8) .

PrO'grams are organized so that they use the cO'ntrO'I O'verlay fO'r interrogating the remO'te displayas to' the next O'peration which is expected. The display task used fO'r this interrO'gation is the I/O task. This task allows the prO'grammer to communicate directly with the display as though it were a peripheral device. Thus, with FO'rtran read and write statements, he can read and write cO'ntrol informatiO'n which determine,s what part O'f the program is to be entered next.

The contrO'I overlay performs a read instructiO'n to' the remote display. The remO'te display system has been programmed SO' that, when a read command is given to' it, it will automatically roll the program out ontO' the mass storage device which makes the core storage used by the hybrid program available to the system. When the hybrid programmer has typed in the contrO'I information defining what he wishes to dO' next, the remote display system rolls the pro,gram back intO' central memO'ry and cO'ntinues execution of the contrO'I O'verlay which then determines from the parameters typed in what the O'perator has requested.

The control overlay nO'w trans·fers control to' the main program along with the prO'per parameters set fO'r IO'ading the overlay requested. When executiO'n of the requested overlay is finished, control returns to the main program. The main program then relO'ads the control o.verlay and the display is read again. At this point the O'perator usually needs some time to analyze the results O',f his previO'us request. Since the hybrid pro.gram is rolled-O'ut at this point, the system can immediately begin executing waiting jO'bs and cO'ntinues to' do. so until the hybrid programmer is prepared to continue.

At this point it must be emphasized that the structure we are talking abO'ut is nO't explicitly defined in the O'perating system. Rather it is merely a structure for program O'rganization which has been found to be effective in allowing maximum use of the display as a control device and which emphasizes the efficient use of core storage.


ENTER J

WAD OONTROL OVERlAY

READ

DISPlAY

OPERATOR

ENTERS CORl'ROL

INFORMATION

Program Rolled ... out

CONTROL OVERLAY DETEHMINES FROM EXTERED INFORMATION vlHAT OVERLA.Y IS NEEDED

,"'"

EXIT

TO MAIN PHOO •. WITH PARAJmrERS FOR OlERLAY ':;i

WAD AND EXECUTE ~UESTED (JIERIAY

Em TO MAIN PROl.

END

FIGURE 8-Flow·diagram of overlay loading and execution



Several of the typical overlays that may be .requested by the control overlay will now be briefly described. The initialization overlay is requested to initialize the program and to proces1s all of the input data cards.

The analog set-up and test overlay is requested to set the potentiometers according to data that have been previously processed in the program initialization overlay. This overlay may initiate a number of tests to calibrate and/or dynamic test the analog mechanization.

The control overlay may request a hybrid program run or possibly a sequence of runs. If a single run is requested, the real time overlay would be loaded into central memory from the mass storage device, the simulation would be executed, and then the control overlay would be reloaded. If a sequence of runs is to be made, normally the hybrid program would contain a run control overlay which would vary parameters in the digital portion of the simulation, change para,meter values on the analog computer portion of the simUlation, and perform other nonreal time functions between the real time phases.

The report generation overlay is requested to recover the data recorded on the mass storage device during the e,xecutiO'n of the real time overlay. It generates listings and plots of data which has been gathered from one or more runs.

Communication with the linkage and analog equipment

In describing the LMSC hybrid computer system, we briefly discussed the communication linkage equipment (Intracom) connecting the digital computer and the analO'g cO'mputers (see Figure 3). AlsO' in describing the software organization for the digital computer (see Figure 5), we briefly discussed the two pool PP program, HIO and AIO, which are used in communicating with the Intracom. In this and subsequent sectiO'ns O'f this paper, we will describe in detail the important features of this communication both from the standpoint of the Intracom's hardware and the system sO'ftware programs.

To facilitate hardware design and system SO'ftware development, communication between the digital cO'mputer and the Intracom was grO'uped into the three categories: priority interrupt processing, Hybrid Input-Output (HIO), and AnalO'g Input-Output (AIO).

The first category, priO'rity interrupt prO'cessing, was desired in order that digital programs,

called priority subroutines, with varying priorities might be initiated by logic signals from sO'urces external to the digital computer.

The second category, Hybrid Input-Output, was desired in order that values of analog or digital prO'gram variables might be input/O'utput (I/O) at a fast rate to O'r from the analog cO'mputer, allO'wing for the possibility that the I/O defined in a predetermined pattern, might be initiated by a. logic signal from sO'urces external to' the digital computer. AlsO' the second category was desired to allow the digital computer to' read or write IO'gic signals (Le., discrete lines) to O'r from the IntracO'm, to' control a precision interval generator, and to control the mode of the Intracom.

The third categO'ry, AnalO'g Input-Output, was desired in order that the digital computer might perform initialization, checking, and monitoring of variO'us components within the· analO'g computer. This _ category gives the same capability to' the digital cO'mputer as the analog prO'grammer has with the manual keyboard O'n the analog computer.

The first twO' categO'ries are closely related in that sensing of logic signals O'ccurring externally to' the digital cO'mputer is necessary and alsO' due to' the desirability and/O'r necessity of having bO'th I/O patterns and priO'rity subrO'utines initiated by the same logic signal. Our attention in this section will be primarily fO'cused on real time priority interrupt processing.

Priority interrupt processing

Interrupt capability

The CDC 6400 digital computer does not have a hard-wired priority interrupt capability; hO'wever, each O'f its PPs has the capability of commanding the CPU to exchange its registers with 16 central memory words. This exchange includes the transfer O'f all O'f the control, index, address, and arithmetic registers. Thus, by formatting in central memory exchange packages for each priority subroutine that is to be initiated by a priority -interrupt signal, it is possible to' rapidly -switch the CPU between priority subroutines frO'm a PP by executing an exchange jump command. This exchanging of registers requires less than three microseconds of CPU time.

By installing hardware in the Intracom which senses the O'ccurrence of priority interrupts, determines the highest priority interrupt line active, and transmits this infO'rmation upon request



by a PP to a data channel which is co.nnected to the digital computer the ability to detect and respond to external interrupt signals can be realized by the CDC 6400.

By designing the Intracom priority interrupt hardware such that two separate but identical circuits (priority trees) may determine the highest priority interrupt active, installing a switch to. transfer the interrupt signal from one circuit to the other, and connecting the o.utput o.f each circuit to a separate data channel and PP, computation and input/output can be performed in parallel.

Peripheral proceSso.rs associated with interrupt processing

The digital portion of the detectio.n and response to external interrupt signals is handled by the Hybrid Monitor (HYP) and the Hybrid Input-Output (HIO) peripheral pro.cessor pro.grams.

Hybrid monitor

It contro.ls the o.peratio.n of the CPU and also determines which priority subroutines should be initiated in response to priority interrupts detected by it. It is comprised of a PP program, HYP, which is loaded at dead start time and a CPU program which is part of the central memory' resident.

When no prio.rity subroutines are active o.r waiting to be processed, the PP program honors exchange requests from the system monitor to execute background jobs and maintains the jo.b stack. Perio.dically the Hybrid Monitor checks to see if a request to. initialize a hybrid program has been received. When such a request is received, it will read from central memory resident information necessary to set up and to execute the corresPo.nding hybrid program.

The PP program (HYP) detects the occurrence of priority interrupts and activates the CPU when priority subroutines are to be executed. The HYP program periodically requests from the Intracom the highest priority interrupt line active and monito.rs the priority subro.utine currently being pro.cessed by the CPU. Then based upon setup information which supplies the relative priority of the interrupt initiated priority subroutines determines whether an exchange jump to a higher prio:vity subroutine than the one currently being executed i,s required. If an

exchange jump is made to a higher prio.rity subroutine, the Hybrid Monitor will mo.nitor the execution time of this priority subroutine to insure that it does not exceed the programs' allotted time as specified by setup data. If the execution time becomes larger than that specified, the monitor will abort that ~particular hybrid program.

Hybrid input-output

The HIO peripheral processor program proc..: esses analog to digital, digital to analog, and discrete information to and from the Intraco.m. It Io.oks both to the central memo.ry fo.r requests coming from the CPU and to the Intracom's interrupt structure for commands to initiate transfer of data to and from the Intracom and/o.r analog computer.

The HIO program requests' fro,m the Intracom the highest priority interrupt activated and determines, based upon setup info.rmation, whether or not an I/O pattern is associated with that particular priority interrupt. If an I/O pattern is associated with that interrupt, then the communication codes of the I/O pattern are executed and the transfer of data is accomplished.

If both an I/O pattern and a prio.rity subroutine are associated with a priority interrupt (leading edge I/O), the pattern definition is completely executed by HIO and then a function code is sent by HIO to the Intracom which transfers the interrupt to the hybrid priority tree and thus to the Hybrid Monitor.

Hybrid program organizatio.n

To obtain an understanding of how priority interrupt processing is implemented, the organization and various phases of a hybrid program will now be discussed. A hybrid program is o.rganized with a main program, no.n-priority subro.utines to. the. main program, prio.rity subro.utines, and subroutines to the priority subroutines. The typical organization fo.r a hybrid pro'gram is shown in Figure 9.

In the following paragraphs we will present a step by step explanation o.f the main program structure of a hybrid program as it relates to priority interrupt proces,sing (see Figure 10). Information deemed necess'ary to clarify the description will be inserted where needed.

The main program of a hybrid program initiates and controls the various program phases and calls into executio.n non-priority subroutines.



JOB Card

HooK-- control card

Hook data cards

Ha1n program

Hon-priority subrout1Des to IIa1n Program

Priority subrout:lDes

Subroutines to the Priority Subroutines END

FIGURE 9-Hybrid program organization

Analog set-up pbaae

Pre-real t1ae pbase

. Real u.s pbase

EXTERNAL priority subrOllt1lle mae CALL CONOOJE CALL SETPOT .:ALL lUlE CALL READ

CALL SETUPFL (I/O patte.'n detJ.n1t1ons) CALL STRl'f "r (b0d7 ot p.·~tern) CALL WDACS CALL HADCS CALL ENDPAT CALL CONNECT CALL RLTIHE CALL WAlT

(Priority subrOllt1lles, I/O patterns, and cOllib1nat1on I/O pattern and pricr1t;r subrOlltmes which are i.merrupt initiated are in operation

during real time UDder the cont.rol or the aybrid Monitor and/or tbe HIO peripheral processor routines)

SUBIDJ'1'IHE Haae

(1D1t1al1.zatiOO code) (I/o pattern detJ.n1tions)

CALL PAS'l'P1I1 (real t1ae code) am . CALL REI&SE (poet-real tiM UlalJs1s of data obtd.Ded during real t.1-.) am

FIGURE lO-Main program structure

The main program and its nOon-priority subroutines execute the analog set-up, pre-real time, and post-real time phas,es of a hybrid program.

SETUPFL

In general one of the first executable statements called in the main prO' gram is SET'UPFL. This system subroutine performs the initialization needed to enable a hybrid program to cO'mmunicate thrO'ugh the HIO peripheral processor program via a data channel to the IntracO'm. The HIO circular buffer is initialized to' enable CPUPP cO'mmunicatiO'n. Also the Intracom priority interrupt subsystem is initialized such that all

interrupts are cleared and disabled and such that all interrupt masks are cleared.

I/O patterns

The main program or the initialization code of a priority subroutine generates the I/O patterns during the pre-re,al time phase and they are executed when an associated priority interrupt signal occurs during the real time phase O'r when called from the main prO' gram, a priO'rity subrO'utine, a nOon-priO'rity subroutine, or by another I/O pattern. An I/O pattern is structured as shown in Figure 10. The pattern defines a sequence of computer instructiO'ns which perform input and output to' the Intracom and/ or the analO'g computer. A CALL STRTPAT statement must be the first statement of the pattern definitiO'n. This statement specifies a number (from 1to 63) by which the pattern can be referenced in the hybrid program, and it infOorms the system that what is to follow is to' be assO'ciated with this specified identification number. The CALL E,NDPAT statement indicates to' the system that the pattern definition is to' be terminated. The body of the pattern definition consists of calls to system communication subrOoutines such as GALL RADGS, analog-to-digital cO'nversiO'n, and CALL WDAGS, digital-to-analOog conversiOon. The s:ystem subroutines called in the body of the definition cause instructions to be generated for the HIO peripheral processor program. These 1/ patterns are resident in and executed from the PP which contains the ,HIO program.

Priority subroutines

A priority subroutine is a subroutine located in central memory which is to' be executed only during the real time phas.e Oof a hybrid prO' gram and is nO'rmally initiated by the occurrence O'f a priority interrupt signal. The priority subroutine is structured according to the special format shown in Figure 11. The initialization cO'de is executed in the pre-real time phas,e. The real time cO'de however, is executed in the real time pha,se due to' the occurrence Oof a priOority interrupt to' which the priority subroutine is associated.

Priority levels

Each I/O pattern, priority subroutine, or com-



(initialization code and definition of I/O patterDs)

(real t:t.e code)

SUBROU'l'DlE .. CALL STRl'PAT (bodT of patten) CA.LL ENDPA'l' CAlL WDACS

•

CALL SHSK: CALL FASTPlIl

· qA.LL SCALIN

· CALL SCAIDUT

· DID

FIGURE ll-Priority subroutine structure

bination I/O pattern and priority subroutine (leading edge I/O) is assigned a priority level on the basis of its frequency of occurrence or relative importance. A priority .interrupt line is then aSisigned to' each of these priority levels with the interrupt line with the smallest number being assigned to the highest priority level.

Hook and hook data

For each priority interrupt line that has been associated with a priority subroutine, a Hook data card which contains the interrupt line number, maximum frequency O'f occurrence, and the maximum CPU execution time needed to process the corresponding priority subrO'utine is inserted in the program deck. The Hook system program is called by a HOOK control card at the beginning of a hybrid program deck. Using the data cards the Hook program informs the Hybrid Monitor as to which interrupts are to be used to initiate associated priority subroutines., the maximum frequencies of occurrence, and the maximum CPU execution times. Also the percentage of total CPU time needed per second to process each priority subroutine is calculated from the information on the Hook data cards and placed in the output file.

CONNECT

In the pre-real time phase of a hybrid program, calls are made to the CONNECT system

program which communicates to the HYP and to the HIO peripheral processor programs what should take place in response to the occurrence of the various priority interrupt signals. A separate CALL CONNECT statement must be made for each priority interrupt which is to be used by the hybrid program. The calling sequence of the CONNECT statement specifies the Intracom to be used, the interrupt line number, the I/O pattern number, the priority subroutine na~e, and priority subroutine parameters.

This call statement may connect an Intracom interrupt to an I/O pattern, resident in the RIO PP, which will communicate information to the Intracom during the real time phase of the hybrid program whenever its associated priority interrupt is triggered.

It may connect a priority interrupt to a priority subroutine which will be called into execution by the Hybrid Monitor's PP program (HYP) during the real time phase whenever the connected priority interrupt occurs. The CONNECT program executes or places in an RIO buffer for execution when RLTIME is called, the various initialization codes of the priority subroutine and t e r min ate s upon encountering the CALL F ASTPRG statement; then during the real time phase whenever the associated priority interrupt is detected, the priority subroutine will be entered after the CALL F ASTPRG statement and the real time code will be executed. The initialization code of a priority subroutine usually contains a SMSK call statement, whose purpose is to set the mask of (i.e., enable) the associated priority interrupt. The SMSK statement is placed in the RIO buffer to be processed at the time the RLTIME call statement is executed.

The CONNECT statement may connect both an I/O pattern and a priority subroutine to a priority interrupt. In which case, the I/O pattern will be executed completely and then the priority subroutine will be executed.

RLT/ME

This system subroutine is called, following the initialization portion (pre-real time phase) of a hybrid program at the point in the main program where it is desired for real time processing of priority interrupts to be initiated. This subroutine determines whether the total CPU execution time required by both hybrid programs exceeds 80 percent of the available CPU time. A pause is initiated in the new hybrid program if


678 Fall Jeint Cemputer Cenference, 1968

the total execution time needed does exceed the available CPU time. The routine enables the IntracQm's priQrity interrupt. subsystem. The prime functicns of the RLT'IME call statement are activating the Hybrid Menitor so that it may start real time precessing Qf prierity interrupts and ca using the HIO program to' be loaded into. a poel PP. HIO remains resident in the pp. during real time and makes it possible to' cemmunicate with the Intracom and the analeg ccmputer.

WAIT

Fellowing the RLTIME call statement the WAIT subreutine is called by the main prQgram to' place the main pregram in recall status until requested to. become active again by an ACTIVE or ABORT call statement in a priority interrupt initiated prierity subrQutine. The CPU at this point discontinues processing the slew or nonreal time portion of the hybrid program.

I/O patterns, priority subroutines, and combination I/O patterns and prierity subroutines continue to operate during this time, that the main pregram is in recall status, whenever, initiated by their associated priority interrupts.

I/O pattern body

The body Qf an I/O pattern is primarily made up of the RADeS and the WDAGS statements. These two. call statements centrel the flew ef analog-to-digital and digital-to-analog data and perfQrm the actual transfer ef that data to and frem the digital cemputer. ,

The functiQn of the RADGS system routine is to read sequentially addressed analog-to-digital (A/D) channels, A/D channels eriginate frem analeg trunks lecated en the analeg cemputer's patchboard, by means of the analog-to-digital converter (ADC) in the Intracom, transfer the data read frem the Intracom's ADC to the HIO PP, and then pass the data into a specified buffer in central memory. In the RADGS call statement the address of first A/D channel to. be read, the total number of channels to be read, and the buffer intO' which the data is to be stered are specified. AlsO', one of eight sample al\d held contrels en the Intracem patchbeard may be specHied; thereby, allewing the A/D· channels equipped with sample and held amplifiers to' be placed in held prier to' their being read by the ADC, previding apprepriate patching has been dene en the Intracem.

The WDAGS subreutine outputs to. sequentially addressed digital-to-analeg channels (DAGs) in the Intracom . data which has been previously prepared by the digital program (GALL SeALOUT) er data scaled, co' nverted , and packed by the WDACS subreutine itself. The HAGs' outputs are terminated en analog trunks en the analog computer patchbeard. The WHAOS call statement specifies the buffer frem which data is to output, the address ef the first DAC to' which data are to' be transferred, and the total number of sequentially addressed DACs to. which data are to' be eutput. If ene of the eight transfer centrels, lecated en the Intracom patchboard, is specified then, aU data to' be output are transferred to' the DACs sequentially but are cenverted simultaneeusly to' ana leg veltages. If the data to' be transferred have net been previeusly prepared, a table of scales (cenversion factors to cenvert frem physical units to. analeg voltages) must be specified in the WDAGS call sta;tement.

The body cf the I/O pattern may also centain calls to system subreutines which read Qr write logic signals to' er frem individual or groups Qf discrete lines which Qriginate er terminate on the Intracem patchboard, change the mode ef the Intracom, control the precisien interval generator, set er reset interrupt masks, and ·etc.

Real time code of a priority subroutine

N ermally in the real time code a can to the SCALIN system subreutine is made to unpack, cenvert, and scale the data that have been placed in central memory by the HIO PP as a result of a RADGS call in an I/O pattern. Computatiens based upen this data are then made in the priority subroutine using any legitimate Fortran statements and/er the data are stered en the disk fer later analysis during the post-real time phase of the hybrid pregram. Data which have been generated by the priority subroutine are prepared for output to' the analog computer by a call to the SCALOUT subroutine _ which scales, converts, and packs the generated data. Nerm.ally this data will then be output to' the analeg compute:r by a WDACS call statement in an I/O pattern.

Leading edge I/O

At this point the significance of having both an I/O pattern and a priority subroutine asseciated with a prierity interrupt should be reemphasized. Since the I/O pattern executien is


The Leckheed Hybred System-A Giant Step 679 '

accomplished by the HIO PP, it is apparent that parallel cemputatiQn in the CPU may be taking place while the input or eutput of data is being handled in the PP.

If, fQr example, two. interrupts which have associated leading edge I/O Qccur simultaneQusly, HIO perfQrms the prQcessing Qf data assQciated with the highest priQrity interrupt and then, by switching the prierity interrupt to a hybrid priQrity tree, causes the Hybrid MQnitor to swit~h the CPU to. the priority subrQutine assQciated with this priQrity interrupt. HIO now prQcesses I/O data assQciated with the other priQrity interrupt while the CPU is executing the prierity subreutine asseciated with the highest prierity interrupt. Then UPQn cempletiQn Qf this priQrity subroutine, the ether priQrity subreutine will be'gin executiQn. Thus, parallel input/Qutput and CPU ccmputatiQn is accQmplished. This becomes very impQrtant when it is realized that if two. hybrid jcbs are running in parallel, then CPU cemputatiQn and two I/O patterns may be preceeding in pa.rallel.

Hybrid utility display

InfQrmatiQn about the priority interrupts being used in a hybrid pr.ogram may be displayed Qn a display SCQpe by using the Hybrid Utility Task Qf the display Qperating system. Each interrupt's priority, HOOK duty cycle count, elapsed duty cycle cQunt, and the number Qf times that the asseciated priority subrQutine has been in executiQn when a higher priority interrupt Qccurred is displayed. This display allows the prQgress .of the real time phase .of a hybrid program to be mon ito. red.

If a duty cycle Qf zero. is placed Qn a HOOK data card, a maximum duty cycle will be assumed and cnly cne hybrid prQgram Qf this na.ture is allQwed Qn the cQmputer at a time. This feature assures that the hybrid jQb will nQt be thrQwn cff due to duty cycle failures and it allQwsa methQd whereby the duty cycle Qf a prierity subrQutine can be evaluated by m.onitering the actual duty cycle time en the display. Once the duty cycle has been determined, it may be entered via the display keyboard under Task H to medify the appropriate HOOK data card for subsequent runs.

RELEASE

When it is desired to' terminate the real time prQcessing of prierity interrupts, the RELEASE statement is called. This' subrQutine inferms the

Hybrid MQniter to' gO' inactive and causes the HIO pp to be drcpped, thus ending cemmunicatiQn with the Intracom and/er analQg cemputer.

Priority interrupt hardware

The priority interrupt subsystem of the linkage equipment (Intracem) is cemprised Qf an interrupt register, mask register, switching register, enable/ dis,able flip-flep, two' steering gates, and twO' interrupt priority trees. Each registe,r cQnsists of 24 flip-flQPs; thus, 24 individual and unique priQrity interrupts are provided fer hybrid prQgram usage. A simplified blQck diagram of the priority interrupt subsystem is shown in Figure 12.

A basic priQrity interrupt line cQnsists . of a mask, a switch, and an interrupt flip-flop. The interrupt flip-flQP is set by a lQgic signal applied to. the pr.oper IntracQm patchboard hele Qr by an INTRPT call statement frem the HIO PP. Nete that the interrupt flip-flQP cannet beset unless the Enable/Disable flip-flQP has been enabled by the RLTIME call statement frQm the HIO PP.

If bQth an I/O pattern and a priQrity subroutine are to. be initiated by the interrupt, neither the I/O Interrupt Inhibit Qr the Hybrid Interrupt Inhibit are inhibited by lQgic signals on the IntracQm p1atchboard. In this case, the switch flip-flQP WQuld be reset, having been reset if set by the changing ef states of the Enable/disable flip-fl.oP which eccurred in response to the call RLTIME statement. Then assuming that the Mask flip-flcp has been set by a SMSK call statement frem the HIO PP, the I/O steering gate is enabled and passes the interrupt signal to' the I/O prierity tree where it is ceded.

The priQrity tree generates a coded' numbe:r, which is read by the HIO PP, centaining the highest priority interrupt currently active in the IntracQm. The RIO PP executes the I/O pattern associated with that priQrity interrupt and sends a functiQn cede to. the Intracem which sets the switch flip-flep. T'he setting Qf the switch flipflQp disables the I/O steering gate and enables the Hybrid steering gate which allQws the prierity interrupt signal to be p'assed to. the Hybrid priQrity tree where it is ceded. The HYP PP reads this cQded number and if no. higher priQrity interrupt assQciated priority subreutine is being executed, the HYP PP initiate3 an exchange jump to. the priQrity subreutine assQciated with the active priQrity interrupt. Upon completiQn cf the exchange jump to' the prierity subroutine,


.680 Fall Joint Computer Conference, 1968

the HYP PPsends a function code to the Intracom which resets the switch and interrupt flipflops.

If only an I/O pattern is to be executed, the Hybrid Interrupt Inhibit is inhibited by a logic ground applied at the patchboard. The priority interrupt is processed as previously dis.cussed except that upon completion of the pattern execution the interrupt flip-flop is reset by a function code from the HIO PP and nothing is done to the switch flip-flop.

To execute only a priority subroutine, the I/O Interrupt Inhibit is inhibited which sets the switch flip-flop and maintains it in a set state. The priority interrupt is processed as previously described.

Non-real time hybrid input-output

A number of system subroutines are provided for communicating with the various sub-systems of the linkage equipment. These subroutines use

the HIO PP to perform the actual communication with the linkage equipment. They may be used either in the real time phase or in the non-real time phases of a hybrid program. Several examples of their use in the real time phase have been discussed previously.

To be used in one of the non-real time phases of a hybrid program a call is made to the LOADHIO subroutine which loads the RIO program into an available pool PP (see Figure 13). Once RIO has been loaded, then any of the subroutines listed in Figure 13 may be called. The DROPRIO call statement is used to inform the system that no further communication to the Intracom is to occur and HIO is then dropped from the pool PP.

Analog input-output

The digital computer can perform initialization, checking, and monitoring of various analog computer components by using AIO. The system

FIGURE 12-Intra.com interrupt SubsYfitem

DIGITAL CALL STATEME .... N_TS __ ....

RMSK

CMIIK (ALSO 8ETUPFL)

MASTER CLEAR

JNTRPT

RLTDlE

BETUPFL

MASTER CLEAR

CDITS

FUNCTION DECODER I/O CHANNEL CONTROLLER

1------1 MASK 1

I--~t---+-------t------i SWITCH

FUNCTION

DECODER HYBRID CONTROLLER 0

I/O INTERRUPT INHIBIT

(I/O PATTERN INHIBITED)

HYBRID INTERRUPT INHIBrr (PRIORITY SUBROUTINE lNHIBr;t'ED)

NOTES: @ HIO SENDS RESET CODE WHEN I/O T.:\ PATTERN EXECUTION 18 COMPLETED. o HYBRID MONITOR SENDS RESET CODa

WHEN EXCHANGE JUMP HAS B'fEN MADE TO THE PRIORITY SUBROUTINE.


The Lo.ckheed Hybred System-A Giant Step 681

SETUPFL

. WADHIO

(IntracCID I/O Subroutines)

CINTS (clears interrupts) RPIG (read PIG) (].ISK (clears I18.sks) SCAIOOT (scale data for output) INTRPr (set interrupt) 3MSK (set mask) PATIO (execute I/O pattern) STORE (place sample/holti in hold) PIG (change mode of PIG) TRACK (place SiB in sample) RAnCS (read A/D channels) TRNSFER (DAG control) RDI'3CR (read discrete line) WDAGS (output to DAG3) RD\.J' (read parallel word) ~IDISGR (write to discrete) .\ RMODE (read Intracan mode) ~ID\<1 (write to parallel "Ioro) RMSK (read masks) lOODE (set Intracan mode)

WPIG (initialize PIG)

DROPHIO

FIGURE l3-Non-real time HIO call order

subroutine, CONSOLE, is called to specify the analo.g computer with which communication is desired. The MODE, READ, and SETPOT subroutines are used during the analo.g setup phase o.f the hybrid pro.gram to. change the mo.de of the analo.g co.mputer, to read analo.g components, and to. set the Po.tentio.meters. These analog co.mputer setup commands are processed much like those of HIO. A pool PP pro.gram, AIO is called up to. process the 'requests that are placed in the central memo.ry circular buffer, and when the requests have been processed, the PP is returned back to. the o.perating system.

Since the data channel, connected to. the analog contro.ller o.f an Intracom is only reserved during the time that an actual communication is being made, two. AlO PPs 'may be operating via the Intracom's single analog co.ntro.ller to different analo.g compute~s. Communicatio.n can be performed simultaneously to. theanalo.g computer and to the Intracom because separate PPs are used to. transmit informatio.n to the analo.g controller· and to. the I/O contro.ller o.f the linkage equipment. This feature permits a hybrid prob· lem and an analog pro.blem to. be run using the same Intraco.m and at the same time witho.ut interfering with each other.

Automatic problem verification

Static checking o.f the analog co.mputer por~ tio.ns o.f a hybrid problem can be perfo.rmed using the Automatic Problem Verification (APV) digital program which resides in the central library sto.red o.n the mass sto.rage device. APV m:ay also be used as a request package to. o.perate the analo.g computer if desired.

APV uses source program statements, similar in syntax to. Fortran, to process commands to select an analog computer or an Intracom, to set an analog computer or Intraco.m mode, to set a Po.tentiometer, to. set the precision interval generator, to set a digital to analo.g co.nverter, to. read analo.g components" an.d to. test readings fro.m an analog computer against the evaluatio.n of an arithmetic expressio.n. Each source statement is processed immediately after it is read from either the remo.te display or the input file. If an error is detected, the nature of the error detected is output to either the remo.te display, or to the output file.

Testing is perfo.rmed by statements of the fo.rm: system variable (a string o.f characters representing the value o.f a particular analo.g oomponent) = expressio.n (string o.f co.nstants, system variables, etc., separated by arithmetic operato.rs) . When such a statement is encountered, the analog co.mpo.nent specified by the system variable is read, the expressio.n is evaluated with o.ther system variables being read if necessary, and if the two values o.btained lie within a specified tolerance, the test passes. To.lerances can be specified by the programmer o.r standard built-in to.lerances may be used. If the test fails, the value read for the system variable being checked, the value of the evaluated expre~ sio.n, and the difference between these two. values are output to the display and to the o.utput file ..

Step-by-step static checking of the analo.g computer under the pro.grammer's control is acco.mplished by allowing the APV program to be controlled from the remote display.

SUMMARY

This paper has speculated o.n the blue sky hybrid systems o.f the future, and discussed the general features and some o.f the details o.f implementatio.n o.f the Lockheed Missiles and Space Company (LMSG) hybrid computer system. Mo.st o.f the features described were implemented by modifying and augmenting a digital batch processing system.


682 Fall Jo.int Co.mputer Co.nference, 1968

At the time of the writing of this paper there. have been at least six implementatio.ns o.f hybrid o.r real time systems using CDC 6000 series digital computers. All o.f these systems are different. Each system has been implemented independently and the emphasis guiding the develo.pment of each system has been focused o.n completely different areas. The desire to. use the system as a batch processor has tended in some systems to. o.verride the hybrid requirements.

The backgro.und of p'eople responsible for the software develo.pment has also varied. Tho.s,e with predo.minately analog background have been s,atisfled with simple system design which requires the hybrid programmer/o.perator to. use complicated methods o.f program organizatio.n and contro.l. Those with batch processing experience have compro.mised the hybrid requirements and have been mo.re concerned with protecting the system fro.m the hybrid pro.grammer/o.perato.r rather than giving him mo.re capability and assistance.

Interface hardware varies in each o.f these systerns fro.m a single level interrupt so.urce to a Hardware Hybrid Mo.nitor.

Mo.st o.f the systems which have been delivered are no.w maintained by the customer. The independent development o.f these systems continually widens the gap between the compatability o.f the various systems. This trend has been aggravated by the tendencies of people to. defend their o.wn implementatio.ns to the point o.f igno.ring o.the·r system approaches that would sati.sfy their particular hybrid requirements.

The reason fo.r all of this disunity is the lack o.f experience and the resulting definitio.n o.f the requirements o.f an efficient hybrid co.mputing system. Hybrid computation is at the point that batch pro.cessing was when each installation de .. veloped their own operating systems. What hybrid system software needs is a definition of what a hybrid system is and guidelines to implement it.

The definition of a hybrid system would set requirements o.n hybrid equipment vendo.rs to. furnish software to. meet a certain standard. They would then be required to develop and maintain a

system o.f software that would meet the requirements o.f most customers. This definition of ,a hybrid package would also. allo.w the pro.spective customer to. make meaningful evaluatio.n of a hybrid system regardless o.f his experience.

Guidelines should emphasize characteristics of a hybrid system that will handle most o.f the problems that a general hybrid facility will face. In general the implementatio.n of a hybrid system has been built aro.und the system's initial requirements. After this has been do.ne the capability of the system is set and future requirements must fall within that cap.ability. Systems, however, should be designed to explo.it the capability of the hardware as the o.nly limiting facto.r.

If we review o.ur crystal ball gazing and our current implementatio.n, we can say we have co.me a long way towards our ultimate go.al. We have established co.mmunicatio.n to. the hybrid pro.grammer / o.perato.r at a Io.catio.n remo.te to the digital computer and close to. the operatio.ns center of the hybrid program. We have allowed him co.mplete system flexibility giving him extensive co.ntro.I and monito.ring capabilities. We have harnessed a large CPU and taken advantage o.f a multi-pro.cesso.r organizatio.n. The system is effective as a hybrid computer allo.wing two. hybrid jobs to. run simultaneously and is still capable of processing backgro.und digital wo.rk when possible. Our interactive Automatic Pro.blem Verificatio.n Pro.gram (APV) is an effective step towards the software package described.

The "blue sky" set o.f software described at the beginning of the paper is beyo.nd the reso.urces and capability o.f a single existing installation, and can o.nly come about by utilizing all the re.. sources o.f vendo.rs, universities, and users in designing and implementing co.mprehensive and efficient hybrid software systems.

We at LMSC feel that we have made a giant step fo.rward. The rest of the way is clearly possible with the hardware available. The last step will come about when so.ftware resources are better marshalled to. pursue the commo.n objective, "the ultimate hybrid system."


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The Lockheed hybrid system-A giant step · PDF fileThe Lockheed hybrid system-A giant step ... The flexi ­ bility gained from ... *Hybrid computation at LMCS began in 1966 with a

The Lockheed hybrid system-A giant step · PDF fileThe Lockheed hybrid system-A giant step ... The flexi bility gained from ... *Hybrid computation at LMCS began in 1966 with a