10 SUMMARY

In 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every two years in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map. The SIA road map has been a guide for the industry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. Semiconductor industry tries to keep up with Moore's law, to appease the hunger for ever increasing chip functionality. Accordingly, as dis­cussed in Chapter 2, past, present and future CMOS technology generations are characterized by decreasing feature sizes, increasing clock frequencies and tran­sistor densities causing both increased power consumption and power density. Especially for battery operated systems increased power consumption burdens the environment and is also responsible for increased operational costs, whereas increased power densities push chip temperatures to physical limits. Battery operated systems and nowadays desktop machines possess standby modes to reduce overall power consumption.

The power dissipation of computational processes depends on the physical processes on which they are based. They are either reversible or irreversible, as discussed in Chapter 3. In contrast to an irreversible process, a reversible pro­cess can traverse all states in opposite direction in such a way that it dissipates no power and does not increase the entropy of the universe when returning to its initial state. In case logical operations performed by reversible logic are physi­cally being performed quasi-statically, the process will be physically reversible. However, practical operations will have to be performed in a limited amount of time, i.e. non quasi-statically, and hence become physically irreversible.

141

P. R. van der Meer et al., Low-Power Deep Sub-Micron CMOS Logic© Kluwer Academic Publishers, Boston 2004

142 SUMMARY

In literature the concept adiabatic often is used as a synonym for loss­less. However, adiabatic processes are not necessarily physically reversible and therefore not necessarily lossless.

Irreversible logic is based on physically irreversible processes, since after the logic operations the logic state sequences are not traversed in reverse order to return to initial states. Accordingly, logical irreversibility implies physical irreversibility. Nowadays the majority of computational systems consists of irreversible logic CMOS blocks. Consequently, all power delivered to them will eventually be dissipated, either in the form of functional power or in parasitical power.

The functional power is dissipated to just attribute to state changes of a digital CMOS circuit in favor of logic operations, and is a function of the following parameters:

• node transition-cycle activity;

• clock frequency;

• transition-cycle energy.

In Chapter 4 it has been discussed that the node transition-cycle activity can be reduced by e.g. choice of algorithm and reduction of signal skews. Parallelisa­tion is a method to reduce the clock frequency. Reducing the supply voltage or voltage swing, statically or as a function of e.g. workload, is the most effective way of reducing the transition-cycle energy, because of its quadratic depen­dency. Increasing the reversibility factor by the use of ramp-wise, step-wise or resonant charging circuits, is another solution to reduce transition-cycle energy.

The parasitical power is either dissipated when the circuit is idle, defined as leakage power, or could be dissipated during state transitions without attribut­ing to the actual changes of the internal states, defined as short-circuit power. Accordingly, the parasitical power is divided into two groups:

• leakage power dissipation;

• short-circuit power dissipation.

Leakage power is device related power, whereas short-circuit power is circuit related power caused by rail-to-rail currents during state transitions of static CMOS circuits. The latter can be reduced by preventing direct paths from rail to rail, e.g. by using domino logic or reducing the supply voltage below the sum of both NMOS and PMOS threshold voltages. The leakage power dissipation becomes dominant during idle periods, since the functional and short circuit power dissipation are zero then. It has been subdivided into three sub-groups distinguished by their origins:

• channel leakage current;

B.5. CONCLUSIONS 143

• diode leakage current;

• gate leakage current.

In Chapter 5 techniques have been presented to reduce the parasitical power dissipation. It has been argued that the weak-inversion current component of the channel leakage current and the gate leakage currents become dominant compared to the other components, since both increase exponentially due to device scaling trends.

Regarding technological developments it is to be expected that gate leakage will be reduced by application of high-permittivity gate insulators.

Chapter 6 introduced a classification of weak-inversion current-reduction techniques. These techniques might all be applied to systems possessing standby periods. At the highest level a distinction has been made between two main weak-inversion current-reduction concepts:

• power reduction without state retention;

• power reduction with state retention.

Power reduction without state retention culminates into a power switch, which switches off all combinatorial logic. To retain circuit states in e.g. flip-flops, while reducing weak-inversion currents, system states can either be stored in separate intrinsically low leakage, e.g. high threshold voltage, memory cells or the memory cell can be switched into a low leakage state. The latter can be done by:

• substrate biasing;

• source or gate biasing;

• Triple-S.

In Chapter 7 the effectiveness of weak-inversion current reduction techniques has been determined. It became clear that substrate biasing has no future in bulk CMOS processes, since the body factor diminishes, resulting in negligi­ble leakage current reduction. As far as source and gate biasing is concerned, except for the application in power switches and the Triple-S mode switches, no practical solutions to implement both biasing techniques in sequential cir­cuitry have been found yet. Triple-S, a new leakage current reduction tech­nique, enables almost independent design of the leakage reduction factor and speed performance. Leakage reduction factors between 103 and 105 have been demonstrated for circuits containing flip-flops and latches. These experimental circuits have been processed in an adapted 0.25J.lm CMOS technology with low and high threshold voltages of 200m V and 600m V, respectively.

144 SUMMARY

Chapter 8 presents the Triple-S technique applied to ring oscillators, latches, flip-flops, shift registers and binary counters, to determine speed, area, func­tional power and leakage. To implement the power reduction scheme ofTriple-S in combination with power switches, the following is required:

• low- and high-threshold-voltage transistors;

• stable and defined clock signal during standby periods;

• "virtual" power supply lines and power switches.

Compared to "standard" designs, implementation of Triple-S and power switches requires on average 12% more chip area and consumes 4% more functional power. Propagation delays of Triple-S flip-flops increase by 10%. Overhead costs are dominant compared to the energy stored in the system. To regain the overhead costs, weak-inversion currents have to be reduced considerably and standby periods have to be large compared to active periods.