/THE INSTITUTION OF'ENGINEERS, SRI LANKAIESL ENGINEERING QOURSE

PART II EXAMINATION-2013210 ELECTRONICS

Instructions: This question paper contains eight questions in five pages. Answer anyfive questions only. Tentative mark allocation for each part is shown in brackets forguidance only.

Time: Three hours.

QIThe 6.8-V zener diode shown in Figure QI is specified to have Vz = 6.8Vat Iz =SmA, rz = 20.0 and IZK = 0.2mA. The supply voltage V + is nominally 10 V but canvary by ±1 V.

y+

R tllz t ~

+ hVzo

Var.

R = .5 t..H

6.8-Vzener

-- -- ...-(a (b)

Figure Ql

a) Find Vawith no load and with V+ at its nominal value.

b) Find the change in Varesulting from the ±V change in V+. Note LlVa/LlV+that,

usuallyexpressed in mVN, is known as line regulation.c) Find the change in Varesulting from connecting a load resistance RLthat draws a

current/, = lmA, and hence find the load regulation LlVa/ LlIL in mV/mA.

d) Find the change in Vawhen RL= 2 ill.e) Find the value of Vawhen RL= 0.5 kQ.t) What is the minimum value of RLfor which the diode still operates in the

breakdown region?

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Q2(a) Draw a circuit syip.~oL of a diode and a zener diode also

characteristic of each.(b) What are the full wave rectification methods? Explain using circuit diagrams. ."

Draw give output wave form of each circuit when the input is sinusoidal. '(c) Following figure Q2 shows the emitter follower regulation circuit. Calculate the

values of VL, IL '. VCEand power dissipated by T 1. Assume that the transistor isSi.

r2000

1kO

15 V

Vz= 9V

Figure Q2Q3(a) Write down the three bipolar transistor configurations for a NPN transistor.(b) Draw the input (Is Vs VSE) and output (Ie Vs VCE) characteristics ofa bipolar

transistor.(c) Consider the common emitter transistor amplifier circuit as shown in Figure Q3.

The transistor is silicon.1. Calculate the quiescent voltages and currents.11. Find the small signal mid-band voltage gain of the circuit.

Vcc

Oulpul...---Input

---+-----t-[

Figure Q3Where: Vcc=12V, VSE= O.6V, R1=18kn, R2= 3.3kQ, Rc= 1.5kQ, RE= 270n,P=100

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Q4

The circuit given in Figure Q4, it is required to determine the value of the voltageVBB that results when the transistor is operating.

Vcc= lOV

Rc = 1 kO

--Figure Q4

a) in the active mode with VCE = SVb) at the edge of saturationc) deep in saturation with P[orced = 10

For simplicity, assume that VBE is constant at 0.7 V and remains a VCEsat = 0.2V. ~value of the transistor is specified to be 50.

Q5

a) List four characteristics of an ideal operational amplifier (Op-Amp), Comparethe ideal values with its typical values.

b) Explain following terms for an operational amplifier

1. Input bias current11. Output offset voltage111. Common Mode Rejection Ratio (CMRR)IV. Slew rate.

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c) Determine an expression for the output voltage VOUI in the circuit shown inFigure Q5. Assume that the operational amplifier is ideal.

v.:>------- ..•

Figure Q5

If V2=3V and V3=2V, then find the value of VI to get VOUI = 0 V.

Q6

a) i. Convert 110010 100 10 10 1112 to Octal and Hexadecimal numbers.

ii. Express the decimal number -34 ina. Sign magnitude methodb. l's compliment methodc. 2's compliment method

b) 1. State De Morgan's theorem for three Boolean variables A, Band C.

ii. Define the following 2-input logic elements using truth tables.

a. NOR gateb. NAND gatec. Exclusive OR gate

iii. Realize the following logic function using 2-input NOR gates.It =A.B+AB

c) 1. Prove that following identity,(AEBBEBAB)(AEBCEB AC) = A+BC

ii. Simplify the following function using Karnaugh map.

f(A,B, C,D) = L(0,1,2,3,4,9,1 0,13,14)

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Q7

The i1!Qutto a cqmbinational Iogic circuit is a 4-1?itQ!!1arynumberABCD where A andD are the most and least significant bits respectively. The output of the circuit is"TRUE" or "1" if the input is divisible by 4 or greater than 10 otherwise the output is"FALSE" or "0". Assume that zero is not divisible by any number.

a) Write the Boolean expression for the output (j) and simplify it using Kamaugh map,Show the steps very clearly.

b) Design a circuit using logic gates (OR, AND and NOT) to carry out the function.

Q8a) Explain briefly the terms "Combinational-logic" and "Sequential-logic".b) Design a 3-bit Gray Code synchronous counter using JK Flip-Flop and logic

gates. You have to show the state diagram, state table, K-map, logic expressionsand the circuit implementation very clearly.

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