The informal side of system architecture; illustrated by a waferstepper case

9 jun 1999 -1

The informal side of System Engineering Gerrit Muller

The informal side of system architecture;illustrated by a waferstepper case

Gerrit Muller

9-6-1999

Eindhoven

EESI System Architecture Colloquia

9 jun 1999 -2


The Market

PC’snon PCcomputing

consumerelectronics

communications otherapplications

IC’s memory othersemiconductors

equipment

32% 16% 17% 18% 17%

semiconductor salesby end-user market

source: Dataquest, ING Barings research www.asml.com

ASMLsales 1997: 1.8 Gflnet income: 0.3 Gfl

steppers

GDP

1997 2002

33.4 T$ 39.4 T$

electronicsales

semiconductorsales

902.4G$ 1284.2G$

151.7G$ 330.6G$

Equipmentsales

22.3G$ 42.8G$

Steppers 3.6G$ 7.3G$

17% 26%

15%

16%

13%

17%

3% 3%

9 jun 1999 -3


Market fluctuations

1995 1996 1997 1998

units 177 205 211 162net sales Mfl 918 1331 1803 1717net profit Mfl 131 218 329 137

The semiconductor equipment market shows large fluctuations.

Logistic and manufacturing flexibility is a must.

9 jun 1999 -4


Cost structure flexibility

Sales

$

Costs

Income

Market fluctuation

mar

gin

9 jun 1999 -5


What is a waferstepper?

Lightsource

Mask (Reticle)

Lens

Wafer

Die

9 jun 1999 -6


Step & Scan technology

Slit

reticle

wafer

Lens

Scanningfieldsize

Steppingfieldsize

250 mm/s

Lens

9 jun 1999 -7


Main specifications

Imaging Overlay Productivity

linewidth: 180 nm (1999)

critical dimension control

AA (single machine) 40 nmBC (matched) 60 nm

96 Wafers per hour

For comparison: Wafer diameter 200 mmDie size ca.: 20*20 mm2

9 jun 1999 -8


Moore’s law (or challenge?)

97 98 99 00 01 02 03 04 05 06

1994roadmap

1997roadmap

1998revision

1999proposal

leadingedgecustomers

250 180 130

250 180 150 130

250 180 150 125

250 180 130 90

250 180 130 100

SIA

linewidth in nm.

9 jun 1999 -9


Product roadmap

/250C i-line stepper

/300C DUV stepper

/500 DUV scanner

/400 i-line scanner

/900 193 nm scanner

/700 DUV scanner

S700 DUV scanner T700 DUV scanner

T1100 193 nm scanner

5500 stepper body

5500 scanner body

Atlas 300 mm body

AT

HE

NA

/TIS

Qu

adru

pol

e

2 k

Hz

lase

r

S400 I-line scanner T400 I-line scanner

/300D

9 jun 1999 -10


Modular subsystems

illuminator light source

reticle stage

lens

wafer stage

base frame

reticlehandling

waferhandling

contaminationandtemperaturecontrol

electronicscabinets

UIconsole

measurement

9 jun 1999 -11


System engineering

mechanics optics control measurement contamination &temperature

imaging

overlay

productivity

9 jun 1999 -12


System Engineering

Integral system design consistencyintegritybalancespecificationdecompositionmodularizationverification

synergy of products and programs roadmapvision

Product and Competence definition

leading in system-

supporting system- integrationrisk reduction

9 jun 1999 -13


Profile of the system engineer

• Highly skilled:• Communication• Teamwork• Documentation• Multi-tasking (many parallel activities,

many interrupts)• Conceptual• Pragmatic;

balance between conceptual and pragmatic• Insight in process

(Who does What, When for Whom)• Insight in Politics• Authority by expertise• Flexible and open, egoless• Ability to absorb new know how fast, curiosity• Constructive Critical (inward and outward)

•Generalist, know how areas:•Source, illumination•Projection•Dynamic performance•Alignment•Metrology•C&T•Wafer+reticle handling+interfacing•Aerial imaging•Imaging, processing, application•throughput•Safety•Reliability, uptime, robustness•Testability•fab interfacing; HW+SW infrastructure•configuration management•Software architecure•Electronics architecture•Mechanical architecture

9 jun 1999 -14


Understanding the context of the system

Waferstepper

Fablayout

Wafer

Processing

Metrology

Reticles

Reticleproduction

devices

Semiconductordesign

Resists Fablogistics

Reticlelogistics

Operator

Contamination

Tracks

Fabautomation

Matching

Fab costmodel

Fabinfrastructure

utilization

Yieldoptimization

SPC

maintenanceInspection andmonitoring

Waferlogistics

9 jun 1999 -15


Understanding the business context

Yield

Valueof performance(MHz)

CD control

Parameter trade-offs

Other players:• equipments vendors• system integrators• lease companies• fab designers• consultants• mask makers• resist makers• wafer makers• OEM’s: laser• intimate partners: lens

Business models of the customer:• design houses• foundries• vertical integration

Limited number of customers;Many systems per customer

9 jun 1999 -16


Understanding the people context

People

Process

Skills

Style

Organization

Culture

Shared Value

teams

maturitypeople

principles

maturitycompany

strategy

profesionalism

technologies

location

informalrelations

projects

incentives

reviews

roles, tasksWell-being

motivation

family, homesituation

facilitation

9 jun 1999 -17


Technology context

Lithography

ImagingOptics

MechanicsDynamics

Measurement

Lens

Gratings

Lasers

OpticalMaterials

coatings

Servo’s

ConstructionmaterialsConstruction

C&T

Robotics

Interferometers

Dosecontrol

Lamps

homesensors

Measurementsgratings

Measurementlasers

SW control

Capacitivesensors Hall

sensors

Mirrors

Actuators

modes

TransmissionUVsensitivity

Temperaturesensitivity ReflectionStiffness

Dosesensor

bandwidth

frequency

energy

Pulse timing

uniformity

Airshowers

Cooling

Vacuumclamping

Lightsensors

Pre-amplifiersAnalog

signalprocesing

Digitalsignalprocessing

Real timeexecutives

Digitalinfrastructure

Motors

9 jun 1999 -18


Project Context

Specification

Budget Time

Projectdefinition

Verification

Plan

production

Installation

Support

RisksDevelopmentresources

Materialplanning

Projectdocumentation

Progress

prototypes

Functional models

Criticalpath

milestones

review

Qualityassurance

tracking

Criticalresources

Long leaditems

Scenario’s

TPD

Alfa test

Beta test

Productionengineers

Productionspace

Serviceengineers

Training

Manuals

Customers

Slot list

Spareparts

Babysitters

activities

SPS/SDS ATPFAT/SAT

outsourcingcosts

9 jun 1999 -19


Making specification and design choices

System context

Business context

People context

marketing,applicationmanager

Business manager

line manager

TechnologyCompetencemanager

Project contextProductDevelopmentmanager

System Engineer(s)

OverviewCommon sense proposals

80/20 optimization, balanceknowledgerisksauthority

design for:• market• verification• manufacturability• serviceability•etcetera

architecture for:• control• dynamics• optics• mechanics•etcetera

System Design

9 jun 1999 -20


Overlay budget

ProcessOverlay80 nm

Reticle15 nm

MatchedMachine60 nm

Processdependencysensor5 nm

SingleMachine30 nm

LensMatching25 nm

MatchingAccuracy5 nm

Stageoverlay12 nm

Globalalignmentaccuracy6 nm

Stage gridaccuracy5 nm

Metrologystability6 nm

Positionaccuracy7 nm

alignmentrepro5 nm

Interferometerstability1 nm

Framestability2.5 nm

trackingerror phi75 nrad

trackingerror X, Y2.5 nm

Off axispos measaccuracy4 nm

Stage Al.pos. meas.accuracy4 nm

Systemadjustmentaccuracy2 nm

Off axisSensorrepro3 nm

Blue alignsensorrepro3 nm

trackingerror WS2 nm

trackingerror RS1 nm

9 jun 1999 -21


Lens

Metroframe

RSSensor-

frame + IFBlock

RS Chuck

Reticle

IF

Ref-IF

HP Rack

SSMotor

Z-sensors

Ligh

tE

nerg

y

LoSMotor

WS Chuck

WaferIF

SS MotorLoS

Motor

Ref-IFIF

Block

Z-mirror

WS Balance Mass

Air Foot

RS BalMass

Airshower RS

Airshower WS

MO

PAC/PA

MetrologyAirmounts

Accelerometers

Accelerometers

Baseframe

: Fiducial

Athena

LS

P and T in LensCompartment

Data Delay

Airmount Noise,Limited Vibration

Isolation

MetroframeTemperature Drift

-> Effect on Showers-> Effect on Position of

mirrors and IF's

ATHENA MeasurementAccuracy

ATHENA MountingAccuracy/Stability

Disturbance ofHorizontal WS Servo

by LS setpoints

Lens Heating

Accuracy ofLensmanipulators

T at top element of Lens(Mag)

Inaccurate LensaccelerationFeedforward

Wafer Expansion byExposure

Wafer Distortion due toWafer table/chuck

Wafer Expansion byinput temperature offset

Metroframe vibration due towater cooling (lens and

coolplates)

Sound

P and T of Air,Turbulences

Reticle Errors

Reticle Heating

Reticle Clampinginduced DistortionFiducial Stability

Fiducial Calibration

TIS Measurement

Fiducial Stability

Fiducial Calibration

Metrology inaccuracy

Metrology Errors

HP Inaccuracy

Servo error

Chuck expansion

Heat flow from LoS intoIF beams

Heat flow from SS intoWS chuck

Chuck deformation

Chuck DimensionalStability

Gravity Compensatornoise

Feedforward errors

Heat flow from LoS intoIF beams andcompartment

Heat flow from SS intoRS chuck andcompartment

Illumination settings (NA )

Overlay Influence Diagram.(Maarten Bonnema, 19-3-1999)

T stability in LSlightpath

Lens Dynamics

P&T correction of Lens

9 jun 1999 -22


Development phases

sps

plancost, effort,time

prs

eps

eds

integrationplan

tps

1 2 3 40

feasibility definition system design integration field monitoring

tpd

alfa test TAR

prototype

tps

subsystem spec subsystemdesign

engineering verification

sds

beta test TAR

business impact

9 jun 1999 -23


SPS contents checklist

performance requirements• imaging• overlay• throughput

overviewdoc tree, structure

functional requirements draft• functional model (extern) draft

product lifecycleoption structure draft

machine requirements• design constraints, f.i. robustness• safety• reliability• COG, COO• interoperability

operations requirements draft• serviceability• manufacturability

option structure

environment requirements• wafer, reticles• power, gases, water, etc.• weight size•transport

functional requirements• functional model (extern)• factory integration• user interface

operations requirements• serviceability• manufacturability

1 2 30

feasibility definition system design subsystem spec engineeringsubsystemdesign

9 jun 1999 -24


SDS contents checklist

decomposition in subsystems draft

performance budgets draft

functional model (design) draft

overview

control architecture

costprice budget draft

consumable budget draft

diagnostic analysis

safety design

accessabilityset up sequencetolerance budgetcycle time budget

mechanical layout budgets draft

SW architecture draft

Electrical architecture

handling interfacespower, gas, water, etc budgets draft

doc tree, structure draft doc tree, structureoverview draft

decomposition in subsystems

performance budgets

functional model (design) concept functional model (design)

function allocation draft function allocation concept function allocation

control architecture draft

SW architecture

mechanical layout budgetspower, gas, water, etc budgets

safety analysis

reliability/uptime budget draft reliability/uptime budget

costprice budgetconsumable budget

1 2 30

feasibility definition system design subsystem spec engineeringsubsystemdesign

diagnostic design

interoperability design

transport design

9 jun 1999 -25


Definitions

PRS Product Requirement Specification What should the product be Marketing

SPS System Performance Specification What will the product be SESDS System Design Specification How will it be made SETPS Test Performance Specification What and how will it be tested SETAR Test Acceptance Report Testresult SE

EPS Element Performance Specification What D&EEDS Element Design Specification How D&ETPS Test Performance Specification What and how will it be tested D&ETAR Test Acceptance Report Testresult D&EEPS, EDS, TPS are recursively applied from subsystem level to monodisciplinary module level

9 jun 1999 -26


Concurrent engineering, Integration

subsystem1 design

subsystem2 design

Subsystem n design

dynamical performance

imaging

overlay

metrology

levelling

Integrationprototypes

Finalintegration

Concurrentengineering

• • • • •

9 jun 1999 -27


Overlay budget

ProcessOverlay80 nm

Reticle15 nm

MatchedMachine60 nm

Processdependencysensor5 nm

SingleMachine30 nm

LensMatching25 nm

MatchingAccuracy5 nm

Stageoverlay12 nm

Globalalignmentaccuracy6 nm

Stage gridaccuracy5 nm

Metrologystability6 nm

Positionaccuracy7 nm

alignmentrepro5 nm

Interferometerstability1 nm

Framestability2.5 nm

trackingerror phi75 nrad

trackingerror X, Y2.5 nm

Off axispos measaccuracy4 nm

Stage Al.pos. meas.accuracy4 nm

Systemadjustmentaccuracy2 nm

Off axisSensorrepro3 nm

Blue alignsensorrepro3 nm

trackingerror WS2 nm

trackingerror RS1 nm

2003:35 nm

Dramaticincrease ofcomplexity!

Documents

The informal side of system architecture; illustrated by a waferstepper case