THE I C-BUS SPECIFICATION VERSION 2.0 DECEMBER 1998esd.cs.ucr.edu/webres/i2c20.pdf · NOTE: Neither the 100 kbit/s I2C-bus system nor the 100 kbit/s devices have been changed. 1.2

THE I2C-BUS SPECIFICATION

VERSION 2.0

DECEMBER 1998

2

Philips Semiconductors

The I2C-bus specification

CONTENTS

1 PREFACE 3

1.1 Version 1.0- 1992 31.2 Version 2.0- 1998 31.3 Purchase of Philips I2C-bus components 3

2 THE I2C-BUS BENEFITS DESIGNERSAND MANUFACTURERS 4

2.1 Designer benefits 42.2 Manufacturer benefits 6

3 INTRODUCTION TO THE I2C-BUSSPECIFICATION 6

4 THE I2C-BUS CONCEPT 6

5 GENERAL CHARACTERISTICS 8

6 BIT TRANSFER 8

6.1 Data validity 86.2 START and STOP conditions 9

7 TRANSFERRING DATA 10

7.1 Byte format 107.2 Acknowledge 10

8 ARBITRATION AND CLOCKGENERATION 11

8.1 Synchronization 118.2 Arbitration 128.3 Use of the clock synchronizing

mechanism as a handshake 13

9 FORMATS WITH 7-BIT ADDRESSES 13

10 7-BIT ADDRESSING 15

10.1 Definition of bits in the first byte 1510.1.1 General call address 1610.1.2 START byte 1710.1.3 CBUS compatibility 18

11 EXTENSIONS TO THE STANDARD-MODE I2C-BUS SPECIFICATION 19

12 FAST-MODE 19

13 Hs-MODE 20

13.1 High speed transfer 2013.2 Serial data transfer format in Hs-mode 2113.3 Switching from F/S- to Hs-mode and back 2313.4Hs-mode devices at lower speed modes2413.5 Mixed speed modes on one serial

bus system 24

13.5.1 F/S-mode transfer in amixed-speed bus system 25

13.5.2 Hs-mode transfer in amixed-speed bus system 25

13.5.3 Timing requirements for the bridge in amixed-speed bus system 27

14 10-BIT ADDRESSING 27

14.1 Definition of bits in the first two bytes 2714.2 Formats with 10-bit addresses 2714.3 General call address and start byte

with 10-bit addressing 30

15 ELECTRICAL SPECIFICATIONSAND TIMING FOR I/O STAGESAND BUS LINES 30

15.1 Standard- and Fast-mode devices 3015.2 Hs-mode devices 34

16 ELECTRICAL CONNECTIONS OFI2C-BUS DEVICES TO THE BUS LINES 37

16.1 Maximum and minimum values ofresistors Rp and Rs for Standard-modeI2C-bus devices 39

17 APPLICATION INFORMATION 41

17.1 Slope-controlled output stages ofFast-mode I2C-bus devices 41

17.2 Switched pull-up circuit for Fast-mode I2C-bus devices 41

17.3 Wiring pattern of the bus lines 4217.4 Maximum and minimum values of

resistors Rp and Rs for Fast-modeI2C-bus devices 42

17.5 Maximum and minimum values ofresistors Rp and Rs for Hs-modeI2C-bus devices 42

18 BI-DIRECTIONAL LEVEL SHIFTERFOR F/S-MODE I2C-BUS SYSTEMS 42

18.1 Connecting devices with differentlogic levels 43

18.1.1 Operation of level shifter 44

19 DEVELOPMENT TOOLS AVAILABLEFROM PHILIPS 45

20 SUPPORT LITERATURE 46

3



1 PREFACE

1.1 Version 1.0 - 1992

This version of the 1992 I2C-bus specification includes thefollowing modifications:

• Programming of a slave address by software has beenomitted. The realization of this feature is rathercomplicated and has not been used.

• The “low-speed mode” has been omitted. This mode is,in fact, a subset of the total I2C-bus specification andneed not be specified explicitly.

• The Fast-mode is added. This allows a fourfold increaseof the bit rate up to 400 kbit/s. Fast-mode devices aredownwards compatible i.e. they can be used in a 0 to100 kbit/s I2C-bus system.

• 10-bit addressing is added. This allows 1024 additionalslave addresses.

• Slope control and input filtering for Fast-mode devices isspecified to improve the EMC behaviour.

NOTE: Neither the 100 kbit/s I2C-bus system nor the100 kbit/s devices have been changed.

1.2 Version 2.0 - 1998

The I2C-bus has become a de facto world standard that isnow implemented in over 1000 different ICs and licensedto more than 50 companies. Many of today’s applications,however, require higher bus speeds and lower supplyvoltages. This updated version of the I2C-bus specificationmeets those requirements and includes the followingmodifications:

• The High-speed mode (Hs-mode) is added. This allowsan increase in the bit rate up to 3.4 Mbit/s. Hs-modedevices can be mixed with Fast- and Standard-modedevices on the one I2C-bus system with bit rates from 0to 3.4 Mbit/s.

• The low output level and hysteresis of devices with asupply voltage of 2 V and below has been adapted tomeet the required noise margins and to remaincompatible with higher supply voltage devices.

• The 0.6 V at 6 mA requirement for the output stages ofFast-mode devices has been omitted.

• The fixed input levels for new devices are replaced bybus voltage-related levels.

• Application information for bi-directional level shifter isadded.

1.3 Purchase of Philips I 2C-bus components

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips.

4



2 THE I2C-BUS BENEFITS DESIGNERS ANDMANUFACTURERS

In consumer electronics, telecommunications andindustrial electronics, there are often many similaritiesbetween seemingly unrelated designs. For example,nearly every system includes:

• Some intelligent control, usually a single-chipmicrocontroller

• General-purpose circuits like LCD drivers, remote I/Oports, RAM, EEPROM, or data converters

• Application-oriented circuits such as digital tuning andsignal processing circuits for radio and video systems,or DTMF generators for telephones with tone dialling.

To exploit these similarities to the benefit of both systemsdesigners and equipment manufacturers, as well as tomaximize hardware efficiency and circuit simplicity, Philipsdeveloped a simple bi-directional 2-wire bus for efficientinter-IC control. This bus is called the Inter IC or I2C-bus.At present, Philips’ IC range includes more than 150CMOS and bipolar I2C-bus compatible types forperforming functions in all three of the previouslymentioned categories. All I2C-bus compatible devicesincorporate an on-chip interface which allows them tocommunicate directly with each other via the I2C-bus. Thisdesign concept solves the many interfacing problemsencountered when designing digital control circuits.

Here are some of the features of the I2C-bus:

• Only two bus lines are required; a serial data line (SDA)and a serial clock line (SCL)

• Each device connected to the bus is softwareaddressable by a unique address and simplemaster/slave relationships exist at all times; masters canoperate as master-transmitters or as master-receivers

• It’s a true multi-master bus including collision detectionand arbitration to prevent data corruption if two or moremasters simultaneously initiate data transfer

• Serial, 8-bit oriented, bi-directional data transfers can bemade at up to 100 kbit/s in the Standard-mode, up to400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in theHigh-speed mode

• On-chip filtering rejects spikes on the bus data line topreserve data integrity

• The number of ICs that can be connected to the samebus is limited only by a maximum bus capacitance of400 pF.

Figure 1 shows two examples of I2C-bus applications.

2.1 Designer benefits

I2C-bus compatible ICs allow a system design to rapidlyprogress directly from a functional block diagram to aprototype. Moreover, since they ‘clip’ directly onto theI2C-bus without any additional external interfacing, theyallow a prototype system to be modified or upgradedsimply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.

Here are some of the features of I2C-bus compatible ICswhich are particularly attractive to designers:

• Functional blocks on the block diagram correspond withthe actual ICs; designs proceed rapidly from blockdiagram to final schematic.

• No need to design bus interfaces because the I2C-businterface is already integrated on-chip.

• Integrated addressing and data-transfer protocol allowsystems to be completely software-defined

• The same IC types can often be used in many differentapplications

• Design-time reduces as designers quickly becomefamiliar with the frequently used functional blocksrepresented by I2C-bus compatible ICs

• ICs can be added to or removed from a system withoutaffecting any other circuits on the bus

• Fault diagnosis and debugging are simple; malfunctionscan be immediately traced

• Software development time can be reduced byassembling a library of reusable software modules.

In addition to these advantages, the CMOS ICs in theI2C-bus compatible range offer designers special featureswhich are particularly attractive for portable equipment andbattery-backed systems.

They all have:

• Extremely low current consumption

• High noise immunity

• Wide supply voltage range

• Wide operating temperature range.

5



Fig.1 Two examples of I2C-bus applications: (a) a high performance highly-integrated TV set(b) DECT cordless phone base-station.

handbook, full pagewidth SDA SCL

MICRO-CONTROLLER

PCB83C528

PLLSYNTHESIZER

TSA5512

NON-VOLATILEMEMORY

PCF8582E

STEREO / DUALSOUNDDECODER

TDA9840

HI-FIAUDIOPROCESSOR

TDA9860

SINGLE-CHIPTEXT

SAA52XX

M/S COLOURDECODER

TDA9160A

PICTURESIGNAL

IMPROVEMENT

TDA4670

VIDEOPROCESSOR

TDA4685

ON-SCREENDISPLAY

PCA8510

(a)

MSB575

SDA SCL

LINEINTERFACE

PCA1070

BURST MODECONTROLLER

PCD5042

ADPCM

PCD5032

(b)

DTMFGENERATOR

PCD3311

MICRO-CONTROLLER

P80CLXXX

6



2.2 Manufacturer benefits

I2C-bus compatible ICs don’t only assist designers, theyalso give a wide range of benefits to equipmentmanufacturers because:

• The simple 2-wire serial I2C-bus minimizesinterconnections so ICs have fewer pins and there arenot so many PCB tracks; result - smaller and lessexpensive PCBs

• The completely integrated I2C-bus protocol eliminatesthe need for address decoders and other ‘glue logic’

• The multi-master capability of the I2C-bus allows rapidtesting and alignment of end-user equipment viaexternal connections to an assembly-line

• The availability of I2C-bus compatible ICs in SO (smalloutline), VSO (very small outline) as well as DILpackages reduces space requirements even more.

These are just some of the benefits. In addition, I2C-buscompatible ICs increase system design flexibility byallowing simple construction of equipment variants andeasy upgrading to keep designs up-to-date. In this way, anentire family of equipment can be developed around abasic model. Upgrades for new equipment, orenhanced-feature models (i.e. extended memory, remotecontrol, etc.) can then be produced simply by clipping theappropriate ICs onto the bus. If a larger ROM is needed,it’s simply a matter of selecting a micro-controller with alarger ROM from our comprehensive range. As new ICssupersede older ones, it’s easy to add new features toequipment or to increase its performance by simplyunclipping the outdated IC from the bus and clipping on itssuccessor.

3 INTRODUCTION TO THE I2C-BUS SPECIFICATION

For 8-bit oriented digital control applications, such asthose requiring microcontrollers, certain design criteria canbe established:

• A complete system usually consists of at least onemicrocontroller and other peripheral devices such asmemories and I/O expanders

• The cost of connecting the various devices within thesystem must be minimized

• A system that performs a control function doesn’trequire high-speed data transfer

• Overall efficiency depends on the devices chosen andthe nature of the interconnecting bus structure.

To produce a system to satisfy these criteria, a serial busstructure is needed. Although serial buses don’t have thethroughput capability of parallel buses, they do requireless wiring and fewer IC connecting pins. However, a busis not merely an interconnecting wire, it embodies all theformats and procedures for communication within thesystem.

Devices communicating with each other on a serial busmust have some form of protocol which avoids allpossibilities of confusion, data loss and blockage ofinformation. Fast devices must be able to communicatewith slow devices. The system must not be dependent onthe devices connected to it, otherwise modifications orimprovements would be impossible. A procedure has alsoto be devised to decide which device will be in control ofthe bus and when. And, if different devices with differentclock speeds are connected to the bus, the bus clocksource must be defined. All these criteria are involved inthe specification of the I2C-bus.

4 THE I2C-BUS CONCEPT

The I2C-bus supports any IC fabrication process (NMOS,CMOS, bipolar). Two wires, serial data (SDA) and serialclock (SCL), carry information between the devicesconnected to the bus. Each device is recognized by aunique address (whether it’s a microcontroller, LCD driver,memory or keyboard interface) and can operate as eithera transmitter or receiver, depending on the function of thedevice. Obviously an LCD driver is only a receiver,whereas a memory can both receive and transmit data. Inaddition to transmitters and receivers, devices can also beconsidered as masters or slaves when performing datatransfers (see Table 1). A master is the device whichinitiates a data transfer on the bus and generates the clocksignals to permit that transfer. At that time, any deviceaddressed is considered a slave.

7



Table 1 Definition of I2C-bus terminology

The I2C-bus is a multi-master bus. This means that morethan one device capable of controlling the bus can beconnected to it. As masters are usually micro-controllers,let’s consider the case of a data transfer between twomicrocontrollers connected to the I2C-bus (see Fig.2).

This highlights the master-slave and receiver-transmitterrelationships to be found on the I2C-bus. It should be notedthat these relationships are not permanent, but onlydepend on the direction of data transfer at that time. Thetransfer of data would proceed as follows:

TERM DESCRIPTION

Transmitter The device which sends data to thebus

Receiver The device which receives data fromthe bus

Master The device which initiates a transfer,generates clock signals andterminates a transfer

Slave The device addressed by a master

Multi-master More than one master can attempt tocontrol the bus at the same timewithout corrupting the message

Arbitration Procedure to ensure that, if morethan one master simultaneously triesto control the bus, only one is allowedto do so and the winning message isnot corrupted

Synchronization Procedure to synchronize the clocksignals of two or more devices

1) Suppose microcontroller A wants to send information tomicrocontroller B:

• microcontroller A (master), addresses microcontroller B(slave)

• microcontroller A (master-transmitter), sends data tomicrocontroller B (slave- receiver)

• microcontroller A terminates the transfer

2) If microcontroller A wants to receive information frommicrocontroller B:

• microcontroller A (master) addresses microcontroller B(slave)

• microcontroller A (master- receiver) receives data frommicrocontroller B (slave- transmitter)

• microcontroller A terminates the transfer.

Even in this case, the master (microcontroller A) generatesthe timing and terminates the transfer.

The possibility of connecting more than onemicrocontroller to the I2C-bus means that more than onemaster could try to initiate a data transfer at the same time.To avoid the chaos that might ensue from such an event -an arbitration procedure has been developed. Thisprocedure relies on the wired-AND connection of all I2Cinterfaces to the I2C-bus.

If two or more masters try to put information onto the bus,the first to produce a ‘one’ when the other produces a‘zero’ will lose the arbitration. The clock signals duringarbitration are a synchronized combination of the clocksgenerated by the masters using the wired-AND connectionto the SCL line (for more detailed information concerningarbitration see Section 8).

Fig.2 Example of an I2C-bus configuration using two microcontrollers.

MBC645

SDA

SCL

MICRO -CONTROLLERA

STATICRAM OREEPROM

LCDDRIVER

GATEARRAY ADC

MICRO -CONTROLLERB

8



Generation of clock signals on the I2C-bus is always theresponsibility of master devices; each master generates itsown clock signals when transferring data on the bus. Busclock signals from a master can only be altered when theyare stretched by a slow-slave device holding-down theclock line, or by another master when arbitration occurs.

5 GENERAL CHARACTERISTICS

Both SDA and SCL are bi-directional lines, connected to apositive supply voltage via a current-source or pull-upresistor (see Fig.3). When the bus is free, both lines areHIGH. The output stages of devices connected to the busmust have an open-drain or open-collector to perform thewired-AND function. Data on the I2C-bus can betransferred at rates of up to 100 kbit/s in theStandard-mode, up to 400 kbit/s in the Fast-mode, or up to3.4 Mbit/s in the High-speed mode. The number ofinterfaces connected to the bus is solely dependent on thebus capacitance limit of 400 pF. For information onHigh-speed mode master devices, see Section 13.

6 BIT TRANSFER

Due to the variety of different technology devices (CMOS,NMOS, bipolar) which can be connected to the I2C-bus,the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are notfixed and depend on the associated level of VDD (seeSection 15 for electrical specifications). One clock pulse isgenerated for each data bit transferred.

6.1 Data validity

The data on the SDA line must be stable during the HIGHperiod of the clock. The HIGH or LOW state of the data linecan only change when the clock signal on the SCL line isLOW (see Fig.4).

Fig.3 Connection of Standard- and Fast-mode devices to the I2C-bus.

MBC631

SCLKN1OUT

SCLKIN

SCLK

DATAN1OUT

DATAIN

DEVICE 1

SDA (Serial Data Line)

SCL (Serial Clock Line)

SCLKN2OUT

SCLKIN

SCLK

DATAN2OUT

DATAIN

DEVICE 2

VDD

RpRppull-up

resistors

9



Fig.4 Bit transfer on the I2C-bus.

handbook, full pagewidth

MBC621

data linestable;

data valid

changeof dataallowed

SDA

SCL

6.2 START and STOP conditions

Within the procedure of the I2C-bus, unique situationsarise which are defined as START (S) and STOP (P)conditions (see Fig.5).

A HIGH to LOW transition on the SDA line while SCL isHIGH is one such unique case. This situation indicates aSTART condition.

A LOW to HIGH transition on the SDA line while SCL isHIGH defines a STOP condition.

START and STOP conditions are always generated by themaster. The bus is considered to be busy after the STARTcondition. The bus is considered to be free again a certaintime after the STOP condition. This bus free situation isspecified in Section 15.

The bus stays busy if a repeated START (Sr) is generatedinstead of a STOP condition. In this respect, the START(S) and repeated START (Sr) conditions are functionallyidentical (see Fig.6). For the remainder of this document,therefore, the S symbol will be used as a generic term torepresent both the START and repeated STARTconditions, unless Sr is particularly relevant.

Detection of START and STOP conditions by devicesconnected to the bus is easy if they incorporate thenecessary interfacing hardware. However,microcontrollers with no such interface have to sample theSDA line at least twice per clock period to sense thetransition.

Fig.5 START and STOP conditions.


MBC622

SDA

SCLP

STOP condition

SDA

SCLS

START condition

10



7 TRANSFERRING DATA

7.1 Byte format

Every byte put on the SDA line must be 8-bits long. Thenumber of bytes that can be transmitted per transfer isunrestricted. Each byte has to be followed by anacknowledge bit. Data is transferred with the mostsignificant bit (MSB) first (see Fig.6). If a slave can’treceive or transmit another complete byte of data until ithas performed some other function, for example servicingan internal interrupt, it can hold the clock line SCL LOW toforce the master into a wait state. Data transfer thencontinues when the slave is ready for another byte of dataand releases clock line SCL.

In some cases, it’s permitted to use a different format fromthe I2C-bus format (for CBUS compatible devices forexample). A message which starts with such an addresscan be terminated by generation of a STOP condition,even during the transmission of a byte. In this case, noacknowledge is generated (see Section 10.1.3).

7.2 Acknowledge

Data transfer with acknowledge is obligatory. Theacknowledge-related clock pulse is generated by themaster. The transmitter releases the SDA line (HIGH)during the acknowledge clock pulse.

The receiver must pull down the SDA line during theacknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse (see Fig.7). Ofcourse, set-up and hold times (specified in Section 15)must also be taken into account.

Usually, a receiver which has been addressed is obliged togenerate an acknowledge after each byte has beenreceived, except when the message starts with a CBUSaddress (see Section 10.1.3).

When a slave doesn’t acknowledge the slave address (forexample, it’s unable to receive or transmit because it’sperforming some real-time function), the data line must beleft HIGH by the slave. The master can then generateeither a STOP condition to abort the transfer, or a repeatedSTART condition to start a new transfer.

If a slave-receiver does acknowledge the slave addressbut, some time later in the transfer cannot receive anymore data bytes, the master must again abort the transfer.This is indicated by the slave generating thenot-acknowledge on the first byte to follow. The slaveleaves the data line HIGH and the master generates aSTOP or a repeated START condition.

If a master-receiver is involved in a transfer, it must signalthe end of data to the slave- transmitter by not generatingan acknowledge on the last byte that was clocked out ofthe slave. The slave-transmitter must release the data lineto allow the master to generate a STOP or repeatedSTART condition.

Fig.6 Data transfer on the I2C-bus.


MSC608

SrorP

SDA

Sr

P

SCL

STOP orrepeated START

condition

SorSr

START orrepeated START

condition

1 2 3 - 8 9

ACK

9

ACK

7 81 2

MSB acknowledgementsignal from slave

byte complete,interrupt within slave

clock line held low whileinterrupts are serviced

acknowledgementsignal from receiver

11



Fig.7 Acknowledge on the I2C-bus.


MBC602

S

STARTcondition

9821

clock pulse foracknowledgement

not acknowledge

acknowledge

DATA OUTPUTBY TRANSMITTER

DATA OUTPUTBY RECEIVER

SCL FROMMASTER

8 ARBITRATION AND CLOCK GENERATION

8.1 Synchronization

All masters generate their own clock on the SCL line totransfer messages on the I2C-bus. Data is only valid duringthe HIGH period of the clock. A defined clock is thereforeneeded for the bit-by-bit arbitration procedure to takeplace.

Clock synchronization is performed using the wired-ANDconnection of I2C interfaces to the SCL line. This means

that a HIGH to LOW transition on the SCL line will causethe devices concerned to start counting off their LOWperiod and, once a device clock has gone LOW, it will holdthe SCL line in that state until the clock HIGH state isreached (see Fig.8). However, the LOW to HIGH transitionof this clock may not change the state of the SCL line ifanother clock is still within its LOW period. The SCL linewill therefore be held LOW by the device with the longestLOW period. Devices with shorter LOW periods enter aHIGH wait-state during this time.

Fig.8 Clock synchronization during the arbitration procedure.

CLK1

CLK2

SCL

counterreset

waitstate

start countingHIGH period

MBC632

12



When all devices concerned have counted off their LOWperiod, the clock line will be released and go HIGH. Therewill then be no difference between the device clocks andthe state of the SCL line, and all the devices will startcounting their HIGH periods. The first device to completeits HIGH period will again pull the SCL line LOW.

In this way, a synchronized SCL clock is generated with itsLOW period determined by the device with the longestclock LOW period, and its HIGH period determined by theone with the shortest clock HIGH period.

8.2 Arbitration

A master may start a transfer only if the bus is free. Two ormore masters may generate a START condition within theminimum hold time (tHD;STA) of the START condition whichresults in a defined START condition to the bus.

Arbitration takes place on the SDA line, while the SCL lineis at the HIGH level, in such a way that the master whichtransmits a HIGH level, while another master istransmitting a LOW level will switch off its DATA outputstage because the level on the bus doesn’t correspond toits own level.

Arbitration can continue for many bits. Its first stage iscomparison of the address bits (addressing information isgiven in Sections 10 and 14). If the masters are each trying

to address the same device, arbitration continues withcomparison of the data-bits if they are master-transmitter,or acknowledge-bits if they are master-receiver. Becauseaddress and data information on the I2C-bus is determinedby the winning master, no information is lost during thearbitration process.

A master that loses the arbitration can generate clockpulses until the end of the byte in which it loses thearbitration.

As an Hs-mode master has a unique 8-bit master code, itwill always finish the arbitration during the first byte (seeSection 13).

If a master also incorporates a slave function and it losesarbitration during the addressing stage, it’s possible thatthe winning master is trying to address it. The losingmaster must therefore switch over immediately to its slavemode.

Figure 9 shows the arbitration procedure for two masters.Of course, more may be involved (depending on howmany masters are connected to the bus). The momentthere is a difference between the internal data level of themaster generating DATA 1 and the actual level on the SDAline, its data output is switched off, which means that aHIGH output level is then connected to the bus. This willnot affect the data transfer initiated by the winning master.

Fig.9 Arbitration procedure of two masters.


MSC609

DATA1

DATA2

SDA

SCL

S

master 1 loses arbitrationDATA 1 SDA

13



Since control of the I2C-bus is decided solely on theaddress or master code and data sent by competingmasters, there is no central master, nor any order ofpriority on the bus.

Special attention must be paid if, during a serial transfer,the arbitration procedure is still in progress at the momentwhen a repeated START condition or a STOP condition istransmitted to the I2C-bus. If it’s possible for such asituation to occur, the masters involved must send thisrepeated START condition or STOP condition at the sameposition in the format frame. In other words, arbitration isn’tallowed between:

• A repeated START condition and a data bit

• A STOP condition and a data bit

• A repeated START condition and a STOP condition.

Slaves are not involved in the arbitration procedure.

8.3 Use of the clock synchronizing mechanism asa handshake

In addition to being used during the arbitration procedure,the clock synchronization mechanism can be used toenable receivers to cope with fast data transfers, on eithera byte level or a bit level.

On the byte level, a device may be able to receive bytes ofdata at a fast rate, but needs more time to store a receivedbyte or prepare another byte to be transmitted. Slaves can

then hold the SCL line LOW after reception andacknowledgment of a byte to force the master into a waitstate until the slave is ready for the next byte transfer in atype of handshake procedure (see Fig.6).

On the bit level, a device such as a microcontroller with orwithout limited hardware for the I2C-bus, can slow downthe bus clock by extending each clock LOW period. Thespeed of any master is thereby adapted to the internaloperating rate of this device.

In Hs-mode, this handshake feature can only be used onbyte level (see Section 13).

9 FORMATS WITH 7-BIT ADDRESSES

Data transfers follow the format shown in Fig.10. After theSTART condition (S), a slave address is sent. Thisaddress is 7 bits long followed by an eighth bit which is adata direction bit (R/W) - a ‘zero’ indicates a transmission(WRITE), a ‘one’ indicates a request for data (READ). Adata transfer is always terminated by a STOP condition (P)generated by the master. However, if a master still wishesto communicate on the bus, it can generate a repeatedSTART condition (Sr) and address another slave withoutfirst generating a STOP condition. Various combinations ofread/write formats are then possible within such a transfer.

Fig.10 A complete data transfer.


S

1 – 7 8 9 1 – 7 8 9 1 – 7 8 9

P

STOPcondition

STARTcondition

DATA ACKDATA ACKADDRESS ACKR/W

SDA

SCL

MBC604

14



Possible data transfer formats are:

• Master-transmitter transmits to slave-receiver. Thetransfer direction is not changed (see Fig.11).

• Master reads slave immediately after first byte (seeFig.12). At the moment of the first acknowledge, themaster- transmitter becomes a master- receiver and theslave-receiver becomes a slave-transmitter. This firstacknowledge is still generated by the slave. The STOPcondition is generated by the master, which haspreviously sent a not-acknowledge (A).

• Combined format (see Fig.13). During a change ofdirection within a transfer, the START condition and theslave address are both repeated, but with the R/W bitreversed. If a master receiver sends a repeated STARTcondition, it has previously sent a not-acknowledge (A).

NOTES:

1. Combined formats can be used, for example, tocontrol a serial memory. During the first data byte, theinternal memory location has to be written. After theSTART condition and slave address is repeated, datacan be transferred.

2. All decisions on auto-increment or decrement ofpreviously accessed memory locations etc. are takenby the designer of the device.

3. Each byte is followed by an acknowledgment bit asindicated by the A or A blocks in the sequence.

4. I2C-bus compatible devices must reset their bus logicon receipt of a START or repeated START conditionsuch that they all anticipate the sending of a slaveaddress, even if these START conditions are notpositioned according to the proper format.

5. A START condition immediately followed by a STOPcondition (void message) is an illegal format.

Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address.The transfer direction is not changed.


MBC605

A/AA

'0' (write)data transferred

(n bytes + acknowledge)

A = acknowledge (SDA LOW)

A = not acknowledge (SDA HIGH)S = START condition

P = STOP condition

R/W

from master to slave

from slave to master

DATADATAASLAVE ADDRESSS P

Fig.12 A master reads a slave immediately after the first byte.


MBC606

A

(read)data transferred

(n bytes + acknowledge)

R/W A

1

PDATADATASLAVE ADDRESSS A

15



Fig.13 Combined format.


MBC607

DATAAR/W

read or write

A/ADATAAR/W

(n bytes+ ack.)

directionof transfermay changeat this point.

read or write

(n bytes+ ack.)

Sr = repeated START condition

A/A

* *

* not shaded becausetransfer direction ofdata and acknowledge bitsdepends on R/W bits.

SLAVE ADDRESSS Sr PSLAVE ADDRESS

10 7-BIT ADDRESSING

The addressing procedure for the I2C-bus is such that thefirst byte after the START condition usually determineswhich slave will be selected by the master. The exceptionis the ‘general call’ address which can address all devices.When this address is used, all devices should, in theory,respond with an acknowledge. However, devices can bemade to ignore this address. The second byte of thegeneral call address then defines the action to be taken.This procedure is explained in more detail inSection 10.1.1. For information on 10-bit addressing, seeSection 14

10.1 Definition of bits in the first byte

The first seven bits of the first byte make up the slaveaddress (see Fig.14). The eighth bit is the LSB (leastsignificant bit). It determines the direction of the message.A ‘zero’ in the least significant position of the first bytemeans that the master will write information to a selectedslave. A ‘one’ in this position means that the master willread information from the slave.

When an address is sent, each device in a systemcompares the first seven bits after the START conditionwith its address. If they match, the device considers itselfaddressed by the master as a slave-receiver orslave-transmitter, depending on the R/W bit.

A slave address can be made-up of a fixed and aprogrammable part. Since it’s likely that there will beseveral identical devices in a system, the programmablepart of the slave address enables the maximum possiblenumber of such devices to be connected to the I2C-bus.The number of programmable address bits of a devicedepends on the number of pins available. For example, ifa device has 4 fixed and 3 programmable address bits, atotal of 8 identical devices can be connected to the samebus.

The I2C-bus committee coordinates allocation of I2Caddresses. Further information can be obtained from thePhilips representatives listed on the back cover. Twogroups of eight addresses (0000XXX and 1111XXX) arereserved for the purposes shown in Table 2. The bitcombination 11110XX of the slave address is reserved for10-bit addressing (see Section 14).

Fig.14 The first byte after the START procedure.

handbook, halfpage

MBC608

R/W

LSBMSB

slave address

16



Table 2 Definition of bits in the first byte

Notes

1. No device is allowed to acknowledge at the receptionof the START byte.

2. The CBUS address has been reserved to enable theinter-mixing of CBUS compatible and I2C-buscompatible devices in the same system. I2C-buscompatible devices are not allowed to respond onreception of this address.

3. The address reserved for a different bus format isincluded to enable I2C and other protocols to be mixed.Only I2C-bus compatible devices that can work withsuch formats and protocols are allowed to respond tothis address.

10.1.1 GENERAL CALL ADDRESS

The general call address is for addressing every deviceconnected to the I2C-bus. However, if a device doesn’tneed any of the data supplied within the general callstructure, it can ignore this address by not issuing anacknowledgment. If a device does require data from ageneral call address, it will acknowledge this address andbehave as a slave- receiver. The second and followingbytes will be acknowledged by every slave- receivercapable of handling this data. A slave which cannotprocess one of these bytes must ignore it bynot-acknowledging. The meaning of the general calladdress is always specified in the second byte (seeFig.15).

There are two cases to consider:

• When the least significant bit B is a ‘zero’.

• When the least significant bit B is a ‘one’.

SLAVEADDRESS

R/W BIT DESCRIPTION

0000 000 0 General call address

0000 000 1 START byte(1)

0000 001 X CBUS address(2)

0000 010 X Reserved for different busformat(3)

0000 011 X Reserved for future purposes

0000 1XX X Hs-mode master code

1111 1XX X Reserved for future purposes

1111 0XX X 10-bit slave addressing

When bit B is a ‘zero’; the second byte has the followingdefinition:

• 00000110 (H‘06’). Reset and write programmable partof slave address by hardware. On receiving this 2-bytesequence, all devices designed to respond to thegeneral call address will reset and take in theprogrammable part of their address. Pre-cautions haveto be taken to ensure that a device is not pulling downthe SDA or SCL line after applying the supply voltage,since these low levels would block the bus.

• 00000100 (H‘04’). Write programmable part of slaveaddress by hardware. All devices which define theprogrammable part of their address by hardware (andwhich respond to the general call address) will latch thisprogrammable part at the reception of this two bytesequence. The device will not reset.

• 00000000 (H‘00’). This code is not allowed to be used asthe second byte.

Sequences of programming procedure are published inthe appropriate device data sheets.

The remaining codes have not been fixed and devicesmust ignore them.

When bit B is a ‘one’; the 2-byte sequence is a ‘hardwaregeneral call’. This means that the sequence is transmittedby a hardware master device, such as a keyboardscanner, which cannot be programmed to transmit adesired slave address. Since a hardware master doesn’tknow in advance to which device the message has to betransferred, it can only generate this hardware general calland its own address - identifying itself to the system (seeFig.16).

The seven bits remaining in the second byte contain theaddress of the hardware master. This address isrecognized by an intelligent device (e.g. a microcontroller)connected to the bus which will then direct the informationfrom the hardware master. If the hardware master can alsoact as a slave, the slave address is identical to the masteraddress.

Fig.15 General call address format.

MBC623

LSB

second byte

0 0 0 0 0 0 0 0 A X X X X X X X B A

first byte(general call address)

17



Fig.16 Data transfer from a hardware master-transmitter.


MBC624

generalcall address

(B)

A A

secondbyte

A A

(n bytes + ack.)

S 00000000 MASTER ADDRESS 1 PDATA DATA

In some systems, an alternative could be that thehardware master transmitter is set in the slave-receivermode after the system reset. In this way, a systemconfiguring master can tell the hardware master-transmitter (which is now in slave-receiver mode) to whichaddress data must be sent (see Fig.17). After thisprogramming procedure, the hardware master remains inthe master-transmitter mode.

10.1.2 START BYTE

Microcontrollers can be connected to the I2C-bus in twoways. A microcontroller with an on-chip hardware I2C-businterface can be programmed to be only interrupted byrequests from the bus. When the device doesn’t have such

an interface, it must constantly monitor the bus viasoftware. Obviously, the more times the microcontrollermonitors, or polls the bus, the less time it can spendcarrying out its intended function.

There is therefore a speed difference between fasthardware devices and a relatively slow microcontrollerwhich relies on software polling.

In this case, data transfer can be preceded by a startprocedure which is much longer than normal (see Fig.18).The start procedure consists of:

• A START condition (S)

• A START byte (00000001)

• An acknowledge clock pulse (ACK)

• A repeated START condition (Sr).

Fig.17 Data transfer by a hardware-transmitter capable of dumping data directly to slave devices.(a) Configuring master sends dump address to hardware master

(b) Hardware master dumps data to selected slave.


MBC609

write

A A

(a)

(b)

R/W

write

A A

(n bytes + ack.)

A/A

R/WS PSLAVE ADDR. H/W MASTER DUMP ADDR. FOR H/W MASTER X

S PDUMP ADDR. FROM H/W MASTER DATA DATA

18



Fig.18 START byte procedure.

MBC633

S

9821

Sr

7

ACK

dummyacknowledge

(HIGH)

start byte 00000001

SDA

SCL

After the START condition S has been transmitted by amaster which requires bus access, the START byte(00000001) is transmitted. Another microcontroller cantherefore sample the SDA line at a low sampling rate untilone of the seven zeros in the START byte is detected.After detection of this LOW level on the SDA line, themicrocontroller can switch to a higher sampling rate to findthe repeated START condition Sr which is then used forsynchronization.

A hardware receiver will reset on receipt of the repeatedSTART condition Sr and will therefore ignore the STARTbyte.

An acknowledge-related clock pulse is generated after theSTART byte. This is present only to conform with the bytehandling format used on the bus. No device is allowed toacknowledge the START byte.

10.1.3 CBUS COMPATIBILITY

CBUS receivers can be connected to the Standard-modeI2C-bus. However, a third bus line called DLEN must thenbe connected and the acknowledge bit omitted. Normally,I2C transmissions are sequences of 8-bit bytes; CBUScompatible devices have different formats.

In a mixed bus structure, I2C-bus devices must notrespond to the CBUS message. For this reason, a specialCBUS address (0000001X) to which no I2C-buscompatible device will respond, has been reserved. Aftertransmission of the CBUS address, the DLEN line can bemade active and a CBUS-format transmission sent (seeFig.19). After the STOP condition, all devices are againready to accept data.

Master-transmitters can send CBUS formats after sendingthe CBUS address. The transmission is ended by a STOPcondition, recognized by all devices.

NOTE: If the CBUS configuration is known, and expansionwith CBUS compatible devices isn’t foreseen, the designeris allowed to adapt the hold time to the specificrequirements of the device(s) used.

19



MBC634

S P

STOPcondition

CBUSload pulse

n - data bitsCBUSaddress

STARTcondition

R/Wbit

ACKrelated

clock pulse

SDA

SCL

DLEN

Fig.19 Data format of transmissions with CBUS transmitter/receiver.

11 EXTENSIONS TO THE STANDARD-MODE I2C-BUSSPECIFICATION

The Standard-mode I2C-bus specification, with its datatransfer rate of up to 100 kbit/s and 7-bit addressing, hasbeen in existence since the beginning of the 1980’s. Thisconcept rapidly grew in popularity and is today acceptedworldwide as a de facto standard with several hundreddifferent compatible ICs on offer from PhilipsSemiconductors and other suppliers. To meet thedemands for higher speeds, as well as make availablemore slave address for the growing number of newdevices, the Standard-mode I2C-bus specification wasupgraded over the years and today is available with thefollowing extensions:

• Fast-mode , with a bit rate up to 400 kbit/s.

• High-speed mode (Hs-mode ), with a bit rate up to3.4 Mbit/s.

• 10-bit addressing , which allows the use of up to 1024additional slave addresses.

There are two main reasons for extending the regularI2C-bus specification:

• Many of today’s applications need to transfer largeamounts of serial data and require bit rates far in excessof 100 kbit/s (Standard-mode), or even 400 kbit/s(Fast-mode). As a result of continuing improvements insemiconductor technologies, I2C-bus devices are nowavailable with bit rates of up to 3.4 Mbit/s (Hs-mode)without any noticeable increases in the manufacturingcost of the interface circuitry.

• As most of the 112 addresses available with the 7-bitaddressing scheme were soon allocated, it became

apparent that more address combinations were requiredto prevent problems with the allocation of slaveaddresses for new devices. This problem was resolvedwith the new 10-bit addressing scheme, which allowedabout a tenfold increase in available addresses.

New slave devices with a Fast- or Hs-mode I2C-businterface can have a 7- or a 10-bit slave address. Ifpossible, a 7-bit address is preferred as it is the cheapesthardware solution and results in the shortest messagelength. Devices with 7- and 10-bit addresses can be mixedin the same I2C-bus system regardless of whether it is anF/S- or Hs-mode system. Both existing and future masterscan generate either 7- or 10-bit addresses.

12 FAST-MODE

With the Fast-mode I2C-bus specification, the protocol,format, logic levels and maximum capacitive load for theSDA and SCL lines quoted in the Standard-mode I2C-busspecification are unchanged. New devices with an I2C-businterface must meet at least the minimum requirements ofthe Fast- or Hs-mode specification (see Section 13).

Fast-mode devices can receive and transmit at up to400 kbit/s. The minimum requirement is that they cansynchronize with a 400 kbit/s transfer; they can thenprolong the LOW period of the SCL signal to slow down thetransfer. Fast-mode devices are downward-compatibleand can communicate with Standard-mode devices in a0 to 100 kbit/s I2C-bus system. As Standard-modedevices, however, are not upward compatible, they shouldnot be incorporated in a Fast-mode I2C-bus system asthey cannot follow the higher transfer rate andunpredictable states would occur.

20



The Fast-mode I2C-bus specification has the followingadditional features compared with the Standard-mode:

• The maximum bit rate is increased to 400 kbit/s.

• Timing of the serial data (SDA) and serial clock (SCL)signals has been adapted. There is no need forcompatibility with other bus systems such as CBUSbecause they cannot operate at the increased bit rate.

• The inputs of Fast-mode devices incorporate spikesuppression and a Schmitt trigger at the SDA and SCLinputs.

• The output buffers of Fast-mode devices incorporateslope control of the falling edges of the SDA and SCLsignals.

• If the power supply to a Fast-mode device is switchedoff, the SDA and SCL I/O pins must be floating so thatthey don’t obstruct the bus lines.

• The external pull-up devices connected to the bus linesmust be adapted to accommodate the shorter maximumpermissible rise time for the Fast-mode I2C-bus. For busloads up to 200 pF, the pull-up device for each bus linecan be a resistor; for bus loads between 200 pF and400 pF, the pull-up device can be a current source(3 mA max.) or a switched resistor circuit (see Fig.43).

13 Hs-MODE

High-speed mode (Hs-mode) devices offer a quantumleap in I2C-bus transfer speeds. Hs-mode devices cantransfer information at bit rates of up to 3.4 Mbit/s, yet theyremain fully downward compatible with Fast- orStandard-mode (F/S-mode) devices for bi-directionalcommunication in a mixed-speed bus system. With theexception that arbitration and clock synchronization is notperformed during the Hs-mode transfer, the same serialbus protocol and data format is maintained as with theF/S-mode system. Depending on the application, newdevices may have a Fast or Hs-mode I2C-bus interface,although Hs-mode devices are preferred as they can bedesigned-in to a greater number of applications.

13.1 High speed transfer

To achieve a bit transfer of up to 3.4 Mbit/s the followingimprovements have been made to the regular I2C-busspecification:

• Hs-mode master devices have an open-drain outputbuffer for the SDAH signal and a combination of anopen-drain pull-down and current-source pull-up circuiton the SCLH output(1). This current-source circuitshortens the rise time of the SCLH signal. Only the

current-source of one master is enabled at any one time,and only during Hs-mode.

• No arbitration or clock synchronization is performedduring Hs-mode transfer in multi-master systems, whichspeeds-up bit handling capabilities. The arbitrationprocedure always finishes after a preceding mastercode transmission in F/S-mode.

• Hs-mode master devices generate a serial clock signalwith a HIGH to LOW ratio of 1 to 2. This relieves thetiming requirements for set-up and hold times.

• As an option, Hs-mode master devices can have abuilt-in bridge(1). During Hs-mode transfer, the highspeed data (SDAH) and high-speed serial clock (SCLH)lines of Hs-mode devices are separated by this bridgefrom the SDA and SCL lines of F/S-mode devices. Thisreduces the capacitive load of the SDAH and SCLHlines resulting in faster rise and fall times.

• The only difference between Hs-mode slave devicesand F/S-mode slave devices is the speed at which theyoperate. Hs-mode slaves have open-drain output bufferson the SCLH and SDAH outputs. Optional pull-downtransistors on the SCLH pin can be used to stretch theLOW level of the SCLH signal, although this is onlyallowed after the acknowledge bit in Hs-mode transfers.

• The inputs of Hs-mode devices incorporate spikesuppression and a Schmitt trigger at the SDAH andSCLH inputs.

• The output buffers of Hs-mode devices incorporateslope control of the falling edges of the SDAH and SCLHsignals.

Figure 20 shows the physical I2C-bus configuration in asystem with only Hs-mode devices. Pins SDA and SCL onthe master devices are only used in mixed-speed bussystems and are not connected in an Hs-mode onlysystem. In such cases, these pins can be used for otherfunctions.

Optional series resistors Rs protect the I/O stages of theI2C-bus devices from high-voltage spikes on the bus linesand minimize ringing and interference.

Pull-up resistors Rp maintain the SDAH and SCLH lines ata HIGH level when the bus is free and ensure the signalsare pulled up from a LOW to a HIGH level within therequired rise time. For higher capacitive bus-line loads(>100 pF), the resistor Rp can be replaced by externalcurrent source pull-ups to meet the rise time requirements.Unless proceeded by an acknowledge bit, the rise time ofthe SCLH clock pulses in Hs-mode transfers is shortenedby the internal current-source pull-up circuit MCS of theactive master.

(1) Patent application pending.

21



Fig.20 I2C-bus configuration with Hs-mode devices only.


MSC612

VSS

SLAVE

SDAH SCLH

VSS

MASTER/SLAVE

SDAH SCLH SDA

MCS

SCL

Rs Rs

SLAVE

SDAH SCLH

VSS

Rs Rs Rs Rs

VDD

VSS

MASTER/SLAVE

SDAH SCLH SDA SCL

Rs Rs

VDD

(1) (1)(1) (1)

(2) (2)

(4) (4) (3)MCS

(3)

(2) (2) (2) (2) (2) (2)

VDD

RpRp

SCLH

SDAH

(1) SDA and SCL are not used here but may be used for other functions.

(2) To input filter.

(3) Only the active master can enable its current-source pull-up circuit

(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCLH.

13.2 Serial data transfer format in Hs-mode

Serial data transfer format in Hs-mode meets theStandard-mode I2C-bus specification. Hs-mode can onlycommence after the following conditions (all of which arein F/S-mode):

1. START condition (S)

2. 8-bit master code (00001XXX)

3. not-acknowledge bit (A)

Figures 21 and 22 show this in more detail. This mastercode has two main functions:

• It allows arbitration and synchronization betweencompeting masters at F/S-mode speeds, resulting inone winning master.

• It indicates the beginning of an Hs-mode transfer.

Hs-mode master codes are reserved 8-bit codes, whichare not used for slave addressing or other purposes.Furthermore, as each master has its own unique mastercode, up to eight Hs-mode masters can be present on theone I2C-bus system (although master code 0000 1000should be reserved for test and diagnostic purposes). The

master code for an Hs-mode master device is softwareprogrammable and is chosen by the System Designer.

Arbitration and clock synchronization only take placeduring the transmission of the master code andnot-acknowledge bit (A), after which one winning masterremains active. The master code indicates to otherdevices that an Hs-mode transfer is to begin and theconnected devices must meet the Hs-mode specification.As no device is allowed to acknowledge the master code,the master code is followed by a not-acknowledge (A).

After the not-acknowledge bit (A), and the SCLH line hasbeen pulled-up to a HIGH level, the active master switchesto Hs-mode and enables (at time tH, see Fig.22) thecurrent-source pull-up circuit for the SCLH signal. As otherdevices can delay the serial transfer before tH by stretchingthe LOW period of the SCLH signal, the active master willenable its current-source pull-up circuit when all deviceshave released the SCLH line and the SCLH signal hasreached a HIGH level, thus speeding up the last part of therise time of the SCLH signal.

The active master then sends a repeated START condition(Sr) followed by a 7-bit slave address (or 10-bit slave

22



address, see Section 14) with a R/W bit address, andreceives an acknowledge bit (A) from the selected slave.

After each acknowledge bit (A) or not-acknowledge bit (A)the active master disables its current-source pull-upcircuit. This enables other devices to delay the serialtransfer by stretching the LOW period of the SCLH signal.The active master re-enables its current-source pull-upcircuit again when all devices have released and the

SCLH signal reaches a HIGH level, and so speeds up thelast part of the SCLH signal’s rise time.

Data transfer continues in Hs-mode after the nextrepeated START (Sr), and only switches back toF/S-mode after a STOP condition (P). To reduce theoverhead of the master code, it’s possible that a masterlinks a number of Hs-mode transfers, separated byrepeated START conditions (Sr).

Fig.21 Data transfer format in Hs-mode.


F/S-mode Hs-mode (current-source for SCLH enabled) F/S-mode

MSC616

AA A/ADATA

(n bytes + ack.)

S R/WMASTER CODE Sr SLAVE ADD.

Hs-mode continues

Sr SLAVE ADD.

P


MSC618

8-bit Master code 00001xxx AtH

t1S

F/S mode

Hs-modeIf P thenF/S mode

If Sr (dotted lines)then Hs-mode

1 6 7 8 9 6 7 8 91

1 2 to 5

2 to 52 to 5

6 7 8 9

SDAH

SCLH

SDAH

SCLH

tHtFS

Sr Sr Pn × (8-bit DATA + A/A)7-bit SLA R/W A

= MCS current source pull-up

= Rp resistor pull-upFig.22 A complete Hs-mode transfer.

23



13.3 Switching from F/S- to Hs-mode and back

After reset and initialization, Hs-mode devices must be inFast-mode (which is in effect F/S-mode as Fast-mode isdownward compatible with Standard-mode). EachHs-mode device can switch from Fast- to Hs-mode andback and is controlled by the serial transfer on the I2C-bus.

Before time t1 in Fig.22, each connected device operatesin Fast-mode. Between times t1 and tH (this time intervalcan be stretched by any device) each connected devicemust recognized the “S 00001XXX A” sequence and hasto switch its internal circuit from the Fast-mode setting tothe Hs-mode setting. Between times t1 and tH theconnected master and slave devices perform thisswitching by the following actions.

The active (winning) master:

1. Adapts its SDAH and SCLH input filters according tothe spike suppression requirement in Hs-mode.

2. Adapts the set-up and hold times according to theHs-mode requirements.

3. Adapts the slope control of its SDAH and SCLH outputstages according to the Hs-mode requirement.

4. Switches to the Hs-mode bit-rate, which is requiredafter time tH.

5. Enables the current source pull-up circuit of its SCLHoutput stage at time tH.

The non-active, or loosing masters:

1. Adapt their SDAH and SCLH input filters according tothe spike suppression requirement in Hs-mode.

2. Wait for a STOP condition to detect when the bus isfree again.

All slaves:

1. Adapt their SDAH and SCLH input filters according tothe spike suppression requirement in Hs-mode.

2. Adapt the set-up and hold times according to theHs-mode requirements. This requirement may alreadybe fulfilled by the adaptation of the input filters.

3. Adapt the slope control of their SDAH output stages, ifnecessary. For slave devices, slope control isapplicable for the SDAH output stage only and,depending on circuit tolerances, both the Fast- andHs-mode requirements may be fulfilled withoutswitching its internal circuit.

At time tFS in Fig.22, each connected device mustrecognize the STOP condition (P) and switch its internalcircuit from the Hs-mode setting back to the Fast-modesetting as present before time t1. This must be completedwithin the minimum bus free time as specified in Table 5according to the Fast-mode specification.

24



13.4 Hs-mode devices at lower speed modes

Hs-mode devices are fully downwards compatible, andcan be connected to an F/S-mode I2C-bus system (seeFig.23). As no master code will be transmitted in such aconfiguration, all Hs-mode master devices stay in

F/S-mode and communicate at F/S-mode speeds withtheir current-source disabled. The SDAH and SCLH pinsare used to connect to the F/S-mode bus system, allowingthe SDA and SCL pins (if present) on the Hs-mode masterdevice to be used for other functions.

Fig.23 Hs-mode devices at F/S-mode speed.


VSS VSS

Hs-modeSLAVE

SDAH SCLH

VSS

Hs-modeMASTER/SLAVE

SDAH SCLH SDA SCL

Rs Rs

Hs-modeSLAVE

SDAH SCLH

VSS

Rs Rs

F/S-modeMASTER/SLAVE

SDA SCL

Rs Rs

F/S-modeSLAVE

SDA SCL

VSS

Rs RsRs Rs

VDD

(1)

(2) (2)

(4) (4) (4)

(2) (2) (2) (2) (2) (2) (2) (2)

(3)

(1)

VDD

RpRp

SCL

SDA

MSC613

(1) Bridge not used. SDA and SCL may have an alternative function.


(3) The current-source pull-up circuit stays disabled.

(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCL.

13.5 Mixed speed modes on one serial bus system

If a system has a combination of Hs-, Fast- and/orStandard-mode devices, it’s possible, by using aninterconnection bridge, to have different bit rates betweendifferent devices (see Figs 24 and 25).

One bridge is required to connect/disconnect an Hs-modesection to/from an F/S-mode section at the appropriatetime. This bridge includes a level shift function that allowsdevices with different supply voltages to be connected. Forexample F/S-mode devices with a VDD2 of 5 V can beconnected to Hs-mode devices with a VDD1 of 3 V or less(i.e. where VDD2 ≥ VDD1), provided SDA and SCL pins are5 V tolerant. This bridge is incorporated in Hs-modemaster devices and is completely controlled by the serialsignals SDAH, SCLH, SDA and SCL. Such a bridge can beimplemented in any IC as an autonomous circuit.

TR1, TR2 and TR3 are N-channel transistors. TR1 andTR2 have a transfer gate function, and TR3 is an open-drain pull-down stage. If TR1 or TR2 are switched on theytransfer a LOW level in both directions, otherwise whenboth the drain and source rise to a HIGH level there will be

a high impedance between the drain and source of eachswitched on transistor. In the latter case, the transistors willact as a level shifter as SDAH and SCLH will be pulled-upto VDD1 and SDA and SCL will be pulled-up to VDD2

During F/S-mode speed, a bridge on one of the Hs-modemasters connects the SDAH and SCLH lines to thecorresponding SDA and SCL lines thus permittingHs-mode devices to communicate with F/S-mode devicesat slower speeds. Arbitration and synchronization ispossible during the total F/S-mode transfer between allconnected devices as described in Section 8. DuringHs-mode transfer, however, the bridge opens to separatethe two bus sections and allows Hs-mode devices tocommunicate with each other at 3.4 Mbit/s. Arbitrationbetween Hs-mode devices and F/S-mode devices is onlyperformed during the master code (00001XXX), andnormally won by one Hs-mode master as no slave addresshas four leading zeros. Other masters can win thearbitration only if they send a reserved 8-bit code(00000XXX). In such cases, the bridge remains closedand the transfer proceeds in F/S-mode. Table 3 gives thepossible communication speeds in such a system.

25



Table 3 Communication bit-rates in a mixed speed bus system

TRANSFERBETWEEN

SERIAL BUS SYSTEM CONFIGURATION

Hs + FAST +STANDARD

Hs + FAST Hs + STANDARDFAST +

STANDARD

Hs <–> Hs 0 to 3.4 Mbit/s 0 to 3.4 Mbit/s 0 to 3.4 Mbit/s –

Hs <–> Fast 0 to 100 kbit/s 0 to 400 kbit/s – –

Hs <–> Standard 0 to 100 kbit/s – 0 to 100 kbit/s –

Fast <–> Standard 0 to 100 kbit/s – – 0 to 100 kbit/s

Fast <–> Fast 0 to 100 kbit/s 0 to 400 kbit/s – 0 to 100 kbit/s

Standard <–> Standard 0 to 100 kbit/s – 0 to 100 kbit/s 0 to 100 kbit/s

MSC614

VSS

Hs-modeSLAVE

SDAH SCLH

VSS

Hs-modeMASTER/SLAVE

SDAH SCLH SDA SCL

Rs Rs

Hs-modeSLAVE

SDAH SCLH

VSS

Rs Rs

F/S-modeMASTER/SLAVE

SDA

SDAH

SCLH

SDA

SCL

SCL

VSS

VSS

Rs Rs

F/S-modeSLAVE

SDA SCL

VSS

Rs RsRs Rs

Rs

Rs

VDD

VSS

Hs-modeMASTER/SLAVE

VDD

VDD1

RpRp

VDD2

RpRp

SCLH

SDAH

MCSMCS(3)(3)

(2)(2) (2)(2) (2)(2) (2)(2)(2)(2)(2)

(4) (4) (4)

(2)

(1) (1)

BRIDGE

TR1

TR3

TR2

Fig.24 Bus system with transfer at Hs- and F/S-mode speeds.

(1) Bridge not used. SDA and SCL may have an alternative function.


(3) Only the active master can enable its current-source pull-up circuit.

(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCL or SCLH.

13.5.1 F/S-MODE TRANSFER IN A MIXED-SPEED BUS

SYSTEM

The bridge shown in Fig.24 interconnects correspondingserial bus lines, forming one serial bus system. As nomaster code (00001XXX) is transmitted, thecurrent-source pull-up circuits stay disabled and all outputstages are open-drain. All devices, including Hs-modedevices, communicate with each other according theprotocol, format and speed of the F/S-mode I2C-busspecification.

13.5.2 HS-MODE TRANSFER IN A MIXED-SPEED BUS

SYSTEM

Figure 25 shows the timing diagram of a completeHs-mode transfer, which is invoked by a START condition,a master code, and a not-acknowledge A (at F/S-modespeed). Although this timing diagram is split in two parts, itshould be viewed as one timing diagram were time point tHis a common point for both parts.

26




MSC611

8-bit Master code 00001xxx AtH

t1

t2

S

F/S mode

Hs-modeIf P thenF/S mode

If Sr (dotted lines)then Hs-mode

1 6 7 8 9

1 6 7 8 9 6 7 8 91

1 2 to 5

2 to 5

2 to 52 to 5

6 7 8 9

SDAH

SCLH

SDA

SCL

SDAH

SCLH

SDA

SCL

tHtFS

Sr Sr P

P

n × (8-bit DATA + A/A)7-bit SLA R/W A


= Rp resistor pull-up

Fig.25 A complete Hs-mode transfer in a mixed-speed bus system.

The master code is recognized by the bridge in the activeor non-active master (see Fig.24). The bridge performs thefollowing actions:

1. Between t1 and tH (see Fig.25), transistor TR1 opensto separate the SDAH and SDA lines, after whichtransistor TR3 closes to pull-down the SDA line to VSS.

2. When both SCLH and SCL become HIGH (tH inFig.25), transistor TR2 opens to separate the SCLHand SCL lines. TR2 must be opened before SCLHgoes LOW after Sr.

Hs-mode transfer starts after tH with a repeated STARTcondition (Sr). During Hs-mode transfer, the SCL linestays at a HIGH and the SDA line at a LOW steady-statelevel, and so is prepared for the transfer of a STOPcondition (P).

27



After each acknowledge (A) or not-acknowledge bit (A) theactive master disables its current-source pull-up circuit.This enables other devices to delay the serial transfer bystretching the LOW period of the SCLH signal. The activemaster re-enables its current-source pull-up circuit againwhen all devices are released and the SCLH signalreaches a HIGH level, and so speeds up the last part of theSCLH signal’s rise time. In irregular situations, F/S-modedevices can close the bridge (TR1 and TR2 closed, TR3open) at any time by pulling down the SCL line for at least1 µs, e.g. to recover from a bus hang-up.

Hs-mode finishes with a STOP condition and brings thebus system back into the F/S-mode. The active masterdisables its current-source MCS when the STOP condition(P) at SDAH is detected (tFS in Fig.25). The bridge alsorecognizes this STOP condition and takes the followingactions:

1. Transistor TR2 closes after tFS to connect SCLH withSCL; both of which are HIGH at this time. TransistorTR3 opens after tFS, which releases the SDA line andallows it to be pulled HIGH by the pull-up resister Rp.This is the STOP condition for the F/S-mode devices.TR3 must open fast enough to ensure the bus freetime between the STOP condition and the earliest nextSTART condition is according to the Fast-modespecification (see tBUF in Table 5).

2. When SDA reaches a HIGH (t2 in Fig.25) transistorTR1 closes to connect SDAH with SDA. (Note:interconnections are made when all lines are HIGH,thus preventing spikes on the bus lines). TR1 and TR2must be closed within the minimum bus free timeaccording to the Fast-mode specification (see tBUF inTable 5).

13.5.3 TIMING REQUIREMENTS FOR THE BRIDGE IN A

MIXED-SPEED BUS SYSTEM

It can be seen from Fig.25 that the actions of the bridge att1, tH and tFS must be so fast that it does not affect theSDAH and SCLH lines. Furthermore the bridge must meetthe related timing requirements of the Fast-modespecification for the SDA and SCL lines.

14 10-BIT ADDRESSING

This section describes 10-bit addressing and can bedisregarded if only 7-bit addressing is used.

10-bit addressing is compatible with, and can be combinedwith, 7-bit addressing. Using 10 bits for addressingexploits the reserved combination 1111XXX for the first

seven bits of the first byte following a START (S) orrepeated START (Sr) condition as explained in Section10.1. The 10-bit addressing does not affect the existing7-bit addressing. Devices with 7-bit and 10-bit addressescan be connected to the same I2C-bus, and both 7-bit and10-bit addressing can be used in F/S-mode and Hs-modesystems.

Although there are eight possible combinations of thereserved address bits 1111XXX, only the fourcombinations 11110XX are used for 10-bit addressing.The remaining four combinations 11111XX are reservedfor future I2C-bus enhancements.

14.1 Definition of bits in the first two bytes

The 10-bit slave address is formed from the first two bytesfollowing a START condition (S) or a repeated STARTcondition (Sr).

The first seven bits of the first byte are the combination11110XX of which the last two bits (XX) are the twomost-significant bits (MSBs) of the 10-bit address; theeighth bit of the first byte is the R/W bit that determines thedirection of the message. A ‘zero’ in the least significantposition of the first byte means that the master will writeinformation to a selected slave. A ‘one’ in this positionmeans that the master will read information from the slave.

If the R/W bit is ‘zero’, then the second byte contains theremaining 8 bits (XXXXXXXX) of the 10-bit address. If theR/W bit is ‘one’, then the next byte contains datatransmitted from a slave to a master.

14.2 Formats with 10-bit addresses

Various combinations of read/write formats are possiblewithin a transfer that includes 10-bit addressing. Possibledata transfer formats are:

• Master-transmitter transmits to slave-receiver with a10-bit slave address.The transfer direction is not changed (see Fig.26). Whena 10-bit address follows a START condition, each slavecompares the first seven bits of the first byte of the slaveaddress (11110XX) with its own address and tests if theeighth bit (R/W direction bit) is 0. It is possible that morethan one device will find a match and generate anacknowledge (A1). All slaves that found a match willcompare the eight bits of the second byte of the slaveaddress (XXXXXXXX) with their own addresses, butonly one slave will find a match and generate anacknowledge (A2). The matching slave will remainaddressed by the master until it receives a STOP

28



condition (P) or a repeated START condition (Sr)followed by a different slave address.

• Master-receiver reads slave- transmitter with a 10-bitslave address.The transfer direction is changed after the second R/Wbit (Fig.27). Up to and including acknowledge bit A2, theprocedure is the same as that described for amaster-transmitter addressing a slave-receiver. Afterthe repeated START condition (Sr), a matching slaveremembers that it was addressed before. This slavethen checks if the first seven bits of the first byte of theslave address following Sr are the same as they wereafter the START condition (S), and tests if the eighth(R/W) bit is 1. If there is a match, the slave considersthat it has been addressed as a transmitter andgenerates acknowledge A3. The slave-transmitterremains addressed until it receives a STOP condition(P) or until it receives another repeated STARTcondition (Sr) followed by a different slave address.After a repeated START condition (Sr), all the otherslave devices will also compare the first seven bits of thefirst byte of the slave address (11110XX) with their ownaddresses and test the eighth (R/W) bit. However, noneof them will be addressed because R/W = 1 (for 10-bitdevices), or the 11110XX slave address (for 7-bitdevices) does not match.

• Combined format. A master transmits data to a slaveand then reads data from the same slave (Fig.28). Thesame master occupies the bus all the time. The transferdirection is changed after the second R/W bit.

• Combined format. A master transmits data to one slaveand then transmits data to another slave (Fig.29). Thesame master occupies the bus all the time.

• Combined format. 10-bit and 7-bit addressing combinedin one serial transfer (Fig.30). After each STARTcondition (S), or each repeated START condition (Sr), a10-bit or 7-bit slave address can be transmitted.Figure 27 shows how a master-transmits data to a slavewith a 7-bit address and then transmits data to a secondslave with a 10-bit address. The same master occupiesthe bus all the time.

NOTES:

1. Combined formats can be used, for example, tocontrol a serial memory. During the first data byte, theinternal memory location has to be written. After theSTART condition and slave address is repeated, datacan be transferred.

2. All decisions on auto-increment or decrement ofpreviously accessed memory locations etc. are takenby the designer of the device.

3. Each byte is followed by an acknowledgment bit asindicated by the A or blocks in the sequence.

4. I2C-bus compatible devices must reset their bus logicon receipt of a START or repeated START conditionsuch that they all anticipate the sending of a slaveaddress.

Fig.26 A master-transmitter addresses a slave-receiver with a 10-bit address.


MBC613

R/W A1

(write)

A2 A A/A

1 1 1 1 0 X X 0

SLAVE ADDRESS1st 7 BITS

S DATA PDATASLAVE ADDRESS

2nd BYTE

Fig.27 A master-receiver addresses a slave-transmitter with a 10-bit address.


MBC614

R/W A1

(write)

A3 DATA DATAA2 R/W

(read)

1 1 1 1 0 X X 0 1 1 1 1 0 X X 1

AA PSrSLAVE ADDRESS

1st 7 BITSSLAVE ADDRESS

2nd BYTESLAVE ADDRESS

1st 7 BITSS

29



Fig.28 Combined format. A master addresses a slave with a 10-bit address,then transmits data to this slave and reads data from this slave.


MBC615

(write)

A DATA DATAR/W

(read)

R/W A A A A/A

1 1 1 1 0 X X

1 1 1 1 0 X X 1

0

SSLAVE ADDRESS

1st 7 BITSSLAVE ADDRESS

2nd BYTEDATA DATA

A PASr SLAVE ADDRESS1st 7 BITS


MBC616

(write)

A A A/A

(write)

A

A A A A/A

1 1 1 1 0 X X

1 1 1 1 0 X X

0

0

SSLAVE ADDRESS

1st 7 BITS R/WSLAVE ADDRESS

2nd BYTEDATA DATA

SrSLAVE ADDRESS

1st 7 BITS R/W 2nd BYTESLAVE ADDRESS DATA PDATA

Fig.29 Combined format. A master transmits data to two slaves, both with 10-bit addresses.

Fig.30 Combined format. A master transmits data to two slaves, one with a 7-bit address,and one with a 10-bit address.

dbook, full pagewidth

MBC617

R/W A

(write)

A A A/AR/W

(write)

A A/A

A

1 1 1 1 0 X X

0

0

SSLAVE ADDRESS

7 - BIT DATADATA

DATADATA PSLAVE ADDRESS

1st 7 BITS OF 10-BITSr SLAVE ADDRESS

2nd BYTE OF 10-BIT

30



14.3 General call address and start byte with 10-bitaddressing

The 10-bit addressing procedure for the I2C-bus is suchthat the first two bytes after the START condition (S)usually determine which slave will be selected by themaster. The exception is the “general call” address00000000 (H‘00’). Slave devices with 10-bit addressingwill react to a “general call” in the same way as slavedevices with 7-bit addressing (see Section 10.1.1).

Hardware masters can transmit their 10-bit address after a‘general call’. In this case, the ‘general call’ address byte isfollowed by two successive bytes containing the 10-bitaddress of the master-transmitter. The format is as shownin Fig.16 where the first DATA byte contains the eightleast-significant bits of the master address.

The START byte 00000001 (H‘01’) can precede the 10-bitaddressing in the same way as for 7-bit addressing (seeSection 10.1.2).

15 ELECTRICAL SPECIFICATIONS AND TIMING FORI/O STAGES AND BUS LINES

15.1 Standard- and Fast-mode devices

The I/O levels, I/O current, spike suppression, output slopecontrol and pin capacitance for F/S-mode I2C-bus devicesare given in Table 4. The I2C-bus timing characteristics,bus-line capacitance and noise margin are given inTable 5. Figure 31 shows the timing definitions for theI2C-bus.

The minimum HIGH and LOW periods of the SCL clockspecified in Table 5 determine the maximum bit transferrates of 100 kbit/s for Standard-mode devices and400 kbit/s for Fast-mode devices. Standard-mode andFast-mode I2C-bus devices must be able to followtransfers at their own maximum bit rates, either by beingable to transmit or receive at that speed or by applying theclock synchronization procedure described in Section 8which will force the master into a wait state and stretch theLOW period of the SCL signal. Of course, in the latter casethe bit transfer rate is reduced.

31



Table 4 Characteristics of the SDA and SCL I/O stages for F/S-mode I2C-bus devices

Notes

1. Devices that use non-standard supply voltages which do not conform to the intended I2C-bus system levels mustrelate their input levels to the VDD voltage to which the pull-up resistors Rp are connected.

2. Maximum VIH = VDDmax + 0.5 V.

3. Cb = capacitance of one bus line in pF.

4. The maximum tf for the SDA and SCL bus lines quoted in Table 5 (300 ns) is longer than the specified maximum toffor the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCLpins and the SDA/SCL bus lines as shown in Fig.36 without exceeding the maximum specified tf.

5. I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off.

n/a = not applicable

PARAMETER SYMBOLSTANDARD-MODE FAST-MODE

UNITMIN. MAX. MIN. MAX.

LOW level input voltage:fixed input levelsVDD-related input levels

VIL−0.5−0.5

1.50.3VDD

n/a−0.5

n/a0.3VDD

(1)VV

HIGH level input voltage:fixed input levelsVDD-related input levels

VIH3.00.7VDD

(2)

(2)n/a0.7VDD

(1)n/a(2)

VV

Hysteresis of Schmitt trigger inputs:VDD > 2 VVDD < 2 V

Vhysn/an/a

n/an/a

0.05VDD0.1VDD

––

VV

LOW level output voltage (open drain oropen collector) at 3 mA sink current:VDD > 2 VVDD < 2 V

VOL1VOL3

0n/a

0.4n/a

00

0.40.2VDD

VV

Output fall time from VIHmin to VILmax witha bus capacitance from 10 pF to 400 pF tof – 250(4) 20 + 0.1Cb

(3) 250(4) ns

Pulse width of spikes which must besuppressed by the input filter

tSP n/a n/a 0 50 ns

Input current each I/O pin with an inputvoltage between 0.1VDD and 0.9VDDmax

Ii −10 10 −10(5) 10(5) µA

Capacitance for each I/O pin Ci − 10 − 10 pF

32



Table 5 Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1)

Notes

1. All values referred to VIHmin and VILmax levels (see Table 4).

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCLsignal) to bridge the undefined region of the falling edge of SCL.

3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 nsmust then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line isreleased.

5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 areallowed.

n/a = not applicable

PARAMETER SYMBOLSTANDARD-MODE FAST-MODE


SCL clock frequency fSCL 0 100 0 400 kHz

Hold time (repeated) START condition.After this period, the first clock pulse isgenerated

tHD;STA 4.0 – 0.6 − µs

LOW period of the SCL clock tLOW 4.7 – 1.3 – µs

HIGH period of the SCL clock tHIGH 4.0 – 0.6 – µs

Set-up time for a repeated STARTcondition

tSU;STA 4.7 – 0.6 – µs

Data hold time:for CBUS compatible masters (see NOTE,Section 10.1.3)for I2C-bus devices

tHD;DAT

5.00(2)

–3.45(3)

–0(2)

–0.9(3)

µsµs

Data set-up time tSU;DAT 250 − 100(4) – ns

Rise time of both SDA and SCL signals tr – 1000 20 + 0.1Cb(5) 300 ns

Fall time of both SDA and SCL signals tf – 300 20 + 0.1Cb(5) 300 ns

Set-up time for STOP condition tSU;STO 4.0 – 0.6 – µs

Bus free time between a STOP andSTART condition

tBUF 4.7 – 1.3 – µs

Capacitive load for each bus line Cb – 400 – 400 pF

Noise margin at the LOW level for eachconnected device (including hysteresis)

VnL 0.1VDD – 0.1VDD – V

Noise margin at the HIGH level for eachconnected device (including hysteresis)

VnH 0.2VDD – 0.2VDD – V

33



Fig.31 Definition of timing for F/S-mode devices on the I2C-bus.


MSC610

S SrtSU;STOtSU;STAtHD;STA tHIGH

tLOW tSU;DAT

tHD;DAT

tf

SDA

SCL

P S

tBUFtrtftr tSPtHD;STA

34



15.2 Hs-mode devices

The I/O levels, I/O current, spike suppression, output slopecontrol and pin capacitance for I2C-bus Hs-mode devicesare given in Table 6. The noise margin for HIGH and LOWlevels on the bus lines are the same as specified forF/S-mode I2C-bus devices.

Figure 32 shows all timing parameters for the Hs-modetiming.The “normal” START condition S does not exist inHs-mode. Timing parameters for Address bits, R/W bit,Acknowledge bit and DATA bits are all the same. Only therising edge of the first SCLH clock signal after anacknowledge bit has an larger value because the externalRp has to pull-up SCLH without the help of the internalcurrent-source.

The Hs-mode timing parameters for the bus lines arespecified in Table 7. The minimum HIGH and LOW periodsand the maximum rise and fall times of the SCLH clocksignal determine the highest bit rate.

With an internally generated SCLH signal with LOW andHIGH level periods of 200 ns and 100 ns respectively, anHs-mode master can fulfil the timing requirements for theexternal SCLH clock pulses (taking the rise and fall timesinto account) for the maximum bit rate of 3.4 Mbit/s. So abasic frequency of 10 MHz, or a multiple of 10 MHz, canbe used by an Hs-mode master to generate the SCLHsignal. There are no limits for maximum HIGH and LOWperiods of the SCLH clock, and there is no limit for a lowestbit rate.

Timing parameters are independent for capacitive load upto 100 pF for each bus line allowing the maximum possiblebit rate of 3.4 Mbit/s. At a higher capacitive load on the buslines, the bit rate decreases gradually. The timingparameters for a capacitive bus load of 400 pF arespecified in Table 7, allowing a maximum bit rate of1.7 Mbit/s. For capacitive bus loads between 100 pF and400 pF, the timing parameters must be interpolatedlinearly. Rise and fall times are in accordance with themaximum propagation time of the transmission linesSDAH and SCLH to prevent reflections of the open ends.

35



Table 6 Characteristics of the SDAH, SCLH, SDA and SCL I/O stages for Hs-mode I2C-bus devices

Notes

1. Devices that use non-standard supply voltages which do not conform to the intended I2C-bus system levels mustrelate their input levels to the VDD voltage to which the pull-up resistors Rp are connected.

2. Devices that offer the level shift function must tolerate a maximum input voltage of 5.5 V at SDA and SCL.

3. For capacitive bus loads between 100 and 400 pF, the rise and fall time values must be linearly interpolated.

4. SDAH and SCLH I/O stages of Hs-mode slave devices must have floating outputs if their supply voltage has beenswitched off. Due to the current-source output circuit, which normally has a clipping diode to VDD, this requirementis not mandatory for the SCLH or the SDAH I/O stage of Hs-mode master devices. This means that the supply voltageof Hs-mode master devices cannot be switched off without affecting the SDAH and SCLH lines.

PARAMETER SYMBOLHs-MODE

UNITMIN. MAX.

LOW level input voltage VIL −0.5 0.3VDD(1) V

HIGH level input voltage VIH 0.7VDD(1) VDD + 0.5(2) V

Hysteresis of Schmitt trigger inputs Vhys 0.1VDD(1) – V

LOW level output voltage (open drain) at 3 mA sinkcurrent at SDAH, SDA and SCLH for:VDD > 2 VVDD < 2 V

VOL

00

0.40.2VDD

VV

On resistance of the transfer gate, for both currentdirections at VOL level between SDA and SDAH orSCL and SCLH at 3 mA

RonL − 50 Ω

On resistance of the transfer gate between SDA andSDAH or SCL and SCLH if both are at VDD level

RonH(2) 50 – kΩ

Pull-up current of the SCLH current-source. Applies forSCLH output levels between 0.3VDD and 0.7VDD

ICS 3 12 mA

Output rise time (current-source enabled) and fall timeat SCLH with a capacitive load from 10 to 100 pF

trCL, tfCL 10 40 ns

Output rise time (current-source enabled) and fall timeat SCLH with an external pull-up current source of 3 mAand a capacitive load of 400 pF

trCL(3), tfCL

(3) 20 80 ns

Output fall time at SDAH with a capacitive load from 10to 100 pF

tfDA 20 80 ns

Output fall time at SDAH with a capacitive load of400 pF

tfDA(3) 40 160 ns

Pulse width of spikes at SDAH and SCLH that must besuppressed by the input filters

tSP 0 10 ns

Input current each I/O pin with an input voltage between0.1VDD and 0.9VDD

Ii(4) – 10 µA

Capacitance for each I/O pin Ci – 10 pF

36



Table 7 Characteristics of the SDAH, SCLH, SDA and SCL bus lines for Hs-mode I2C-bus devices(1)

Notes

1. All values referred to VIHmin and VILmax levels (see Table 6).

2. For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.

3. A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edgeof the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signalminimizes this hold time.

PARAMETER SYMBOLCb = 100 pF MAX. Cb = 400 pF(2)


SCLH clock frequency fSCLH 0 3.4 0 1.7 MHz

Set-up time (repeated) START condition tSU;STA 160 − 320 − ns

Hold time (repeated) START condition tHD;STA 160 − 320 − ns

LOW period of the SCLH clock tLOW 160 − 320 − ns

HIGH period of the SCLH clock tHIGH 60 − 120 − ns

Data set-up time tSU;DAT 10 − 10 − ns

Data hold time tHD;DAT 0(3) 70 0(3) 150 ns

Rise time of SCLH signal trCL 10 40 20 80 ns

Rise time of SCLH signal afteracknowledge bit

trCL1 20 80 40 160 ns

Fall time of SCLH signal tfCL 10 40 20 80 ns

Rise time of SDAH signal trDA 20 80 40 160 ns

Fall time of SDAH signal tfDA 20 80 40 160 ns

Set-up time for STOP condition tSU;STO 160 − 320 − ns

Capacitive load for SDAH and SCLH lines Cb(2) − 100 − 400 pF

Capacitive load for SDAH + SDA line andSCLH + SCL line

Cb − 400 − 400 pF

Noise margin at the LOW level for eachconnected device (including hysteresis)

VnL 0.1VDD − 0.1VDD − V

Noise margin at the HIGH level for eachconnected device (including hysteresis)

VnH 0.2VDD − 0.2VDD − V

37



Fig.32 Definition of timing for Hs-mode devices on the I2C-bus.

(1) Rising edge of the first SCLH clock pulse after an acknowledge bit.


MGK871

SDAH

SrSr P

SCLH


= Rp resistor pull-up

tfDA

tSU;STA

trDA

tHD;STA tSU;DAT

trCL1

tLOW tHIGH

tHD;DAT

tLOWtHIGH

trCL

tfCL

tSU;STO

trCL1 (1)(1)

16 ELECTRICAL CONNECTIONS OF I 2C-BUSDEVICES TO THE BUS LINES

The electrical specifications for the I/Os of I2C-bus devicesand the characteristics of the bus lines connected to themare given in Section 15.

I2C-bus devices with fixed input levels of 1.5 V and 3 V caneach have their own appropriate supply voltage. Pull-upresistors must be connected to a 5 V ± 10% supply(Fig.33). I2C-bus devices with input levels related to VDDmust have one common supply line to which the pull-upresistor is also connected (Fig.34).

When devices with fixed input levels are mixed withdevices with input levels related to VDD, the latter devices

must be connected to one common supply line of5 V ± 10% and must have pull-up resistors connected totheir SDA and SCL pins as shown in Fig.35.

New Fast- and Hs-mode devices must have supplyvoltage related input levels as specified in Tables 4 and 6.

Input levels are defined in such a way that:

• The noise margin on the LOW level is 0.1VDD

• The noise margin on the HIGH level is 0.2VDD

• As shown in Fig.36, series resistors (RS) of e.g. 300 Ωcan be used for protection against high-voltage spikeson the SDA and SCL lines (resulting from the flash-overof a TV picture tube, for example).

38



Fig.33 Fixed input level devices connected to the I2C-bus.


MBC610

SDA

SCL

Rp NMOS

VDD1

Rp BiCMOS

VDD2

CMOS

VDD3

BIPOLAR

VDD4= 5 V 10 %

DD2 - 4V are device dependent (e.g. 12 V)

Fig.34 Devices with wide supply voltage range connected to the I2C-bus.


MBC625

SDA

SCL

Rp Rp CMOS CMOS CMOS CMOS

V DD = e.g. 3 V

Fig.35 Devices with input levels related to VDD (supply VDD1) mixed with fixed input level devices(supply VDD2,3) on the I2C-bus.


MBC626

SDA

SCL

Rp CMOSRp CMOS NMOS BIPOLAR

5 V 10 %

VDD1 =

V DD2 VDD3

VDD2,3 are device dependent (e.g. 12 V)

39



Fig.36 Series resistors (Rs) for protection against high-voltage spikes.


MBC627

SDA

SCL

Rp RpDEVICE

V DD

I C2

Rs Rs

DEVICE

V DD

I C2

Rs Rs

16.1 Maximum and minimum values of resistors R p

and Rs for Standard-mode I 2C-bus devices

For Standard-mode I2C-bus systems, the values ofresistors Rp and Rs in Fig.35 depend on the followingparameters:

• Supply voltage

• Bus capacitance

• Number of connected devices (input current + leakagecurrent).

The supply voltage limits the minimum value of resistor Rpdue to the specified minimum sink current of 3 mA atVOLmax = 0.4 V for the output stages. VDD as a function of

Rp min is shown in Fig.37. The required noise margin of0.1VDD for the LOW level, limits the maximum value of Rs.Rs max as a function of Rp is shown in Fig.38.

The bus capacitance is the total capacitance of wire,connections and pins. This capacitance limits themaximum value of Rp due to the specified rise time. Fig.39shows Rp max as a function of bus capacitance.

The maximum HIGH level input current of eachinput/output connection has a specified maximum value of10 µA. Due to the required noise margin of 0.2 VDD for theHIGH level, this input current limits the maximum value ofRp. This limit depends on VDD. The total HIGH level inputcurrent is shown as a function of Rp max in Fig.40.

40



Fig.37 Minimum value of Rp as a function of supplyvoltage with the value os Rs as a parameter.

handbook, halfpage

0 4 8 16

6

0

2

4

MBC628

12

minimumvalue Rp

(k )Ω

V (V)DD

5

3

1

R = 0S

max. R S

0 400 800 1600

10

0

8

MBC629

1200

6

4

2

maximum value R (Ω)s

15 V

10 V

Rp(k )Ω V = 2.5 VDD 5 V

Fig.38 Maximum value of Rs as a function of thevalue of Rp with supply voltage as a parameter.

Fig.39 Maximum value of Rp as a function of buscapacitance for a Standard-mode I2C-bus.

0 100 200 400

20

0

16

MBC635

300

12

8

4

bus capacitance (pF)

maximumvalue R

(kΩ)p

max. R

@ VDD= 5 VS

R = 0S

Fig.40 Total HIGH level input current as a functionof the maximum value of Rp with supply voltage as

a parameter.

0 200

20

0

4

MBC630

8

12

16

40 80 120 160total high level input current (µA)

maximumvalue Rp

(k )Ω

5 V

V = 15 VDD

2.5 V

10 V

41



17 APPLICATION INFORMATION

17.1 Slope-controlled output stages of Fast-modeI2C-bus devices

The electrical specifications for the I/Os of I2C-bus devicesand the characteristics of the bus lines connected to themare given in Section 15.

Figures 41 and 42 show examples of output stages withslope control in CMOS and bipolar technology. The slopeof the falling edge is defined by a Miller capacitor (C1) anda resistor (R1). The typical values for C1 and R1 areindicated on the diagrams. The wide tolerance for outputfall time tof given in Table 4 means that the design is notcritical. The fall time is only slightly influenced by theexternal bus load (Cb) and external pull-up resistor (Rp).However, the rise time (tr) specified in Table 5 is mainlydetermined by the bus load capacitance and the value ofthe pull-up resistor.

Fig.41 Slope-controlled output stage in CMOStechnology.

MBC618

P1

N1

R150 kΩ

N22 pF

to inputcircuit

C1

VDD

I/O

VSS

R p

Cb

VDD

VSS

SDA or SCLbus line

Fig.42 Slope-controlled output stage in bipolartechnology.

MBC619

R120 kΩ

to inputcircuit

5 pF

C1I/O

R p

Cb

VDD

VSS

Vp

GND

T1 T2

SDA or SCLbus line

17.2 Switched pull-up circuit for Fast-mode I 2C-busdevices

The supply voltage (VDD) and the maximum output LOWlevel determine the minimum value of pull-up resistor Rp(see Section 16.1). For example, with a supply voltage ofVDD = 5 V ± 10% and VOLmax = 0.4 V at 3 mA, Rp min =(5.5 − 0.4)/0.003 = 1.7 kΩ. As shown in Fig.43, this valueof Rp limits the maximum bus capacitance to about 200 pFto meet the maximum tr requirement of 300 ns. If the bushas a higher capacitance than this, a switched pull-upcircuit as shown in Fig.43 can be used.

The switched pull-up circuit in Fig.43 is for a supply voltageof VDD = 5 V ± 10% and a maximum capacitive load of400 pF. Since it is controlled by the bus levels, it needs noadditional switching control signals. During therising/falling edges, the bilateral switch in the HCT4066switches pull-up resistor Rp2 on/off at bus levels between0.8 V and 2.0 V. Combined resistors Rp1 and Rp2 canpull-up the bus line within the maximum specified rise time(tr) of 300 ns.

Series resistors Rs are optional. They protect the I/Ostages of the I2C-bus devices from high-voltage spikes onthe bus lines, and minimize crosstalk and undershoot ofthe bus line signals. The maximum value of Rs isdetermined by the maximum permitted voltage dropacross this resistor when the bus line is switched to theLOW level in order to switch off Rp2.

Fig.43 Switched pull-up circuit.

MBC620

1.3 kΩ

VCC

I/OCb

VDD

VSS

SDA or SCLbus line

NP

1/4 HCT4066

nZ GND

nE

nY5V 10 %

Rp2 1.7 kΩ R p1

100 Ω Rs

N

I/O

100 Ω Rs

N

400 pFmax.

FAST - MODE I C BUS DEVICES2

42



17.3 Wiring pattern of the bus lines

In general, the wiring must be so chosen that crosstalk andinterference to/from the bus lines is minimized. The buslines are most susceptible to crosstalk and interference atthe HIGH level because of the relatively high impedance ofthe pull-up devices.

If the length of the bus lines on a PCB or ribbon cableexceeds 10 cm and includes the VDD and VSS lines, thewiring pattern must be:

SDA

VDD

VSS

SCL

If only the VSS line is included, the wiring pattern must be:

SDA

VSS

SCL

These wiring patterns also result in identical capacitiveloads for the SDA and SCL lines. The VSS and VDD linescan be omitted if a PCB with a VSS and/or VDD layer isused.

If the bus lines are twisted-pairs, each bus line must betwisted with a VSS return. Alternatively, the SCL line can betwisted with a VSS return, and the SDA line twisted with aVDD return. In the latter case, capacitors must be used todecouple the VDD line to the VSS line at both ends of thetwisted pairs.

If the bus lines are shielded (shield connected to VSS),interference will be minimized. However, the shieldedcable must have low capacitive coupling between the SDAand SCL lines to minimize crosstalk.


and Rs for Fast-mode I 2C-bus devices

The maximum and minimum values for resistors Rp and Rsconnected to a Fast-mode I2C-bus can be determinedfrom Figs 37, 38 and 40 in Section 16.1. Because aFast-mode I2C-bus has faster rise times (tr) the maximumvalue of Rp as a function of bus capacitance is less thanthat shown in Fig.39 The replacement graph for Fig.39showing the maximum value of Rp as a function of buscapacitance (Cb) for a Fast-mode I2C-bus is given inFig.44.


and Rs for Hs-mode I 2C-bus devices

The maximum and minimum values for resistors Rp and Rsconnected to an Hs-mode I2C-bus can be calculated fromthe data in Tables 6 and 7. Many combinations of thesevalues are possible, owing to different rise and fall times,bus line loads, supply voltages, mixed speed systems andlevel shifting. Because of this, no further graphs areincluded in this specification.

18 BI-DIRECTIONAL LEVEL SHIFTER FORF/S-MODE I2C-BUS SYSTEMS

Present technology processes for integrated circuits withclearances of 0.5 µm and less, limit the maximum supplyvoltage and consequently the logic levels for the digital I/Osignals. To interface these lower voltage circuits withexisting 5 V devices a level shifter is needed. Forbi-directional bus systems as like the I2C-bus, such a levelshifter must also be bi-directional, without the need of adirection control signal(1). The simplest way to solve thisproblem is by connecting a discrete MOS-FET to each busline.

(1) US 5,689,196 granted; corresponding patent applicationspending.

Fig.44 Maximum value of Rp as a function of buscapacitance for meeting the tr max requirement for

a Fast-mode I2C-bus.

handbook, halfpage

0 100 200 400

7.5

0

6.0

MBC612

300

4.5

3.0

1.5

bus capacitance (pF)

maximumvalue R

(kΩ)p

max. R

@ VDD= 5 VS

R = 0S

43



In spite of its surprising simplicity, such a solution not onlyfulfils the requirement of bi-directional level shifting withouta direction control signal, it also:

• isolates a powered-down bus section from the rest of thebus system

• protects the “lower voltage” side against high voltagespikes from the “higher-voltage” side.

The bi-directional level shifter can be used for bothStandard-mode (up to100 kbit/s) or in Fast-mode (up to400 kbit/s) I2C-bus systems. It is not intended for Hs-modesystems, which may have a bridge with a level shiftingpossibility (see Section 13.5)

18.1 Connecting devices with different logic levels

Section 16 described how different voltage devices couldbe connected to the same bus by using pull-up resistors tothe supply voltage line. Although this is the simplestsolution, the lower voltage devices must be 5 V tolerant,which can make them more expensive to manufacture. Byusing a bi-directional level shifter, however, it’s possible to

interconnect two sections of an I2C-bus system, with eachsection having a different supply voltage and different logiclevels. Such a configuration is shown in Fig.45. The left“low-voltage” section has pull-up resistors and devicesconnected to a 3.3 V supply voltage, the right“high-voltage” section has pull-up resistors and devicesconnected to a 5 V supply voltage. The devices of eachsection have I/Os with supply voltage related logic inputlevels and an open drain output configuration.

The level shifter for each bus line is identical and consistsof one discrete N-channel enhancement MOS-FET; TR1for the serial data line SDA and TR2 for the serial clock lineSCL. The gates (g) have to be connected to the lowestsupply voltage VDD1, the sources (s) to the bus lines of the“lower-voltage” section, and the drains (d) to the bus linesof the “higher-voltage” section. Many MOS-FETs have thesubstrate internally connected with its source, if this is notthe case, an external connection should be made. EachMOS-FET has an integral diode (n-p junction) between thedrain and substrate.

Fig.45 Bi-directional level shifter circuit connecting two different voltage sections in an I2C-bus system.


MGK879

3.3 V DEVICE 3.3 V DEVICE 5 V DEVICE 5 V DEVICE

g

s d

g

s d

TR1

TR2

VDD2 = 5 V

SDA2

SCL2

VDD1 = 3.3 V

SDA1

SCL1

Rp Rp RpRp

44



18.1.1 OPERATION OF THE LEVEL SHIFTER

The following three states should be considered during theoperation of the level shifter:

1. No device is pulling down the bus line.The bus line of the “lower-voltage” section is pulled upby its pull-up resistors Rp to 3.3 V. The gate and thesource of the MOS-FET are both at 3.3 V, so its VGS isbelow the threshold voltage and the MOS-FET is notconducting. This allows the bus line at the“higher-voltage” section to be pulled up by its pull-upresistor Rp to 5 V. So the bus lines of both sections areHIGH, but at a different voltage level.

2. A 3.3 V device pulls down the bus line to a LOW level.The source of the MOS-FET also becomes LOW,while the gate stay at 3.3 V. VGS rises above thethreshold and the MOS-FET starts to conduct. The busline of the “higher-voltage” section is then also pulleddown to a LOW level by the 3.3 V device via theconducting MOS-FET. So the bus lines of bothsections go LOW to the same voltage level.

3. A 5 V device pulls down the bus line to a LOW level.The drain-substrate diode of the MOS-FET the“lower-voltage” section is pulled down until VGSpasses the threshold and the MOS-FET starts toconduct. The bus line of the “lower-voltage” section isthen further pulled down to a LOW level by the 5 Vdevice via the conducting MOS-FET. So the bus linesof both sections go LOW to the same voltage level.

The three states show that the logic levels are transferredin both directions of the bus system, independent of thedriving section. State 1 performs the level shift function.States 2 and 3 perform a “wired AND” function betweenthe bus lines of both sections as required by the I2C-busspecification.

Supply voltages other than 3.3 V for VDD1 and 5 V for VDD2can also be applied, e.g. 2 V for VDD1 and 10 V for VDD2 isfeasible. In normal operation VDD2 must be equal to orhigher than VDD1 (VDD2 is allowed to fall below VDD1 duringswitching power on/off).

45



19 DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS

Table 8 I2C evaluation boards

Table 9 Development tools for 80C51-based systems

Table 10 Development tools for 68000-based systems

Table 11 I2C analyzers

PRODUCT DESCRIPTION

OM4151/S87C00KSD

I2C-bus evaluation board with microcontroller, LCD, LED, Par. I/O, SRAM, EEPROM, Clock, DTMFgenerator, AD/DA conversion.

OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software

OM5500 Demo kit for the PCF2166 LCD driver and PCD3756A telecom microcontroller

PRODUCT DESCRIPTION

PDS51 A board-level, full featured, in-circuit emulator:RS232 interface to PC, universal motherboard, controlled via terminal emulation

PRODUCT DESCRIPTION

OM4160/2 Microcore-2 demonstration/evaluation board with SCC68070

OM4160/4 Microcore-4 demonstration/evaluation board with 90CE201

OM4160/5 Microcore-5 demonstration/evaluation board with 90CE301

PRODUCT DESCRIPTION

OM1022 PC I2C-bus analyzer with multi-master capability. Hardware and software (runs on IBM orcompatible PC) to experiment with and analyze the behaviour of the I2C-bus (includesdocumentation)

OM4777 Similar to OM1022 but for single-master systems only

PF8681 I2C-bus analyzer support package for the PM3580 logic analyzer family

46



20 SUPPORT LITERATURE

Table 12 Data handbooks

Table 13 Brochures/leaflets/lab. reports/books etc.

For more information about Philips Semiconductors and how we can help in your I2C-bus design, contact your nearestPhilips Semiconductors national organization from the address list of the back of this book, or visit our worldwide website at http://www.semiconductors.philips.com

TITLE ORDERING CODE

IC01: Semiconductors for Radio, Audio and CD/DVD Systems 9397 750 02453

IC02: Semiconductors for Television and Video Systems 9397 750 01989

IC03: Semiconductors for Wired Telecom Systems (parts a & b) 9397 750 00839,9397 750 00811

IC12: I2C Peripherals 9397 750 01647

IC14: 8048-based 8-bit microcontrollers 9398 652 40011

IC17: Semiconductors for wireless communications 9397 750 01002

IC18: Semiconductors for in-car electronics 9397 750 00418

IC19: ICs for data communications 9397 750 00138

IC20: 80C51-based 8-bit microcontrollers + Application notes and Development tools 9397 750 00963

IC22: Multimedia ICs 9397 750 02183

TITLE ORDERING CODE

Can you make the distance... with I2C-bus (information about the P82B715 I2C-busextender IC)

9397 750 00008

I2C-bus multi-master & single-master controller kits 9397 750 00953

Desktop video (CD-ROM) 9397 750 00644

80C51 core instructions quick reference 9398 510 76011

80C51 microcontroller selection guide 9397 750 01587

OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software 9398 706 98011

P90CL301 I2C driver routines AN94078

User manual of Microsoft Pascal I2C-bus driver (MICDRV4.OBJ) ETV/IR8833

C routines for the PCF8584 AN95068

Using the PCF8584 with non-specified timings and other frequently asked questions AN96040

User's guide to I2C-bus control programs ETV8835

The I2C-bus from theory to practice (book and disk) Author: D. ParetPublisher: WileyISBN: 0-471-96268-6

Bi-directional level shifter for I2C-bus and other systems AN97055

OM5500 demo kit for the PCF2166 LCD driver and PCD3756A telecom microcontroller 9397 750 00954

47



NOTES

48



NOTES

Documents

THE I C-BUS SPECIFICATION VERSION 2.0 DECEMBER 1998esd.cs.ucr.edu/webres/i2c20.pdf · NOTE: Neither the 100 kbit/s I2C-bus system nor the 100 kbit/s devices have been changed. 1.2