The front-end (Level-0) electronics interface

module for the LHCb RICH detectors

M. Adinolfi a,1, J.H. Bibby a, S. Brisbane a, V. Gibson b,N. Harnew a, M. Jones a, J. Libby a,∗, A. Powell a, C. Newby a,

N. Rotolo a, N. Smale a,2, L. Somerville a, P. Sullivan a,S. Topp-Jorgensen a, S. Wotton b, K. Wyllie c

aSub-department of Particle Physics, University of Oxford, Denys WilkinsonBuilding, Keble Road, Oxford, OX1 3RH, United Kingdom

bCavendish Laboratory, University of Cambridge, Madingley Road, CambridgeCB3 0HE, United Kingdom

cCERN, CH-1211, Geneva 23, Switzerland

Abstract

The front-end (Level-0) electronics interface module for the LHCb RICH detectorsis described. This module integrates the novel hybrid photon detectors, which in-strument the RICH detectors, to the LHCb DAQ, trigger and control systems. Thesystem operates at 40 MHz with a first-level trigger rate of 1 MHz. The moduledesign is presented and results are given for both laboratory and beam tests.

Key words:PACS:

1 Introduction

The LHCb experiment will study the decays of B hadrons produced in ppcollisions at a centre–of–mass energy of 14 TeV [1]. The LHC, operating with

∗ Corresponding authorEmail address: j.libby1@physics.ox.ac.uk (J. Libby).

1 Now at Department of Physics, University of Bristol, H. H. Wills Physics Labo-ratory, Tyndall Avenue, Bristol BS8 1TL, United Kingdom.2 Now at Max-Planck-Institut fur Kernphysik, Saupfercheckweg 1, 69117 Heidel-berg, Germany.

Preprint submitted to Elsevier Science 13 November 2006

an instantaneous luminosity of 2 × 1032 cm−2s−1 for 107 s/year, will produce1012 bb quark pairs. This large data sample will allow precise measurements ofCP–violating parameters in many different B–decay final states. These mea-surements will overconstrain the Standard Model description of CP violation;any discrepancies will be evidence for new physics.

The ability to identify charged hadrons is essential for reconstructing the Bdecays of interest. LHCb includes Ring Imaging Cerenkov (RICH) detectorsto identify π± and K± in the momentum range 1 to 100 GeV/c [2]. Thereare two RICH detectors with three radiators of differing refractive indices (n).RICH1 has an aerogel radiator (n − 1 = 0.03) and a gaseous C4F10 radiator(n−1 = 1.4×10−3), which cover the momentum ranges 1–10 GeV/c and up to65 GeV/c, respectively. RICH2 has a gaseous CF4 radiator (n−1 = 5×10−4)that covers the momentum range up to 100 GeV/c. Fig. 1 shows schematicsections of RICH1 and RICH2.

The emitted Cerenkov radiation is focussed and reflected out of the LHCbspectrometer acceptance by spherical and planar mirrors in both RICH detec-tors. The focal planes are instrumented with Hybrid Photon Detectors (HPDs)[3], which have both the high quantum efficiency and spatial precision re-quired to discriminate between π± and K± over the full momentum range. Aphotoelectron produced in the photocathode of the HPD is accelerated andelectrostatically focussed onto a silicon anode segmented into 8192 pixels ar-ranged into a 256 × 32 array. Each pixel is of dimension 62.5 × 500 µm. Thecustom-buit binary readout ASIC, LHCBPIX1 [4], is bump-bonded to the sil-icon anode and the complete assembly is encapsulated within the vacuum ofthe photodetector. The LHCBPIX1 ASIC pre–amplifies and shapes the siliconsignals; these are then discriminated at a rate of 40 MHz, which corresponds tothe bunch crossing frequency of the LHC. Any signals above the discriminatorthreshold are considered as hits. The LHCBPIX1 ASIC can operate in twomodes. One mode in which all 8192 pixels are readout and another in whichthe hits in an 8-pixel group are OR-ed together and the result is considered asa single hit. The second mode of operationleads to an effective 32 × 32 pixelarray with each pixel being of dimension 500×500 µm. The mode of operationwith 1024 pixels is used by LHCb to collect data because it gives the requiredspatial accuracy with reduced data size. The mode with 8192 pixels is usedfor calibration and diagnostic running.

Any hits are buffered within delay units in LHCBPIX1 ASIC for the fixed4 µs latency of the first level of the LHCb trigger (Level–0). Accepted dataare multiplexed into thirty-two 32-bit words for readout to the front–end elec-tronics (Level-0) interface module. The events are buffered in a 16 deep FirstIn First Out (FIFO) register which allows data from up to 16 consecutivebunch crossings to be accepted.

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A total of 484 HPDs are used in the RICH detectors, 196 in RICH1 and288 in RICH2. These are mounted in columns of 14 (16) HPDs in RICH1(RICH2). Each Level-0 interface module services two HPDs, therefore, 242are required to instrument both RICH detectors. Fig. 2 is a photograph of aRICH2 column.

The purpose of the Level-0 interface module is to read out a pair of HPDsand provide the interface to the timing and fast control (TFC) system, thedata acquisition (DAQ) system and the experimental control system (ECS). Inaddition, the interface module provides all low voltage (LV) to the LHCBPIX1ASIC and the silicon sensor of the HPD. Each Level-0 interface module issituated within the RICH detector volume; this leads to constraints on thedimensions of the board, its radiation tolerance and power consumption. Theintegrity of the fast signalling required by the 25 ns clock speeds must also bemaintained. The module integrates digital, analogue and optical components.

The paper is arranged as follows. Section 2 details the overall module designand the functionality of the components. Section 3 presents the results of lab-oratory and beam tests and the performance of components after irradiationis also discussed. The conclusions are given in Section 4.

2 Module design

A schematic of the Level–0 interface module is shown in Fig. 3. All the ma-jor blocks and their interconnections are shown. At the heart of the Level–0interface module is the Pixel Interface (PINT) FPGA. The other main compo-nents are the TTCrx ASIC, analogue PILOT ASIC, GOL serialiser ASIC andthe VCSEL (Vertical Cavity Surface Emitting Laser) optical transmitters. Allthese components, along with their integration, are described in the followingsections.

2.1 Board design and layout

The dimensions of the Level-0 board are constrained to be 165×1000×3 mm3

so that the module fits within the HPD columns along with the other services:the cards to provide LV power and HV power, and cooling plates. Fig. 4is a photograph of the Level-0 interface module; the density of componentintegration is visible. The components are mounted on an 18 layer printedcircuit board. Data speeds of up to 1.6 Gbits/s are handled by the board.Therefore, many lines are of controlled impedance and limited length to ensureclean rise times, signal source matching and synchronized digital timing across

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the whole board. Even with ground currents up to 6 A, the routing leads tonegligible noise being generated.

The I/O’s of the board are as follows. The connection to a HPD is madewith a pair of 50–way kapton cables which plug into a minimal insertion forceconnector 3 . There is an optical receiver 4 for the TFC signals and two VCSELoptical transmitters 5 for the data transfer to the DAQ system. There is alsoa 40-way IDC connector for the LV power supplies and ECS signals.

2.2 Pixel Interface FPGA

The PINT ASIC is an AX1000 fuse-link Field Programmable Gate Array(FPGA) 6 . The programmability of the PINT FPGA allows it to performthe major functionality of the Level-0 interface module as well as allowingflexibility of design. Fig. 5 is a schematic of the main blocks of the PINTFPGA along with their internal and external interconnections.

All HPD data pass through the PINT FPGA, which controls data formattingalong with the supervision of all the TFC and ECS signals. The PINT FPGAinterprets the global trigger and clock signals received by the TTCrx ASIC(see Section 2.3) to generate the data capture and readout commands for theLHCBPIX1 ASIC. The data packet from the LHCBPIX1 ASIC constitutesthirty-two 32-bit words to describe the hit pattern. These data are formattedwithin the PINT FPGA with the addition of two 32-bit header words thatcontain event and HPD identifiers, along with information about the statusof the Level-0 electronics. A 32-bit trailer word is added that contains theparity of each column of data; this allows downstream tests of the data trans-mission integrity to the DAQ system. The PINT also emulates the FIFO ofthe LHCBPIX1 ASIC, which is a 16 events deep, to attach the correct eventidentifiers to the data and to identify overflows. The FIFO also controls thedata readout sequence. Furthermore, the PINT can be configured to handledata from the LHCBPIX1 ASIC when operating in the mode with 8192 pixels,which is used for testing and diagnostic purposes.

The decoding of the TFC signals is also performed by the PINT FPGA to setthe run type and to generate calibration test sequences. The other settings of

3 FH12S-50S-0.5 SH, Hirose Elec. Co. Ltd., 1-11, Osaki 5-chome, Shinagawa-ku,Tokyo 141-8586.4 TRR-1B43-000, TrueLight Corporation, 21 Prosperity Road, I Hsinchu SciencePark, Hsin-Chu, Taiwan, R.O.C. 300.5 ULM-850-05-TN-USMBOP, U-L-M photonics GmbH, Lise-Meitner St. 13, D-89081 Ulm, Germany.6 AX1000, Actel Corporation, 2061 Stierlin Ct., Mountain View, CA 94043, USA.

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the Level-0 electronics are controlled by JTAG [5] signals that are provided tothe Level-0 module by the custom SPECs slave mezzanine board [6], which issituated on an auxiliary LV-supply board. The PINT FPGA interfaces thesesignals to the other components on the board, some of which have differingsignalling requirements: LVDS, CMOS and GTL. The configuration registersof the TTCrx ASIC are addressed with the I2C protocol [7]. The conversionof the JTAG to I2C signals is performed by the PINT FPGA. The status ofall Level-0 module components and the LHCBPIX1 ASICs can be read viathe PINT FPGA to the ECS. All flip-flops and latches are implemented withtriple-voting logic to reduce susceptibility to radiation-induced single-eventupsets (SEUs). Fig. 6 shows the gate-level triple-voting logic.

2.3 Timing and fast control

On the Level-0 module the TTCrx ASIC [8] decodes the TFC signals, receivedoptically, to construct the clock, Level-0 trigger, calibration and reset signals.The PINT FPGA distributes these signals to the external board componentsand the HPDs. The TTCrx ASIC generates two additional clock signals, whichcan be skewed with respect to the 40 MHz clock of the TFC system andeach other, by 104 ps increments. The Level-0 module uses one of the skewedclocks to generate the readout sequence of the LHCBPIX1 ASIC and the datatransmission to the DAQ system; the offset will be calibrated to maximise theefficiency of each board to compensate for timewalk effects of the LHCBPIX1ASICs, the time of flight of particles and cable delays. The other skewedclock is used to generate test pulses at the input to the preamplifier of theLHCBPIX1 ASIC for timing calibrations of the readout sequence.

2.4 Optical data output

The formatted data from the PINT FPGA are transferred serially at 1.6 Gbit/sto the rest of the DAQ system via 100 m of 50/125 µm multimode optical fibre.The 32-bit wide parallel data from the PINT FPGA are serialised by the GOLASIC [9,10]. The data are formatted for Gigabit-link Ethernet transmission,via fibre-optic cables, using 8-bit by 10-bit encoding [11]. The clock input tothe GOL ASICs has to have a peak-to-peak jitter less than 40 ps to maintaindata integrity. The 40 MHz clock from the TTCrx ASIC that drives the GOLASICs has a 300 ps peak-to-peak jitter, therefore, a special ”jitter filter” circuitis incorporated into the design. The radiation tolerant QPLL ASIC [12] isused, which is a quartz crystal based phase-locked loop. The layout aroundthe QPLL ASIC is designed to reduce power dissipation to a level that willnot increase the jitter above 40 ps.

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The serialised data from the GOL ASIC is transferred directly to the VCSELoptical transmitter. This commercial device has been developed in collabora-tion with LHCb to match the GOL ASIC outputs and to ensure an adequatelight intensity at the receiver of the off-detector DAQ electronics. Special cir-cuitry is introduced to power the GOL ASICs and VCSELs to prevent poorphase locking of the GOL ASIC and unacceptable biases being applied to theVCSEL when the board is first switched on. The radiation tolerant CRT4TASIC [10] was used to realise the solution.

2.5 Power supplies

Ten externally generated digital and analogue power supply voltages are routedfor either internal use or for the HPDs. The analogue and digital referenceplanes on the Level-0 interface module are kept separate so that the suppliescan be filtered locally. Particular care is taken in the supplies to the TTCrx,QPLL, GOL and LHCBPIX1 ASICs in which extraneous noise could severelydegrade the performance. The 80 V silicon bias for the silicon anode of theHPD is routed through the interface module and filtered with respect to ana-logue ground. The leakage current is less than 1 nA at the nominal bias.

The PILOT ASIC [13] provides reference voltages for the LHCBPIX1 ASICDigital-to-Analogue Convertors (DACs) that provide the GTL references, dis-criminator threshold references and test-pulse voltage levels. The PILOT ASICcontains a 10-bit Analogue-to-Digital Convertor (ADC) to monitor the refer-ence voltages. The PILOT ASIC also has four inputs that are used for temper-ature monitoring by platinum resistors placed on the PILOT ASIC itself, thePINT FPGA and the bases of the two HPDs. The PILOT ASIC is controlledwith JTAG via the PINT FPGA. The PINT FPGA also routes the resultsof the monitoring ADCs to the ECS. The PILOT ASICs are calibrated andtested in-house prior to mounting on the Level-0 interface modules.

3 Module performance

To ensure the Level-0 interface modules operate to the required specifications,extensive qualification tests have been performed. The modules have under-gone laboratory tests after production to ensure full functionality; these testsare described in Section 3.1. The PINT FPGA has undergone radiation tol-erance qualification and these studies are outlined in Section 3.2. Finally, theperformance of Level-0 interface modules when reading out Cerenkov photonsignals is discussed in Section 3.3.

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3.1 Laboratory tests

3.1.1 Signal–to–noise calibration

A crucial specification that the board must meet is to not contribute additionalnoise to that generated within the LHCBPIX1 ASIC, which would compromisethe detector efficiency. The silicon signals for a single photoelectron are around5,000 e−, though with charge sharing amongst pixels this can be reduced to aslow as 2,500 e− [4]. Therefore, the signal size to which the readout electronicsmust be sensitive is specified to be 2,000 e−, with a channel-to-channel spreadless than 200 e−. Furthermore, noise-induced signals should occur at a rateless than 1 in 10,000 events.

To measure the pixel thresholds in the LHCBPIX1 ASICs, 100,000 eventsat each threshold setting of the pixel discriminator are taken. The minimumthreshold which satisfies the noise-rate criterion is selected as the operatingvalue for the discriminator. The threshold in terms of number of e− is thencalibrated for each pixel using test pulses generated within the LHCBPIX1ASIC at the input to the preamplifier. The magnitude of the test pulse iscontrolled by two reference voltages provided by the PILOT ASIC. The signalis varied from 0 to 2000 e− in 100 e− increments. One hundred events aretaken at each point and the efficiency, defined as the number of hits registeredby the pixel divided by the number of calibration pulses sent, calculated.The efficiency as a function of test-pulse magnitude is fit with a cumulativeerror function 7 (S-curve). The mean of the S-curve, which corresponds to50% efficiency, is taken as the e− threshold of each pixel. An example of athreshold distribution for the 1,024 pixels read out with a Level-0 interfacemodule is shown in Fig. 7; the mean and r.m.s. of 1,027 and 77 e−, respectively,is typical.

A production cohort of fifty boards is tested in this manner and the r.m.s.’s ofpixel measurements from all the boards are compared. Any boards with r.m.s.greater than three standard deviations above the mean r.m.s. are considerednoisy and would be excluded from mounting in the RICH system. A distri-bution of threshold widths for one production cohort is shown in Fig. 8. Ofthe 150 boards produced and tested so far, none have been found to compro-mise the thresholds of the LHCBPIX1-ASIC discriminators. The one outlierin Fig. 8 was the result of a dry solder joint between the PCB and the Hiroseconnector. Once the joint was repaired, the board passed this test.

7 The cumulative error function is defined as erf(Q) =∫∞−∞

1√2πσ

e(Q−µ)2/2σ2dQ,

where Q is the charge and µ and σ are the mean and width, respectively.

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3.1.2 Optical transmission tests

As described in Section 2.4 the HPD data are transferred optically to therest of the LHCb DAQ system. The data transmission integrity has beenstudied in detail [14]. The optical attenuation of the 100 m long fibres providingthe Level–0 interface module-to-DAQ link has been measured, including allinterconnections of the fibres. Fig. 9 is a schematic of the link with all theinterconnections indicated. Fig. 10 shows the power output from the twelve100 m test links as a function of of the GOL ASIC current used to drivethe VCSEL; this current is approximately proportional to the optical powerproduced by the VCSEL. Also shown are the maximum and minimum powerexpected given the attenuation specification of the fibre and connections. Allmeasured values lie within the expected range. At the proposed operatingcurrent for the GOL ASIC of 2 mA, the optical power from the link is wellwithin the 0.03 to 0.65 mW dynamic range of the optical receiver 8 of theDAQ electronics.

The bit error rate (BER) in the data transmission is specified by LHCb re-quirements to be less than 10−12. The BER is measured by counting any errorsflagged by the 8-bit by 10-bit encoding with the DAQ electronics. Given thevery low rates of BER it is safe to assume that an error in an 8-bit word is in-duced by a single bit error. Tests were run with 1013 bits transferred from theLevel–0 module and the single bit errors counted. For the nominal transmittersettings no errors were detected. Running a test until such errors were observedmay have taken several weeks or months of continuous running. Therefore, toexpedite the tests, an optical attenuator was introduced to the fibre optic linkand the attenuation was increased until errors were observed. Measurementsof the BER at several different attenuations are shown in Fig. 11. The BERis then extrapolated linearly to the attenuation of the final system. This indi-cates that the BER for the Level–0 interface module optical link system willbe less than 10−15. This rate does not include any radiation induced errorswhich are discussed in Section 3.2.

3.1.3 Thermal testing

Four production boards were operated in an environmental control chamberto test their performance as a function of temperature. The temperature wascycled from ∼ 20◦C to 60◦C, well above the operational temperature of theRICH system, while the boards were transmitting test patterns generated bythe PINT FPGA. The cycles took 3 to 4 hours. No component failures or datatransmission errors occurred. One board had its temperature elevated to 80◦Cwhere it continued to operate successfully.

8 HFBR782, Agilent Technologies Inc. Headquarters, 395 Page Mill Road, PaloAlto, CA 94306, United States.

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Every Level-0 interface module produced is baked for 12 hours at 50◦ to stressthe board and accelerate early failure of weak solder joints on the board. Anyfailures are identified during the tests described in Section 3.1.1.

3.2 Radiation tests of the PINT FPGA

The anticipated maximum radiation dose to be received by a Level–0 interfacemodule is 20 krad over the 10 year lifetime of LHCb. The TTCrx, GOL,QPLL, CRT4T and PILOT ASICs have been tested successfully beyond thisdose. Hence, the PINT FPGA was the only component that had to be testedspecifically for the Level–0 interface module.

The ACTEL AX1000 FPGA, on which the PINT ASIC has been implemented,has been radiation tested with γ-ray and heavy ion exposures [15] and neutronexposures [16]. However, no tests had been performed with charged particles,which are expected to dominate the dose received in the LHCb RICH de-tectors. Therefore, a dedicated test was performed using a 68 MeV protonbeam at the Cyclotron Research Centre at Louvain-la-Neuve, Belgium. FourAX1000 FPGAs were programmed with three 8-bit 40-deep shift registers.These utilised around 25% of the devices’ flip-flops, which is equivalent to thefraction used by the PINT FPGA. The same test sequence was supplied to allthree registers at 40 MHz; two-third majority voting at the end of the registersidentified any radiation-induced single-event upsets (SEUs) in the device. Theintegrated dose received and the number of SEUs observed for each FPGAare given in Table 1. The results indicate that approximately one SEU wouldbe expected over the 10 year lifetime of LHCb. There were no pathologicalfailures of the FPGA observed during this test nor those presented in Refs.[15] and [16].

FPGA Integrated flux Dose SEUs

(1011 p/cm2) (kRad)

1 1.6 20 0

2 1.6 20 1

3 1.9 24 3

4 12.5 156 6

Total 17.6 220 10Table 1The results of the radiation tests of the ACTEL AX1000 fuse-link FPGA. The fluxof protons, the dose and number of SEUs observed for each FPGA and the totalare given.

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3.3 Beam tests

Pre-production boards with near identical layout and PINT FPGA firmware tothe final production module have been evaluated in a test beam. Photon signalsfrom a prototype Cerenkov detector in an identical configuration to RICH2were read out with HPDs operating at 40 MHz [17]. Three modules read outan array of six HPDs which detected Cerenkov rings from CERN PS beamsof 10 GeV/c charged pions and electrons . Both N2 and C4F10 were used asCerenkov radiators. The integrated distribution of HPD hits from ∼ 100, 000π± events with the C4F10 radiator is shown in Fig. 12; the superposition ofCerenkov rings is clearly visible. The number of photoelectrons per event fora N2 ring centred on a single HPD was found to be ∼ 10, which was in goodagreement with the number predicted by a GEANT4 [18] simulation. Thesetests demonstrate the excellent performance of the Level-0 interface modulein a realistic system environment.

4 Conclusions

The Level-0 interface module for the LHCb RICH detectors has been de-scribed. This module integrates a pair of HPDs to the LHCb DAQ and controlsystems. Rigorous laboratory tests show that the modules match the noise,radiation and data quality specifications. The excellent performance has beenfurther corroborated by beam tests where single Cerenkov photon signals havebeen detected efficiently.

5 Acknowledgements

The authors would like to thank Paolo Moreira for his assistance with theTTCrx, GOL and QPLL ASICs, Giovanni Anelli and David Price for assis-tance with the PILOT ASIC testing and our LHCb collaborators who workedon the RICH test beams. We would like to thank Vincent Bobillier, JorgenChristiansen and Richard Jacobsen for advice and assistance throughout thedesign and production of the module. We would also like to thank the review-ers of the Level-0 interface module design: Jorgen Christiansen (Chair), Vin-cent Bobillier, Dominique Breton, Guido Haefli, Paolo Moreira and RichardJacobsen.

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References

[1] LHCb Technical Proposal, LHCb Collaboration, CERN/LHCC 98-4 (1998);LHCb Reoptimized Detector Design and Performance, LHCb Collaboration,CERN/LHCC 2003-040 (2003).

[2] LHCb RICH Technical Design Report, LHCb Collaboration, CERN/LHCC2000-0037 (2000).

[3] M. Moritz et al., IEEE Trans. Nucl. Sci. NS-51 (3) (2004) 1060.

[4] K. Wyllie et al., Nucl. Instr. and Meth. A 530 (2004) 82.

[5] IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-ScanArchitecture,http://standards.ieee.org/reading/ieee/std public/description/testtech/1149.1-1990 desc.html.

[6] D. Breton et al., A Serial Protocol for the Experimental Controls System ofLHCb Experiment,https://lhcb.lal.in2p3.fr/Specs/Documentation/Specs4.0.pdf.

[7] I2C bus specification, Philips Semiconductors document, 9398 393 40011.

[8] J. Christiansen, A. Marchioro, P. Moreira and T. Toifl, TTCrx V3.0 ReferenceManual, CERN/EP/MIC 1999,http://ttc.web.cern.ch/TTC/TTCrx manual3.0.pdf

[9] P. Moreira et al., Proceedings of the 7th Workshop on Electronics for LHCexperiments, CERN-2001-005 (2001) 145.

[10] P. Moreira et al., GOL Reference Manual,http://proj-gol.web.cern.ch/proj%2Dgol/manuals/gol manual.pdf

[11] A. X. Widmer and P. A. Franaszek, IBM J. Res. Develop., Vol. 27 No. 5 (1983).

[12] P. Moreira, QPLL Manual,http://ttc.web.cern.ch/TTC/TTCmain.html#QPLL.

[13] A. Kluge et al., Proceedings of the 7th Workshop on Electronics for LHCexperiments, CERN-2001-005 (2001) 95.

[14] A. Powell, Overview of the RICH Optical Data Link and Evaluation of theOptical Attenuation, CERN-LHCb-2006-003 (2006).

[15] J. J. Wang et al., IEEE Trans. Nucl. Sci. NS-50 (6) (2003) 2158.

[16] iRoC Technologies, Overview of iRoC Technologies’ Report: Radiation Resultsof the SER Test of Actel, Xilinx and Altera FPGA instances.http://www.actel.com/documents/OverviewRadResultsIROC.pdf .

[17] M. Adinolfi, Nucl. Instr. and Meth. A553 (2005) 328.

[18] S. Agostinelli et al., Nucl. Instr. and Meth. A506 (2003) 250.

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(a) (b)

Fig. 1. Schematic sections of (a) RICH1 and (b) RICH 2.

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Fig. 2. A photograph of a fully integrated column for RICH 2. Eight Level-0 interfacemodules service sixteen HPDs. The modules are centrally placed and connecteddirectly to the HPDs, which are on the left-hand side of the column.

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GOL2 and

VCSEL

2×CRT4TPower supply

filters

AnaloguePILOT

Pixel InterfaceFPGA (PINT)

TTCrx

QPLL and crystal

GOL1 and

VCSEL

SPECSslave

Base powersupply

HPD1

HPD2

TFC fibre

Data fibres to

DAQ

DataTFC signalsPower supplies

JTAG control signalI2C control signal

Kaptoncables

Fig. 3. A schematic of the Level-0 interface module.

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Fig. 4. A photograph of the Level-0 interface module. The numerically labelled com-ponents are: (1) TTCrx ASIC, (2) GOL serialisers, (3) QPLL, (4) PINT FPGA, (5)Analogue PILOT ASIC, (6) Truelight optical receiver, (7) VCSEL optical transmit-ters and (8) Hirose connectors.

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HPD LHCBPIX1 ASICs

GOLs andoptical

transmitter

HPD LHCBPIX1 ASICs

PILOT: DAC and analogue

references

Power supplies and

filtersJTAG TTCrx

GOLs andoptical

transmitter

JTAG PINTinterface

JTAGlevel

translator

TTCdecoder

Calibrationand

trigger

FIFO with bunch

countersand event

type

Link test pattern

generation32×32-bit data words

and 3×32-bitheader and

trailer words

Latch

Control fromFIFO

Fig. 5. A schematic of the main blocks of the PINT FPGA and its interaction withother components. The key of connection types is given in Fig. 3

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A

B

C

Output

Fig. 6. The gate-level implementation of the triple-voting logic used by the PINT.If two or more of A, B and C are 1 then the output is 1.

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Mean 1027

RMS 76.59

)-Threshold (e600 700 800 900 1000 1100 1200 1300 1400

-E

ntr

ies

/ 20

e

0

20

40

60

80

100

120 Mean 1027

RMS 76.59

Fig. 7. The distribution of pixel thresholds measured for a typical LHCBPIX1 ASICand Level–0 interface module.

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/ ndf = 4.289 / 42χConstant 3.45± 17.79

Mean 5.91± 89.74

Sigma 5.79± 29.85

)-RMS (e0 50 100 150 200 250 300 350

-E

ntr

ies

/ 25e

0

5

10

15

20

25 / ndf = 4.289 / 42χConstant 3.45± 17.79

Mean 5.91± 89.74

Sigma 5.79± 29.85

Fig. 8. The distribution of threshold-distribution r.m.s’s for a cohort of productionLevel–0 interface boards tested with the same LHCBPIX1 ASIC.

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Fig. 9. A schematic of the fibre optic link between the Level-0 interface moduleand the off-detector electronics. The various interconnections and fibre lengths areindicated.

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0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 2 4 6 8 10 12

GOL Bias Current (mA)

Op

tic

al

Po

we

r(m

W)

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Channel 9

Channel 10

Channel 11

Channel 12

Max Theory

Min Theory

Fig. 10. The output power for 12 prototype optical data links including all connec-tions as a function of the GOL ASIC current that drives the VCSEL. The minimumand maximum expected from the component tolerances are also shown.

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Additional Attenuation (dB)-13.6 -13.4 -13.2 -13

log

(Bit

Err

or

Rat

e)

-13

-12.5

-12

-11.5

-11

-10.5

-10 / ndf 2χ 94.09 / 4Gradient 0.1384± -4.169 Offset 1.888± -67.14

/ ndf 2χ 94.09 / 4Gradient 0.1384± -4.169 Offset 1.888± -67.14

Fig. 11. The measured BER as a function of optical attenuation of the link for theAgilent receiver used on the RICH off-detector electronics.

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Fig. 12. The Cerenkov ring measured by an array of 6 HPDs read out with 3Level–0 interface modules. The radiator used was C4F10 and ∼ 100k π± events aresuperimposed.

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