IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-25, NO. 8, AUGUST 1978 1019

The Effect of Electrical Conduction of Si3N4 on the Discharge of MNOS Memory Transistors

Abstruct-It is proposed that the discharge of MNOS memory devices proceeds through a combination of direct tunneling from charge traps in the silicon nitride into the silicon, and charge migration through the nitride by a series of Poole-Frenkel emission-drift-capture events. The discharge of MNOS transistors calculated from this model by com- puter agrees well with experimental data taken at elevated temperatures on SOS/MNOS devices with LPCVD nitrides. Parameter values used in- dicate a very low value of electron mobility. The discharge rate at ele- vated temperatures is predicted to be sensitive to whether the silicon under the gate is in accumulation or depletion during the discharge.

E J Nd Nt T V x o x Xn k nt d 4 S

t ud

Uth X

a P

en €ox P

e

V

P 0

7

Q,

DEFINITION OF SYMBOLS Electric field. Electron current density. n-type doping density in silicon. Density of traps in nitride. Absolute temperature. Voltage relative to unperturbed regions of silicon. Thickness of oxide layer. Thickness of nitride layer. Boltzmann’s constant. Density of trapped electrons in nitride. Depth of initial charge distirbution in nitride. Magnitude of electronic charge. Electronic transport parameter in nitride. Time. Electron drift velocity. Thermal electron velocity, Depth coordinate in nitride. Tunneling parameter. Poole-Frenkel parameter. Dielectric permittivity. Dielectric permittivity in nitride. Dielectric permittivity in oxide. Electron mobility. Attempt to escape frequency in nitride traps. Charge density. Electron capture cross section. Tunneling time constant. Potential of traps in nitride.

I. INTRODUCTION

L UNDKVIST et al. [l] have explained the typical room- temperature charge decay of a thin-oxide MNOS memory

transistor on the basis of direct tunneling of trapped charges in

Manuscript received February 2, 1978; revised June 8, 1978. The authors are with the Electronics Research Center, Rockwell In-

ternational, Anaheim, CA 92803.

the nitride back into the silicon. In a subsequent paper, Lund- kvist et al. [2] attributed the increased rate of decay of stored charge observed at elevated temperatures to thermal excitation of the trapped carriers. This model neglected retrapping of the excited carriers and required a broad continuum of trap ener- gies to fit experimental data. However, measurements of elec- trical conduction in Si3N4 at elevated temperatures can be ac- counted for by Poole-Frenkel conduction with a single trap energy [3]. In addition, the observed behavior of the centroid of trapped charge versus write pulse conditions indicates charge migration through the nitride by a series of trapping- detrapping events [4], [SI. The work outlined herein uses a model combining direct tunneling plus strong trapping- detrapping effects from a single-trap level to fit MNOS dis- charge data taken at temperatures up to 280°C on SOS/MNOS devices with LPCVD nitride.

11. EXPERIMENT A. Device Fabrication

Retention measurements were made on p-channel, Al gate MNOS memory devices. These devices were fabricated on (loo), 0.7 pm thick, silicon-on-sapphire along with fixed threshold voltage MOS devices such as those used in the pe- ripheral decode circuitry of a nonvolatile EAROM. The pro- cess sequence was such that the MNOS memory devices were fabricated before the MOS devices, viz. the memory-gate-first (MGF) process. The gate dielectric layer of the memory de- vices consists of a 22 -8 silicon oxide layer grown thermally at 800°C in steam. An -400-8 silicon nitride layer is then de- posited at 825°C in a low pressure CVD system, where the re- actant gases used are dichloro silane and ammonia in the ratio of 1 : 5. The memory device gate dielectric layer is then capped by a 3000-4000-8 undoped silox layer, and MOS devices are fabricated with an 800-A thermal SiOz gate dielectric grown at 875°C in steam with 1.5 -percent HCl. The gate area of the MNOS device is then cleared of silox and the array is metal- lized with 1.2-pm aluminum evaporated from a resistance- heated source. The metal layer is then patterned to yield finished devices. Fully functional 1K EAROM arrays with radiation tolerance > 1 Mrad (Si) have been fabricated by the above process. The experimental measurements were made on MNOS devices in a test pattern. The channel lengths and widths of these devices were 6 and 10 pm, respectively, at mask level.

B. Experimental Measurements The experimental measurements were obtained by means of

a special MNOS tester designed and fabricated at Rockwell In-

0018-9383/78/0800-1019$00.75 0 1978 IEEE

IEEE TRLI,'~SACTIONS ON ELECTRON DEVICES, VOL. ED-25, NO. 8 , AUGUST 1978

Fig. 1. An example of threshold voltage decay data for p-'chumel MNOS memory transistors.

ternational. The tester can perform unattended retention ~scea- surements up to 3 X lo5 s, where the threshold vo1taq:o is monitored once every decade of time up to 1 s and twice every decade of time (at 1 and 3) thereafter. The threshold voltage is measured at a fixed source-to-drain current. These mea! nre- ments are stored internally in the tester and can be accessd by a calculator or a minicomputer that is compatible with the IEEE Specification 488 interface bus. A typical retenl-ion curve is shown in Fig. 1. The write pulse amplitude and witdth can be controlled from 10 to 40 V in 0.1-V increments and 0.5 pus to 1 ms in 0.5-ps increments, respectively. Folr 1:he present experiments, the threshold voltage of the MNOS de- vice was set by a series of l l symmetric 500-ps pulses of ,aI:er- nating polarity. The amplitude of the pulses was varied fr2m 2 1 to 30 V as required to generate a 5-V threshold voltage ,vin- dow (AV, = 5 V). The device was brought up to the reqtrked temperature before it was pulsed. The temperature was c3n- trolled to approximately +5"C over the range of 23 to 280'C.

Fig. 1 illustrates the discharge behavior of an MNOS Euan- sistor observed at room temperature and at 244°C with the gate at ground potential. At both temperatures there is a1 rleg- gligible decay of the negative turn-on threshold VT- whic!~. in- dicates that it is nearly equal to the intrinsic V, (= the V, with no electrically alterable charge in the gate insulator). The displacement between the two sets of initial threshold volt ages is attributed to a change in the intrinsic V, with temperatr.re. After an initial transition region, the 23°C result decays ;.in- early on a logarithmic time scale, which is as predicted b:y .he direct tunneling Lundkvist model of [ l ] . Assuming a s in~~ la r density of trapped electrons at 244"C, the Lundkvist mrdel would also predict a linear decay in logarithmic time at 241OC with the same slope as at 23°C. The experimental resu1t.h %re in agreement with this prior to about 1 s. The higher rat: of decay following 1 s at 244°C is attributed to thermally i s : : m -

ulated electrical conduction in the nitride.

111. THEORETICAL MODEL Electrical conduction in silicon nitride is believed to proce,ed

via the Poole-Frenkel effect [3] and has been studied in w n e detail by Svensson [6] . At equilibrum, the conduction ]pro- cess involves the injection of carriers at the electrodes and ihe establishment of an equilibrum distribution of trapped cl-uwge within the nitride. Equilibrium conduction measurement E in SiBN4 lead to a field-dependent conductivity consistent vl)th

the Poole-Frenkel effect. Treating the nitride as a conducting medium, with the measured field-dependent conductivity, pre- dicted a complete discharge within less than three decades of time after noticeable departure from the initial linear decay in log t , while the observed decay occurs over about six de- cades. Therefore, a nonequilibrium conduction process is as- sumed in which there is no carrier injection into the nitride, and the only source of carriers in the nitride is the region of trapped electrons formed adjacent to the oxide during writing. It is assumed that these electrons then migrate through the ni- tride toward either the oxide or the gate, depending on the local electric-field direction, by a series of Poole-Frenkel excitation-drift-capture events. The equations describing this process are given by Arnett [5] . Note that while in an equilib- rium conduction situation the deeper traps remain filled at low fields and the conduction process is dominated by shallow traps, in the absence of carrier injection at the electrodes, the deeper traps will be unoccupied throughout most of the ni- tride layer and are expected to dominate the electron migra- tion process, even at relatively low electric fields. The detrap- ping process for the deep traps is sensitive to the Poole-Frenkel effect.

The complete charge decay model is the result of combining the direct tunneling charge loss model with the trapping- detrapping charge redistribution process. The resulting equa- tion is

an,(x, t) J s at E

= - [N, - n&, t)] - n,(x, t ) ' v

The first term on the right-hand side represents capture of con- duction electrons, the second, Poole-Frenkel emission of trapped electrons, and the third, direct tunneling from the ni- tride traps into the silicon. In this equation, x is measured from the SiOz -Si3N4 interface towards the gate. The notation is as given in the Definition of Symbols, and is similar to that of [S I , with the exception of the use of the parameter s I outh/p and the assumption that ud = p E where p is the electron mo- bility. In the tunneling term, the parameters a and T~ are dis- cussed in [ l ] .

Equation (1) contains three variables depending on x and t , namely, n,, J , and E. Thus two other equations are required. The first of these is Poisson's equation

which must be integrated from the silicon depletion region to the gate. Within the silicon nitride, p = -qn,, while within the silicon depletion region, p = qNd. It is assumed that no charge trapping occurs in the oxide layer so that p = 0 in the oxide. Also, for the purposes of this calculation, it is assumed that any inversion charge in the silicon is uniformly distributed to a depth of 30 8. The calculation should be insensitive to this assumption for depths less than -100 A. The second equa- tion required is the continuity equation, which is applied to the nitride only, and must be modified from its usual form to

WILLIAMS AND BEGUWALA: EFFECT OF Si,N, ON THE DISCHARGE OF MNOS TRANSISTORS 1021

TABLE I MEASURED AND ASSUMED PARAMETER VALUES

F 5.6 x f/cm

€ox €

CI

B

3.4 x f/cm

1.04 x 1O-I’ f/cm

108 cm-1 Reference 1

3.06 x V1I2 cm Reference 6

xox 2 2 K ellipsometry

‘n

Nd

397 b 5 x 1016 cm-3

C-V curves

C-V curves

T Per expt. Thermocouple

TABLE I1 EFFECTS AND VALUES OF FITTED PARAMETERS

Parameter Effect Fitted Value

Nt Slope of room temperature result 1.5 x cm-3

Tl Initial curve of room temperature result 2 x 1.0~~ sec

d Initial value of AVT 33 P,

0 Temperature dependence 1 . 2 9 v

v Time where nitride conduction appears 5 x IO* sec-l

s=t av

IJ Slope of final portion of curve 2 x v * cm

account for the fact that an& includes the tunneling contri- bution which is not subject to continuity restrictions. Thus the appropriate equation is

In formulating this model, the assumption was made that the effect of conduction electrons on space charge can be neglected. In the present case, where we assume no carrier injection at the electrodes, the ratio of trapped-to-conduction charge will be equal to the ratio of capture probability to emission prob- ability for the traps. This ratio will be large if @ - p fl >> kT, which is expected to be true.

The boundary condition in (1) is simply the initial charge dis- tribution, which for the present work was taken as n,(x, 0) = Nt for x < d and nt (x , 0) = 0 for x > d. For Poisson’s equa- tion, the boundary conditions are that the voltage difference between the silicon and the gate equals the applied gate volt- age, which is zero for the present work, that the electric field is zero in the silicon at the edge of the depletion region, and that the voltages and electric displacements, D = e E, are con- tinuous at the interfaces. Finally, the boundary condition on

the continuity equation is that J = 0 at the value of x where E = 0 in the nitride.

The equations were solved on a digital computer by step in- tegration over x and t . The increments were linear in x and logarithmic in t . Errors arising from the use of logarithmic time intervals at large times were avoided by using the integral of (1) at constant J and E to calculate An, for a given A t . This procedure allows for the fact that at large times the change in n, at a given x is the net result of both capture and emission, and may be small even though the individual contri- butions of capture or emission would be unreasonably large if calculated independently.

IV. DATA FITTING Three classes of parameters are involved in fitting the com-

puter model to experimental data; namely, those whose values are assumed on the basis of published information, those whose values are measured independently for the present ex- periment, and those whose values are adjusted to fit the ex- perimental charge decay data. The assumed and measured values are summarized in Table I. The remaining six param- eters are required to fit the six independent features of the experimental data as shown in Table 11. Fig. 2 compares ex-

IEEE TR.4!VSACTIONS ON ELECTRON DEVICES, VOL. ED-25, NO. 8 , AUGUST 1918

0 23% a 154OC

* 205OC

A 244% 281%

h 0 ) 1 1 1 . 1 I I

10-2 I 102 104 106 108 1010 1012 t ISEC)

Fig. 2. Comparison of theory and experiment. Solid lines are cnlcu- 1atl:d using parameter values of Tables I and 11. Dotted line use 3 @ = 1.ZC V a t T = 154OC.

perinlental VT decay data at various temperatures with the theclletical curves calculated using the parameter values. of Tab.es I and 11. The experimental A V, points in Fig. 2 repre- sent the difference between positive and negative threshdds fzonl data such as those shown in Fig. 1. In fitting the data, it is asmmed that AV, is entirely due to trapped electrons.

V. DISCUSSION An excellent fit of the model predictions to the experin!c:n-

tal data was obtained at 205, 244, and 281OC. The dah\ at 154aC (also 175'C-not shown), however, almost coinaide with the 205°C result and require separate considerations s rch as temperature dependent 4 (or v ) to obtain a good fit. The value of q5 = 1.29 V which fits the higher temperature resldts agrees with Svensson's results and other independent measxli:e- ments [ 6 ] . The other values of fitted parameters are solr$.e- what interrelated with the measured or assumed parameter values. Thus if a different value of 6 had been assumed, a gc od fit wcmld have required different values of s and v . With ;this qualification, it is interesting to note that the value of s = ;: X

V cm implies a very low electron mobility (e.g., uta, = IO' cm/s and u = cm2 give p = 5 X cm2/V. s), which suggests the presence of shallow traps reducing the e!l:c- tron 'drift velocity. Note that in the absence of carrier inj:c- tion a.t the electrodes, the space charge in the shallow traps can be neglected relative to the deep traps if the shallow trap depth can be neglected relative to 4 - @@.

Another interesting result is the fitted value of the atterrpt to escape probability v = 5 X IO8 s-l. Based on Shocklleb- Read theory, it is expected that v = N, u Uth where N, is t i e effective density of states in the conduction band [SI. Us,ilg the above values of u and Uth and the typical value of N,: ;* l O I 9 (e.g., for Si,N, = 2.8 X IOl9 ~ m - ~ ) y i e l d s v = I(]" s-l , which is a factor of 200 higher than the fitted value. A L L - though the foregoing represents the most rigorous theoreticd estimate obtainable for v , being based on considerations that apply well to crystalline semiconductors, it is probably too much to expect these considerations to apply to a highly ells,- ordered insulator such as Si3N4, Consequently, we are left with no good theoretical basis for an expected value of v f o r Si3 N4.

The curves shown in Fig. 2 were calculated for the case wher;

Fig. 3. Predicted distributions of trapped electrons for a p-channel MNOS transistor after various times at 244OC.

1 6

!VOLTS1 DEPLRION - INVERSION

2 -

1 -

Fig. 4. Predicted effect of accumulation versus depletion on the thresh- old voltage decay of an MNOS transistor at 244OC.

the silicon surface under the gate insulator is depleted or in- verted. When the silicon surface is accumulated, the electric field in the nitride is such that the electrons trapped in the ni- tride migrate closer to the oxide where they are more likely to tunnel through to the silicon. On the other hand, for the depleted-inverted case, a significant portion of the charge is conducted towards the gate where it is less likely to tunnel into the silicon. Migration towards the gate is evident in the predicted charge distributions after various times at 24Cl0C shown in Fig. 3 for the depleted-inverted case. The effect of migration towards the gate on threshold voltage decay is shown in Fig. 4 where the accumulated and depleted-inverted predictions are compared at 244OC. The depleted-inverted case is seen to decay significantly less rapidly than the accumu- lated case. The effect is very similar to the use of a larger value of 6 or s. Experiments to verify the predicted depletion layer effects on charge decay at elevated temperatures have not yet been performed.

The foregoing method of calculation can easily be extended to other cases such as nonuniform initial charge distributions, nonuniform trap distributions, multiple trap levels, and trap- ping of both holes and electrons, as well as nonzero applied voltage, and carrier injection at the gate electrode. The present calculations have demonstrated, however, that a good fit to high-temperature charge decay data in MNOS memory transis-

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-25, NO. 8, AUGUST 1978 1023

tors can be obtained by adding electrical conduction effects in REFERENCES the form of migration of the trapped charge by a series of emission-drift-capture events to the direct tunneling model of tro~.,vol, 16, p, 811,1973. Lundkvist et al. [ 1 J . [2] L. Lundkvist, C. Svensson, and B. Hansson, Solid-state Electron.,

[3] S. M. Sze,J. Appl . Phys., vol. 38, p. 2951,1967. [4] K. Lehovec and A. Fedotowsky, IEEE Trans. Electron Devices,

[ l ] L. Lundkvist, I. Lundstrom, and C. Svensson, Solid-state Elec-

vol. 19, p. 221, 1976.

ACKNOWLEDGMENT The authors acknowledge helpful conversations withDr. A. J. [51 p. c, J. Appl. Ph,,s., 46, p. 5236, 1975.

Hughes, Dr. K. Lehovec, and Dr. F. B. Micheletti. [6] C. M. Svensson,J. Appl . Phys., vol. 48, p. 329,1977.

V O ~ . ED-24, p. 536,1917.

An Improved Model for the Charging Characteristics of a Dual-Dielectric (MNOS) Nonvolatile

Memory Device

Absfract-A computer-based model of the shift in the flat-band volt- age by an applied gate bias pulse of a dual-dielectric gate MNOS device is presented. The model is used to predict the write characteristics of an MNOS device where the thickness of the Si02 layer ranges between 20-30 A and that of the nitride layer between 300600 A. The results of the model are found to be in excellent agreement with experimental data. The shift in flat-band voltage versus applied symmetric gate bias pulses is presented with the thickness of the SiOz layer and the dura- tion of the pulse as parameters. The shift in the flat-band voltage of an MNOS transistor is related to the electric charge trapped at the SiOz- Si3N4 interface. This charge results from a discontinuity in the electric current in the Si02 and the Si3N4 layers. The current through the Si02 layer is based upon the expression derived by Murphy and Good and differs in its preexponential [ 9 ] term from the previously used modified Fowler-Nordheim tunnel current expressions. The electric current in the Si3N4 layer is considered to be primarily due to the Frenkel-Poole effect. However, for completeness, an ohmic current component for low electric fields and field emission current component for high electric fields are also included.

I. INTRODUCTION T H E THRESHOLD voltage VT of an MNOS (metal- 1 nitride-oxide semiconductor) transistor can be altered by

applying a suitable voltage pulse to the gate with respect to the drain, source, and body terminals of the transistor. The shift in threshold voltage A V, so achieved depends on the ampli- tude Vg and duration T~ of the applied gate bias, the ambient

Manuscript received February 2, 1978; revised June 7, 1978. The authors are with Electronics Research Center and Strategic

Systems Division, Rockwell International, Anaheim, CA 92803.

temperature of the device T, and the thickness of the silicon dioxide ( 3 i O z , hereafter referred to as oxide) to,, and sili- con nitride (=Si3N4, hereafter referred to as nitride) t,.

Several workers in the past have presented models to predict A V, as a function of Vg, r P , to,, and t,. Ross and Wallmark [ I ] postulate the existence of spatially distributed traps within the nitride with any energy level facing the silicon for- bidden energy gap at flat band. Under a positive applied bias, the charge tunnels directly from the silicon valence band to the traps in the nitride. Their model predicts correctly the ob- served logarithmic behavior of AVT versus T ~ ; however, the saturation of AVT as a function of Vg, which is observed ex- perimentally, is not apparent. This discrepancy arises because the current flow through the nitride is omitted. Frohman- Bentchkowsky and Lenzlinger [2] have presented a numerical model for the write characteristic of MNOS devices with to, 2 50 8. The expression for the electric current density Jox through the oxide layer has been simplified and this sim- plification is valid only when the carriers injected from the silicon tunnel into the conduction band of the oxide layer. However, during the charging of the oxide-nitride interface traps the electric field in the oxide layer changes and for to, < 30 8 the voltage drop across the oxide layer can be re- duced sufficiently such that the charge injected from the semi- conductor tunnels directly into the conduction band of the nitride layer. Svensson [3] has proposed a steady-state maxi- mum charge storage model for thin MNOS devices with to, = 15-30 A. A simple expression for the current through the nitride was used and the current through the oxide was of

0018-9383/78/0800-1023$00.75 0 1978 IEEE