The Development The Development of Psec-Resolution of Psec-Resolution TDC for Large Area TDC for Large Area

TOF SystemsTOF SystemsFukun TangFukun Tang

Enrico Fermi InstituteEnrico Fermi Institute

University of ChicagoUniversity of Chicago

With Karen Byrum and Gary Drake (ANL)

Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)

Major advances for TOF Major advances for TOF measurements:measurements:

Ability to simulate electronics and Ability to simulate electronics and systemssystems

to predict design performanceto predict design performance

Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll

Jitter on leading edge 0.86 psec

From H. Frisch

Requirement: Psec-Requirement: Psec-Resolution TDCResolution TDC

1 ps Resolution Time-to-Digital Converter!!!

Start

Stop500pS

Tw

MCP_PMT Output Signal

Reference Clock

Diagram of MCP-PMT Diagram of MCP-PMT ElectronicsElectronics

From HaroldFrom Harold

(1) TAC-ADC

Approaches & Approaches & PossibilitiesPossibilities

Receiver

“Zero”-walk Disc.

TAC Driver 11-bit ADC

2 Ghz PLL

4x1Ghz PLLREF_CLK

PMT

psFront-end (Timing Module Option #1)

1/4

TAC-ADC:TAC-ADC: Simulation Simulation ResultResult

Electronics with typical gate jitters Electronics with typical gate jitters << 1 psec<< 1 psec

(2) Time Stretcher

Approaches & PossibilitiesApproaches & Possibilities

Receiver

“Zero”-walk Disc.

Stretcher Driver 11-bit Counter

2 Ghz PLLREF_CLK

PMT

psFront-end (Timing Module Option #2)

1/4

CK5Ghz

Time Stretcher:Time Stretcher: Simulation ResultSimulation Result

1ns Time Interval (Input Signal)

Stretched Time = 274ns

(pedestal=74ns)

x200 Stretched Time Interval (Output Signal )

0 50ns 100ns 150ns 200ns 250ns 300ns

Ultimate Goal:Ultimate Goal: To build TDC with 1 pSec Resolution for Large Scale of To build TDC with 1 pSec Resolution for Large Scale of

Time-of-Flight Detector.Time-of-Flight Detector.Primary Goal:Primary Goal: To build 2-Ghz VCO, key module of PLL that generates the To build 2-Ghz VCO, key module of PLL that generates the

TDC reference signalTDC reference signal Cycle-to-Cycle Time-jitter < 1 psCycle-to-Cycle Time-jitter < 1 ps

To evaluate IHP SG25H1/M4M5 Technology for our To evaluate IHP SG25H1/M4M5 Technology for our applicationsapplications

To gain experiences on using Cadence tools To gain experiences on using Cadence tools (Virtuoso (Virtuoso Analog Environment)Analog Environment) Circuit DesignCircuit Design (VSE)(VSE) SimulationSimulation (Spectre)(Spectre) Chip LayoutChip Layout (VLE, XLE, VCAR)(VLE, XLE, VCAR) DRC and LVS Check DRC and LVS Check (Diva, Assura, Calibre)(Diva, Assura, Calibre) Parasitic ExtractionParasitic Extraction (Diva)(Diva) Post Layout SimulationPost Layout Simulation (Spectre)(Spectre) GDSIIGDSII Stream outStream out ValidationValidation Tape OutTape Out

VCO: Submission of Oct. VCO: Submission of Oct. 20062006

1N

Diagram of Phase-Diagram of Phase-Locked LoopLocked Loop

PD

CPI1

I2

LFVCO

Fref

F0

Uc

PD: Phase Detector

CP: Charge Pump

LF: Loop Filter

VCO: Voltage Controlled Oscillator

IHP (SG25H1) 0.25IHP (SG25H1) 0.25m m SiGe BiCMOS TechnologySiGe BiCMOS Technology 0.250.25m BiCMOS technology m BiCMOS technology 200Ghz NPN HBT (hetero-junction 200Ghz NPN HBT (hetero-junction

bipolar transistor)bipolar transistor) MIM Capacitors (layer2-layer3) ( MIM Capacitors (layer2-layer3) (

1f/1u1f/1u22 ) ) Inductors (layer3-layer4)Inductors (layer3-layer4) High dielectric stack for RF passive High dielectric stack for RF passive

componentcomponent 5 metal layers (Al) 5 metal layers (Al) Digital Library: DevelopingDigital Library: Developing

SG25 Process SG25 Process SpecificationSpecification

2-GHz BiCMOS VCO 2-GHz BiCMOS VCO SchematicSchematic

Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50Line Drivers

V-F Plot (3 model cases @ 27C-V-F Plot (3 model cases @ 27C-55C)55C)

Temperature: 27C-55CSupply: VDD=2.5V

VControl varied 0.18V

VControl

Frequency

BestBest -89.94 -89.94 dBc/HzdBc/Hz

TypicalTypical -89.58 -89.58 dBc/HzdBc/Hz

WorstWorst -89.90 -89.90 dBc/HzdBc/Hz

Phase Noise ( 3 model cases @ 27C)Phase Noise ( 3 model cases @ 27C)

Worst

Typical

Best

@100KHz offset

Temperature: 27CSupply: VDD=2.5V

Calculation of Cycle-to-Cycle Calculation of Cycle-to-Cycle JitterJitter

2-GHz VCO Performance 2-GHz VCO Performance SummarySummary (1) (1)

T=27C

f0 = 2 GHz phase noise: dBc/Hz@100K offset

VcontrVcontrolol

(V)(V)

ItailItail

(mA)(mA)VppVpp

(mV)(mV)IccIcc

(mA)(mA)PwPw

(mW(mW))

Phase Phase NoiseNoise

BestBest 1.541.54 10.10.9090

635635 33.33.9292

85.85.00

--89.789.7

55TypicTypicalal

1.601.60 8.88.833

573573 27.27.6363

67.67.55

--89.589.5

44WorsWorstt

1.681.68 7.47.488

524524 22.22.3131

56.56.00

--89.189.1

88

2-GHz VCO Performance 2-GHz VCO Performance Summary (2)Summary (2)

T=55C

f0 = 2 GHz phase noise: dBc/Hz@100K offset

VcontrVcontrolol

(V)(V)

ItailItail

(mA)(mA)VppVpp

(mV)(mV)Icc Icc

(mA)(mA)PwPw

(mW)(mW)Phase Phase NoiseNoise

BestBest 1.561.56 10.510.500

628628 34.434.488

86.386.3 --89.189.1

55TypicTypicalal

1.641.64 8.638.63 571571 28.028.055

70.070.0 --88.788.7

22WorstWorst 1.701.70 7.387.38 521521 22.522.5

7756.556.5 --

88.588.566

Virtuoso XL Layout ViewVirtuoso XL Layout View

Virtuoso Chip Assembly Virtuoso Chip Assembly Router ViewRouter View

Diagram of Post Layout Diagram of Post Layout SimulationSimulation

Schematic

Analog_extracted

Transit Analysis: Comparison of Transit Analysis: Comparison of Schematic and Post Layout Schematic and Post Layout

SimulationsSimulations

Schematic

Post Layout

Outputs@50 loads

V-F Plot: Comparison of Schematic V-F Plot: Comparison of Schematic and Post Layout Simulationsand Post Layout Simulations

Post Layout

Schematic

Vcontrol

Frequency

Phase Noise: Post Layout SimulationsPhase Noise: Post Layout SimulationsVDD=2.5V Temp.=27C, 55CVDD=2.5V Temp.=27C, 55C

Phase Noise @100KHZ offset

27C27C -89.40 -89.40 dBc/HzdBc/Hz

(Sch: -89.75)(Sch: -89.75)

55C55C -88.90 -88.90 dBc/HzdBc/Hz

(Sch: -89.15)(Sch: -89.15)

ConclusionConclusion

(1) VCO time-jitter met our (1) VCO time-jitter met our requirement.requirement.

(2) Post layout simulation matched (2) Post layout simulation matched schematic simulation very well.schematic simulation very well.

(3) Some problems we have (3) Some problems we have encountered with pcell library, encountered with pcell library, layout, DRC, LVS and auto-routing layout, DRC, LVS and auto-routing functionalities.functionalities.

(4)(4) Ready for October Submission.Ready for October Submission.