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TDA9103
DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
May 1996
SHRINK42(Plastic Package)
ORDER CODE : TDA9103
HORIZONTAL.DUAL PLL CONCEPT. 150kHz MAXIMUM FREQUENCY. SELF-ADAPTIVE (EX : 30 TO 85kHz). X-RAY PROTECTION INPUT. DC ADJUSTABLE DUTY-CYCLE. INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICA-TION. 4 OUTPUTS FOR S-CORRECTION.WIDE RANGE DC CONTROLLED H-POSITION.ON/OFF SWITCH (FOR PWR MANAGEMENT). TWO H-DRIVE POLARITIES
VERTICAL.VERTICAL RAMP GENERATOR. 50 TO 150Hz AGC LOOP. DC CONTROLLED V-AMP, V-POS, S-AMP AND S-CENTERING.ON/OFF SWITCH
B+ REGULATOR. INTERNAL PWM GENERATOR FOR B+ CURRENTMODE STEP-UP CONVERTER. DC ADJUSTABLE B+ VOLTAGE.OUTPUT PULSES SYNCHRONISED ON HORIZON-TAL FREQUENCY. INTERNAL MAXIMUM CURRENT LIMITATION
EWPCC.VERTICAL PARABOLA GENERATOR WITH DCCONTROLLED KEYSTONE AND AMPLITUDE
GENERAL.ACCEPT POS. OR NEG. H AND V SYNC POLARI-TIES. SEPARATED H AND V TTL INPUT. SAFETY BLANKING OUTPUT
DESCRIPTIONThe TDA9103 is a monolithic integrated circuit assembledin a 42 pins shrunk dual in line plastic package.This IC controls all the functions related to the horizontaland vertical deflection in multimodes or multisync monitors.As can be seen in the block diagram, the TDA9103 includesthe following functions :- Positive or Negative sync polarities,- Auto-sync horizontal processing,- H-PLL lock/unlock identification,- Auto-sync Vertical processing,- East/West signal processing block,- B+ controller,- Safety blanking output.
This IC, combined with TDA9205 (RGB preamp),STV9420/21 or 22 (O.S.D. processor), ST7271 (microcontroller) and TDA8172 (vertical booster), allows to real-ize very simple and high quality multimodes or multisyncmonitors.
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4
5
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8
9
10
11
12
42
41
40
39
38
37
36
35
34
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32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
24
23
22
ISENSE
COMP
REGIN
B+-ADJ
KEYST
E/W-AMP
E/WOUT
PLL1INHIB
VSYNC
V-POS
VDCOUT
V-AMP
VOUT
VS-CENT
VS-AMP
VCAP
VREF
VAGCCAP
VGND
SBLKOUT
B+OUT
PLL2C
H-DUTY
HFLY
HGND
HREF
S4
S3
S2
S1
C0
R0
PLL1F
HLOCK-CAP
FH-MIN
H-POS
XRAY-IN
HSYNC
VCC
GND
H-OUTEM
H-OUTCOL
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PIN CONNECTIONS
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PIN-OUT DESCRIPTION
Pin N° Name Function1 PLL2C Second PLL Loop Filter
2 H-DUTYDC Control of Horizontal Drive Output Pulse Duty-cycle.If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting acapacitor on this pin a soft-start function may be realized on h-drive output.
3 H-FLY Horizontal Flyback Input (positive Polarity)
4 H-GND Horizontal Section Ground. Must be connected only to components related to H blocks.
5 H-REF Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4
6 S4 Hor S-CAP Switching
7 S3 Hor S-CAP Switching
8 S2 Hor S-CAP Switching
9 S1 Hor S-CAP Switching
10 C0 Horizontal Oscillator Capacitor. To be connected to Pin 4.
11 R0 Horizontal Oscillator Resistor. To be connected to Pin 4.
12 PLL1F First PLL Loop Filter. To be connected to Pin 4.
13 HLOCK-CAPFirst PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency changedetected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, theduration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4.
14 FH-MIN DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltagegenerated by a resistor bridge connected between Pin 5 and 4.
15 H-POS DC Control for Horizontal Centering
16 XRAY-IN X-RAY Protection Input (with internal latch function)
17 H-SYNC TTL Horizontal Sync Input
18 VCC Supply Voltage (12V Typical)
19 GND Ground
20 H-OUTEM Horizontal Drive Output (emiter of internal transistor). See description on pages 15-16.
21 H-OUTCOL Horizontal Drive Output (open collector of internal transistor). See description on pages 15-16.
22 B+ OUT B+ PWM Regulator Output
23 SBLK OUT Safety Blanking Output. Activated during frequency changes, when X-RAY input istriggered or when VS is too low.
24 VGND Vertical Section Signal Ground
25 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26 VREF Vertical Section Reference Voltage
27 VCAP Vertical Sawtooth Generator Capacitor
28 VS-AMP DC Control of Vertical S Shape Amplitude
29 VS-CENT DC Control of Vertical S Centering
30 VOUT Vertical Ramp Output (with frequency independant amplitude and S-correction)
31 V-AMP DC Control of Vertical Amplitude Adjustment
32 VDCOUT Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output
33 V-POS DC Control of Vertical Position Adjustment
34 VSYNC Vertical TTL Sync Input
35 PLL1INHIB TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal)
36 E/WOUT East/West Pincushion Correction Parabola Output
37 E/W-AMP DC Control of East/West Pincushion Correction Amplitude
38 KEYST DC Control of Keystone Correction
39 B+ ADJ DC Control of B+ Adjustment
40 REGIN Regulation Input of B+ Control Loop
41 COMP B+ Error Amplifier Output for Frequency Compensation and Gain Setting
42 ISENSE Sensing of External B+ Switching Transistor Emiter Current
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1 23
4
5
6 910
16
17
1819
20
27 2829 30
36
3738
1112 131415 21
23
25 31 3233
34
35
INPUTINTERFACE
VERTICALOSCILLATOR
SCORRECTION
PARABOLAGENERATOR
INPUTINTERFACE
1st PHASECOMP
87
HFREQUENCY
OUTPUTBUFFER
PULSESHAPER
2nd PHASECOMP
LOCKDETECT
SAFETYPROCESSOR
26
24
BANDGAP
OutputsInhibition
VCC
39
40
22
41
42
EAR
S
VREF
TDA9103
VCO
H-VREF
V-VREF
SBLKOUT
B+-ADJ
IS ENSE
B+OUT
COMP
REGIN
E/WOUT
VSYNC
VGND
HREF
VREF
HGND
XRAY-IN
GN
D
VC
C
VA
GC
CA
P
VS
-CE
NT
VS
-AM
P
V-P
OS
V-A
MP
VO
UT
VD
CO
UT
KE
YS
T
E/W
-AM
P
VC
AP
PLL
1IN
HIB
H-P
OS
PLL
1F
R0
C0
FH
-MIN
HLO
CK
-CA
P
HF
LY
PLL
2C
H-D
UT
Y
H-O
UT
EM
H-O
UT
CO
L
S4
S3
S2
S1
HSYNC
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BLOCK DIAGRAM
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QUICK REFERENCE DATA
Parameter Value Unit
Horizontal Frequency Range 15 to 150 kHz
Autosynch Frequency Range (for Given R0, C0) 1 to 3.7 FH
± Hor Sync Polarity Input YES
Compatibility with Composite Sync on H-SYNC Input YES (1)
Lock/Unlock Identification on 1st PLL YES
DC Control for H-Position YES
X-RAY Protection YES
Hor DUTY Adjust YES
Stand-by Function YES
Hor S-CAP Switching Control YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility YES
Safety Blanking Output YES
Vertical Frequency Range 35 to 200 Hz
Vertical Autosync Range (for a Given Capacitor Value) 50 to 150 Hz
Vertical -S- Correction YES
Vertical -C- Correction YES
Vertical Amplitude Adjustment YES
Vertical Position Adjustment YES
Automatic B+ Adjustment Control Loop YES
B+ Adjustment YES
East/West Parabola Output YES
PCC (Pin Cushion Correction) Amplitude Adjustment YES
Keystone Adjustment YES
Reference Voltage YES (2)
Mode Detection NO
Dynamic Focus NO
Blanking Output NO
Notes : 1. See applicationdiagram.2. One for Horizontal section and one for Vertical section.
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HORIZONTAL SECTIONOperating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCO
R0min Oscillator Resistor Min Value Pin 11 6 kΩC0min Oscillator Capacitor Min Value Pin 10 390 pF
Fmax Maximum Oscillator Frequency 150 kHz
HsVR Horizontal Sync Input Voltage Range Pin 17 0 5.5 V
INPUT SECTION
MinD Minimum Input Pulses Duration Pin 17 0.7 µS
Mduty Maximum Input Signal Duty Cycle Pin 17 25 %
OUTPUT SECTION
I3m Maximum Input Peak Current on Pin 3 2 mA
IS1 to IS4 Maximum Current on S1 to S4 Outputs Pins 6 to 9 0.5 mA
VS1 to VS4 Maximum Voltage on S1 to S4 Outputs Pins 6 to 9 VCC V
HOI1 Horizontal Drive Output Max Current Pin 20, sourced current 20 mA
HOI2 Horizontal Drive Output Max Current Pin 21, sunk current 20 mA
DC CONTROL VOLTAGES
DCadj DC Voltage Range on DC Controls VREF-H = 8V, Pins 2-14-15 2 6 V
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ABSOLUTE MAX RATING
Symbol Parameter Value Unit
VCC Supply Voltage (Pin 18) 13.5 V
VIN Max Voltage on Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39Pin 3Pins 17, 34Pin 40Pin 42Pin 16
81.8688
5.5
V
VESD ESD SucceptibilityHuman Body Model, 100pF Discharge through 1.5kΩEIAJ Norm, 200pF Discharge through 0Ω
2300
kVV
Tstg Storage Temperature -40, +150 °C
Tj Max Operating Junction Temperature 150 °C
Toper Operating Temperature 0, +70 °C
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THERMAL DATA
Symbol Parameter Value Unit
Rth (j-a) Junction-Ambient Thermal Resistance Max. 65 °C/W
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Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin 18 10.8 12 13.2 V
ICC Supply Current Pin 18, See Figure 1 40 60 mA
VREF-H Reference Voltage for Horizontal Section Pin 5, I = 2mA 7.4 8 8.6 V
IREF-H Max Sourced Current on VREF-H Pin 5 5 mA
VREF-V Reference Voltage for Vertical Section Pin 26, I = 2mA 7.4 8 8.6 V
IREF-V Max Sourced Current on VREF-V Pin 26 5 mA
INPUT SECTION/PLL1
VINTH Hor Input Threshold Voltage Pin 17 Low level voltageHigh level voltage 2
0.8 VV
VVCO VCO Control Voltage Range VREF-H = 8V, Pin 12 1.6 6.2 V
VCOG VCO Gain, dF/dV Pin 12 R0 = 6.49kΩ, C0 = 680pF 15 kHz/V
Hph Horizontal Phase Adj Range (Pin 15) % of Hor period ±12.5 %
FFadj Free Running Frequency Adj Range (Pin 14) Without H-sync Signal ±20 %
S1th VCO Input Voltage for S1 Switching Pin 12 voltage, VREF-H = 8V 1.85 2 2.25 V
S2th VCO Input Voltage for S2 Switching Pin 12 voltage, VREF-H = 8V 2.25 2.4 2.65 V
S3th VCO Input Voltage for S3 Switching Pin 12 voltage, VREF-H = 8V 2.9 3 3.3 V
S4th VCO Input Voltage for S4 Switching Pin 12 voltage, VREF-H = 8V 3.5 3.7 3.9 V
F0 Free Running Frequency V14 = VREF/2R0 = 6.49kΩC0 = 680pF
23.5 25 27.5 kHz
VS1D toVS4D
Low Level Output Voltage on S1 to S4 Outputs Pins 6 to 9, I = 0.5mA 0.2 0.4 V
CR PLL1 Capture Range (F0 = 27kHz)Fh MinFh Max
See conditions on Figure 1
9428
kHz
PLLinh PLL 1 Inhibition (Pin 35)PLL ONPLL OFF
V35V35 2
0.8V
SECOND PLL AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage Pin 3 0.65 0.75 V
Hjit Horizontal Jitter 100 ppm
HDminHDmin
Minimum Hor Drive Output Duty-cycleMaximum Hor Drive Output Duty-cycle
Pin 20 or 21, V2 = 2VPin 20 or 21, V2 = 6V 45
3050
35 %%
HDvd Horizontal Drive Low Level Output Voltage V21-V20, Iout = 20mA,Pin 20 to GND
1.1 1.7 V
HDem Horizontal Drive High Level Output Voltage(output on Pin 20)
Pin 21 to VCC, IOUT = 20mA 9.5 10 V
XRAYth X-RAY Protection Input Threshold Voltage Pin 16 1.6 1.8 V
ISblkO Maximum Output Current on Safety BlankingOutput
I23 10 mA
VSblkO Low-Level Voltage on Safety Blanking Output V23 with I23 = 10mA 0.25 0.5 V
Vphi2 Internal Clamping Voltage on 2nd PLL LoopFilter Output (Pin 1)
VminVmax
1.63.2
VV
VOFF Pin 2 Threshold Voltage to Stop H-out, V-outB+out and to Activate S-BLK.OFF Modewhen V2 < VOFF
V2 1 V
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B+ SECTIONOperating Conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
EAOI Maximum Error Amplifier Output Current Sourced by Pin 41Sunk by Pin 41
0.52
mAmA
FeedRes Minimum Feedback Resistor Resistor between Pins 40and 41
5 kΩ
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Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
OLG Error Amplifier Open Loop Gain At low frequency(see Note 1)
85 dB
UGBW Unity Gain Bandwidth (see Note 1) 6 MHz
IRI Regulation Input Bias Current Current sourced byPin 40 (PNP base)
0.2 µA
EAOI Maximum Guaranted Error AmplifierOutput Current
Current sourced by Pin 41Current sunk by Pin 41
0.52
mAmA
CSG Current Sense Input Voltage Gain Pin 42 3
MCEth Max Curent Sense Input Threshold Voltage Pin 42 1.2 V
ISI Current Sense Input Bias Current Current sunk by Pin 42(NPN base)
1 µA
Tonmax Maximum External Power Transistor on Time % of H-period@ f0 = 27kHz
75 %
B+OSV B+ Output Low Level Saturation Voltage V22 with I22 = 10mA 0.25 V
IVREF Internal Reference Voltage On error amp (+) input forV39 = 4V
4.9 V
VREFADJ Internal Reference Voltage Adjustment Range 2V < V39 < 6V ±14 % 9103
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EAST WEST PARABOLA GENERATORElectrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Vsym Parabola Symetry Adjustment Capability (forKeystone Adjustment ; with Pin 38)
See Figure 2 ; internalvoltageV38 = 2VV38 = 4VV38 = 6V
3.23.53.8
V
Kadj Keystone Adjustment CapabilityB/A ratioA/B ratio
See Figure 2 ; V37 = 4VV38 = 2VV38 = 6V
2.32.0
Paramp Parabola Amplitude Adjustment CapabilityMaximum Amplitude on Pin 36Maximum Ratio between Max and Min
V38 = 4.3V, V28 = 2VV37 = 2V2V < V37 < 6V
3.32.4
3.83
4.3V
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VERTICAL SECTIONOperating Conditions
Symbol Parameter Test conditions Min. Typ. Max. UnitVSVR Vertical Sync Input Voltage Range On Pin 34 0 5.5 V
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Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. UnitIBIASP Pin 23-28-29 Bias Current (Current Sourced
by PNP Base)For V23-28-29 = 2V 2 µA
IBIASN Pin 31 Bias Current (Current Sunk by NPNBase)
For V31 = 6V 0.5 µA
VSth Vertical Sync Input Threshold Voltage Pin 34; High-levelLow-level
20.8
VV
VSBI Vertical Sync Input Bias Current (CurrentSourced by PNP Base)
V34 = 0.8V 1 µA
VRB Voltage at Ramp Bottom Point On Pin 27 2/8 VREF-V
VRT Voltage at Ramp Top Point (with Sync) On Pin 27 5/8 VREF-V
VRTF Voltage at Ramp Top Point (without Sync) On Pin 27 VRT-0.1 VIR27 Output Current Range on Pin 27 during
Ramp Charging Time. Current to ChargeCapacitor between Pin 27 and Ground
V28 = 2V (Note 2),2V < V27 < 5VMin currentMax current 100
15135
20 µAµA
VSW Minimum Vertical Sync Pulse Width Pin 34 5 µSVSmDut Vertical Sync Input Maximum Duty-cycle Pin 34 15 %VSTD Vertical Sawtooth Discharge Time Duration On Pin 27, with 150nF cap 85 µSVFRF Vertical Free Running Frequency (V28 = 2V) Measured on Pin 27
Cosc (Pin27) = 150nF100 Hz
ASFR AUTO-SYNC Frequency Range(see Note 3)
With C27 = 150nF ±5% 50 150 Hz
RATD Ramp Amplitude Thermal Drift On Pin 30 (see Note 1)(0°C < Tamb < 70°C)
100 ppm/°C
RAFD Ramp Amplitude Drift Versus Frequency V31 = 6V, C27 = 150nF50Hz < F < 120Hz
200 ppm/Hz
Rlin Ramp Linearity on Pin 27 ∆I27/I27 V28 = 2V, V25 = 4.3V2.5V < V27 < 4.5V
0.5 %
Rload Minimum Load on Pin 25 for less than 1%Vertical Amplitude Drift
50 MΩ
Vpos Vertical Position Adjustment Range Voltageon Pin 32
V33 = 2VV33 = 4VV33 = 6V 3.65
3.23.53.8
3.3 VVV
IVPOS Max Current on Vertical Position ControlOutput (Pin 32)
±2 mA
Vor Vertical Output Voltage Range (on Pin 30)(Peak to Peak Voltage on Pin 30)
V31 = 2VV31 = 4VV31 = 6V 3.75
234
2.2 VVV
VOUTDC DC Voltage on Vertical Output (Pin30) See Note 4 7/16 VREF-V
V0I Vertical Output Maximum Output Current On Pin 30 ±5 mAdVS Max Vertical S-Correction Amplitude
(V28 = 2V Inhibits S-CORR; V28 = 6V givesMaximum S-CORR) (see Figure 3)
∆V/V30pp at T/4∆V/V30pp at 3T/4
-4+4
%%
Ccorr C-Correction Adjustment Range Voltage onPin 27 for Maximum Slope on the Ramp(with S-Correction) (see Figure 4)
V29 = 2VV29 = 4VV29 = 6V
33.54
VVV
Notes : 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includescharacterization on batches comming from corners of our processes and also temperature characterization.
2. When 2V are applied on Pin 28 (Vertical S-Correction control), then the S-Correction is inhibited, consequently the sawtooth havea linear shape.
3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value onPin 27 and with a constant ramp amplitude.
4. Typically 3.5V for Vertical reference voltage typical value (8V).
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4.7kΩ
15kΩ
12
3
45
69
10
1617
1819
20
2728
2930
36
3738
1112
1314
1521
23
2531
3233
34
35
150n
F1%
470n
F1%
S5
12V
INP
UT
INT
ER
FA
CE
VE
RT
ICA
LO
SC
ILLA
TO
RS
CO
RR
EC
TIO
N
PA
RA
BO
LAG
EN
ER
AT
OR
10k Ω
INP
UT
INT
ER
FA
CE
1st
PH
AS
EC
OM
P
12V
15kΩ
15kΩ
15kΩ
87
S6
12V
HF
RE
QU
EN
CY
OU
TP
UT
BU
FF
ER
PU
LSE
SH
AP
ER
2nd
PH
AS
EC
OM
P
22nF
220n
F
6.49kΩ
680p
F1%
1.8kΩ
10nF
VC
O
LOC
KD
ET
EC
T
SA
FE
TY
PR
OC
ES
SO
R
2.2 µ
F
2.2µ
F26 24
H-V
RE
F
V-V
RE
F
BA
ND
GA
P
Out
puts
Inhi
bitio
nV
CC
39 4022 4142
EA
R S
VR
EF
12V
3.9k
Ω
47k Ω
470p
F
10k Ω
12V
4.7k
Ω
TD
A91
03
4.7
F
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Figure 1 : Testing Circuit
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A B
V36
V27
3.23.53.8
V38 = 2V
V38 = 4V
V38 = 6V
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Figure 2 : Keystone Adjustment
V30
∆V increase when V28 increase. ∆V = 0 when V28 = 0.
∆V
V30pp
0 T/4 T/2 T3T/4
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Figure 3 : S Amplitude Adjustment
V27
3.0V
3.5V
4.0V
0 T
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Figure 4 : C Correction Adjustment
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VREF
10kΩ
22kΩ DC Control Voltage
10kΩ
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Figure 5 : Example of Practical DC ControlVoltage Generation
Z
T
Z
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Figure 6
1.6VHSYNC
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Figure 7 : Input Structure
OPERATING DESCRIPTION
GENERAL CONSIDERATIONSPower Supply
The typical value of the power supply voltage VCCis 12V. Perfect operation is obtained if VCC is main-tained in the limits : 10.8V → 13.2V.In order to avoid erratic operation of the circuitduring the transient phase of VCC switching on, orswitching off, the value of VCC ismonitored and theoutputs of the circuit are inhibited if it is too low.In order tohave a very good powersupplyrejection,the circuit is internally powered by several internalvoltage references (The unique typical value ofwhich is 8V). Two of these voltage references areexternally accessible, one for the vertical part andone for the horizontal part. These voltage refer-ences can be used for the DC control voltagesapplied on the concerned pins by the way of poten-tiometers or digital to analog converters (DAC’s).Furthermore it is possible to filter the a.m. voltagereferences by the use of external capacitor con-nected to ground, in order to minimize the noiseand consequently the ”jitter” on vertical and hori-zontal output signals.
DC Control AdjustmentsThe circuit has 10 adjustmentcapabilities : 3 for thehorizontal part, 1 for the SMPS part, 2 for the E/Wcorrection, 4 for the vertical part.The corresponding inputs of the circuit has to bedriven with a DC voltage typically comprised be-tween 2 and 6V for a value of the internal voltagereference of 8V.More precisely, the control voltages have to bemaintained between VREF/4 and 3/4 ⋅ VREF. Theapplication of control voltages outside this range isnot dangerousfor the circuit but the good operationis not guaranted (except for Pin 2 : duty cycleadjusment. See outputs inhibition paragraph).
The input currents of the DC control inputs aretypically very low (about a few µA). Depending onthe internal structure of the inputs, the input cur-rents can be positive or negative (sink or source).
HORIZONTAL PARTInput section
The horizontal input is designed to be sensitive toTTL signals typically comprised between 0 and 5V.The typical threshold of this input is 1.6V. This inputstage uses an NPN differential stage and the inputcurrent is very low.Concerning the duty cycle of the input signal, thefollowing signals may be applied to the circuit.
Using internal integration, both signals are recog-nized on condition that Z/T ≤ 25%. Synchronisationoccurs on the leading edge of the rectified signal.The minimum value of Z is 0.7µs.
PLL1The PLL1 is composed of a phase comparator, anexternal filter and a Voltage Controlled Oscillator(VCO).The phase comparatoris a ”phase frequency” type,designed in CMOS technology. This kind of phasedetector avoids locking on false frequencies. It isfollowed by a ”charge pump”, composed of 2 cur-rent sources sink and source (I = 1mA typ.)
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The dynamic behaviour of the PLL is fixed by anexternal filter which integrates the current of thecharge pump. A ”CRC” filter is generally used.PLL1 is inhibited by applying a high level on Pin 35(PLLinhib)which is a TTLcompatible input.The inhibi-tion results from the opening of a switch located be-tween the charge pump and the filter (see Figure 8).The VCO uses an external RC network. It deliversa linear sawtooth obtained by charge and dis-charge of the capacitor, by a current proportionnalto the current in the resistor. typical thresholds ofsawtooth are 1.6V and 6.4V.
12
PLL1F
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Figure 9
C Lockdet
LOCKDET
COMP1INPUTINTERFACE
CHARGEPUMP
PLLINHIBITION
VCO
PHASEADJUST
Eini
HorizontalAdjust
R0 C0Filter
HorizontalInput
High
LowE2
3.2V
OSC
17
13 35 12 11 10
15
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Figure 8 : Principle Diagram
The control voltage of the VCO is typically com-prised between 1.6V and 6V. The theoretical fre-quency range of this VCO is in the ratio 1 → 3.75,but due to spread and thermal drift of externalcomponents and the circuit itself, the effective fre-quency range has to be smaller (e.g. 30kHz →82kHz). Inthe absenceof synchronisationsignal thecontrol voltage is equal to 1.6V typ. and the VCOoscillates on its lowest frequency (free frequency).Thesynchro frequencyhas tobealways higher thanthe free frequency and a margin has to be taken. Asan example for a synchro range from 30kHz to82kHz, the suggested free frequency is 27kHz. Tocompensate for the spread of external componentsand of the circuit itself, the free frequency may beadjusted by a DC voltage on Pin 14 (Fmin adjust)(see Figure10 for details).
The PLL1 ensures the coincidence between theleading edge of the synchro signal and a phasereference obtained by comparison between thesawtooth of the VCO and an internal DC voltageadjustable between 2.4V and 4V (by Pin 15). So a±45° phase adjustment is possible.
11
12
14
LoopFil ter
R0
(0.8V < a < 1.2V)
FHMINADJ
1.6V
6.4V
10
C0
6.4V
1.6V0 0.75T T
RSFLIP FLOP
a
(1.6V < V < 6V)12
I0
I0
2
4 I0
2
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EP
S
Figure 10 : Details of VCO and Fhmin Adjustment
TDA9103
12/27
SMPS OutputInhibition
-
+
VCC 30
REF 30
XRAY 30
VCCoff 30
S
RQ
-
+
H-duty Cycle 30
1V 30
-
+
Flyback 30
0.7V 30
30PLL-Unloocked
VCC Checking
XRAY Protection
Inhibition
H OutputInhibition
V OutputInhibition
Blanking
9103
-21.
AI
Figure 11 : Safety Functions Block Diagram
20kΩ
220nF
13FromPhaseComparator
NOR1A
6.5VB NOR2 23 SBLK OUT
H-Lock CAP
9103
-59.
EP
S
Figure 12 : LOCK/UNLOCK Block Diagram
The TDA9103 also includes a LOCK/UNLOCKidentification block which sense in real-timewheather the PLL is locked on the incomminghorizontal sync signal or not. Theresulting informa-tion is available on safety blanking output (Pin 23)where it is mixed with others information (see Fig-ure 11). The block diagram of the LOCK/UNLOCKfunction is described in Figure 12.The NOR1 gate is receiving the phase comparatoroutput pulses (which also drives the charge pump).When the PLL is locked, on point A there is a verysmall negative pulse (100ns) at each horizontalcycle, so after R-C filter, there is a high level on Pin13 which force SBLK to high level (provided otherinputs on NOR2 are also at low level).When the PLL is unlocked, the 100ns negativepulse onA becomesmuch largerand consequentlythe average level on Pin 13 will decrease. When itreaches 6.5V, point B goes to high level forcingNOR2 open collector output to ”0”.
The status of Pin 13 is approximately the following :- Near 0V when there is no H-SYNC,- Between0 and 4V with H-SYNC frequency differ-
H Osc Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V2.4V<Vb<4V
0.75T 0.25T
Phase REF1 is obtained by comparison between the sawtoothand a DC voltage adjustable between 2.4V and 4V. The PLL1ensures the exact coincidence between the signals phase REFand HSYNS. A ± 45° phase adjustment is possible.
9103
-16.
AI
Figure 13 : PLL1 Timing Diagram
ent from VCO,- Between 4 and 8V when H-SYNC frequency
= VCO frequency but not in phase,- Near to 8V when PLL is locked.It is important to notice that Pin 13 is not an outputpin and must only be used for filtering purpose (seeFigure 12).
TDA9103
13/27
C Lockdet
LOCKDET
COMP1INPUT INTERFACE
CHARGE PUMP
PLL INHIBITION
VCO
PHASE ADJUST
Eini
Horizontal Adjust
R0 C0Filter
Freq Adjust
High
LowE2
3.2V
OSC
FAJUST
HFREQ
GENPULSECOMP2CHARGE PUMP
High
Low
RAP CYC
E2
E1
Adjust Rapcyc
Cap PH12
PWM LOGI PWM BUFFER
FLYBACK
SortCOLL
Flyback
SortEM
VBVA
Horizontal Input
13 35 12 11 10
17
2 1
15
14
3
21
20
9103
-15.
AI
Figure 14 : Dual PLL Block Diagram
PLL2
The PLL2 ensures the coincidence between theleading edge of the shaped flyback signal and aphase reference signal obtained by comparison ofthe sawtoothof the VCO anda constant DCvoltage(3.2V) (see Figure 15).
The phase comparatorof PLL2 is similar to the oneof PLL1, it is followed by a charge pump with a
20kΩ
400ΩQ1
GND 0V
3HFLY
9103
-11.
AI
Figure 16 : Flyback Input Electrical DiagramH Osc Sawtooth
Phase REF2
H Drive
1.6V
3.2V
6.4V
0.75T 0.25T
Ts
Duty Cycle
Shapped Flyback
Flyback
9103
-57.
AI
Phase REF2is obtainedby comparison betweenthe sawtooth anda 3.2V (constant). The PLL2 ensures the exact coincidencebetween the signals phase REF2 and the flyback signal. The dutycycle of H-drive is adjustable between 30% and 50%.
Figure 15 : PLL2 Timing Diagram
±0.5mA (typ.) output current.The flyback input iscomposedofan NPN transistor.This input has to be current driven. The maximumrecommanded input current is 2mA (see Fig-ure 16).
Output SectionThe H-drive signal is transmitted to the outputthrough a shaping block ensuring a duty cycleadjustable from 30% to 50%. In order to ensure areliable operation of the scanning power part, theoutput is inhibited in the following circumstances :- VCC too low.- Xray protection activated.- During the flyback.- Output voluntarily inhibited.The output stage is composed of a Darlington NPNbipolar transistor. Both the collector and the emitterare accessible.
TDA9103
14/27
H-DRIVE
VCC21
20
VCC
H-DRIVE
21
20
VCC
9103
-12.
AI/
9103
-13.
AI
Figure 17 : Output stage simplified diagram,showing the two possibilities ofconnection
The outputDarlington is in off-state when thepowerscanning transistor is also in off-state.The maximum output current is 20mA, and thecorrespondingvoltage dropof the outputdarlingtonis 1.1V typically.It is evident that the power scanning transistorcannot be directly driven by the integrated circuit.An interface has to be designed betweenthe circuitand the power transistor which can be of bipolar orMOS type.
Outputs inhibition : the application of a voltagelower than 1V (typ.) on Pin 2 (duty cycle adjust)inhibits the horizontal, vertical and SMPS outputs.This is not memorised.
X-ray protection : the activation of the X-ray protec-tion is obtainedby application of a high level on theX-ray input (>1.6V). Consequences of X-ray pro-tection are :- Inhibition of H drive output.- Inhibition of SPMS output.- Activation of safety blanking output.
The reset of this protection is obtained by VCCswitch off.
S Correction. S Outputs
In the case where the ”S correction” of the horizon-tal scanning is performed using capacitors, it isnecessary to switch capacitors when the frequencychanges.
For this the outputsS1, 2, 3 and 4 (Pins 9, 8, 7 and16) give an indication about the horizontal frequencybymonitoring thecontrolvoltage of theVCO (Pin12).
The switching of the S outputs occurs for the fol-lowing value of the control voltage.
S 1 2V
S 2 2.4V
S 3 3V
S 4 3.7V
The use of comparators with hysteresis avoidserratic switching of the Sout outputs if the controlvoltage of the VCO remains very close to a switch-ing reference level.
SMPS
This unit generates the supply voltage for the hori-zontal scanning system. This supply voltage isapproximately proportional to the H frequency inorder to keep the scanning amplitude constantwhen the frequency changes. More precisely theamplitude regulation is obtained by detecting andregulating the ”flyback” amplitude or EHT value.
The power supply is a step-up converterand it usesthe ”current-mode” regulation principle.
The power supply works in synchronism with thehorizontal scanning. The switching power transis-tor (external to the TDA9103) is switched on at thebeginning of the positive slope of the horizontalsawtooth. It is switched off as required by theintegrated regulator. The current in the switchingpower transistor is monitored and limited, and theratio Ton/Ton+Toff of the power transistor is limitedto 75% typically providing a very good reliability tothe power supply.
TDA9103
15/27
VREF
H-amp Reg-in
Compensation
Clamp
ISENSE H-FREQ
Buffer SMPS OUT
+
-EA
RAP CYC-
+
S
R
Basc40
41
42
2239
9103
-18.
AI
Figure 18 : SMPS Block Diagram
H Osc Sawtooth
SMPS Drive
SMPS Current
1.6V
6.4V
0.75T 0.25T
Error Amplifier Output (1.2V Max)
9103
-19.
AI
Figure 19 : SMPS Timing Diagram
UsystU0
TDA9103
HampAdjust
VREF
4.8VSWITCHINGREGULATOR
Flyback PeakDetection and Regulation
H yoke
HDRIVEUsyst isapproximativelyproportionalto Hfreq
Step-up Converter H S canning P art
9103
-20.
EP
S
Figure 20 : H Scanning Amplitude Regulation Example
The following functions are implemented in theTDA9103 :- A DC controlled variable gain amplifier allowing a
variation of ±14% of the voltage reference.This is used to set the horizontal image ampli-tude.
- An erroramplifier, the non inverting input of whichis connected to the above mentioned adjustablevoltage reference.The inverting input and the output of the error
amplifier are externally accessible.- A comparator which determines the conduction
of the external transistor by comparing the outputvoltage of the error amplifier and the voltageapplied on Pin 42 (ISENSE), which is the image ofthe current in the power transistor (current modeprinciple).
- A flip-flop which memorizes the on or off state ofthe power transistor.
- An output buffer stage (open collector).
TDA9103
16/27
+Analog.
Multiplier
E/W-CENT E/W-AMP
Vertical Rampor
I
38 3736
9103
-14.
AI
Figure 21 : Parabola Generation Principle
PARABOLA GENERATION FOR EAST-WESTCORRECTION (see Figure 21)
Starting from the vertical ramp a parabola is gen-erated for E/W correction.The core of the parabola generator is an analogmultiplier which generates a current in the form :
I = k (VRAMP - VMID)2
Where VRAMP is the vertical ramp, typically com-prised between 2 and 5V, VMID is a DC voltage witha nominal value of 3.5V, but adjustable in the range3.2V → 3.8V in order to generate a dissymmetricparabola if required (keystone adjustment).The current is converted into voltage through avariable gain transresistance amplifier. The gain,controlled by the voltage on Pin 37 (E/W-AMP) canbe adjusted in the ratio 3/1.The parabola is available on Pin 36 by the way ofan emitter follower which has to be biased by anexternal resistor (10kΩ). It must beAC coupled withexternal circuitry.The typical parabola amplitude (AC), with the DC
control voltages V37 and V38 set to 4V, is 2V.It is important to note that the parasitic paraboladuring the discharge of the vertical oscillator ca-pacitor is suppressed.
VERTICAL PART (see Figure 22)
The vertical part generates a fixed amplitude rampwhich can be affected by a S correction shape.Then, the amplitude of this ramp is adjustedto drivean external power stage.
The internal reference voltage used for the verticalpart is available between Pin 26 and Pin 24. It canbe usedas voltage referencefor anyDC adjusmentto keep a high accuracy to each adjustment. Itstypical value is :
V26 = VREF = 8V.
The charge of the external capacitor on Pin 27(VCAP) generates a fixed amplitude ramp betweenthe internal voltages, VL (VL = VREF/4) and VH(VH = 5/8 ⋅ VREF).
VREF
Osc Cap
R 19R
Sampling Cap
VREF
S Correction
VERT-OUT
VERT-AMPParabola Generator
EW-AMPKEYST
EW-OUT
OSCILSYNCHROV-SYNC
Disch.
Charge Current
Transconductance Amplifier
27
2534
38 37
3631
30
28
29 S-CENTERS-AMP
9103
-17.
AI
Figure 22 : Vertical Part Block Diagram
TDA9103
17/27
Function
When the synchronisation pulse is not present, aninternal current source sets the free running fre-quency. For an external capacitor, COSC = 180nF,the typical free running frequency is 84Hz.
Typical free running frequency can be calculatedby :
f0 (Hz) = 1.5 ⋅ 10−5 ⋅ 1COSC (nF)
A negative or positive TTL level pulse applied onPin 34 (VSYNC) can synchronise the ramp in thefrequencyrange [fmin, fmax]. This frequency rangedependson theexternal capacitorconnectedonPin27. A capacitor in the range [150nF, 220nF] is re-commanded for applicat ion in the followingrange : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25°Cand without any correction (S correction or C cor-rection), can be calculated by :fmax = 2.5 ⋅ f0fmin = 0.33 ⋅ f0
If S or C corrections are applied, these values areslighty affected.If an external synchronisation pulse is applied, theinternal oscillator is automaticaly caught but theamplitude is no more constant. An internal correc-tion is activated to adjust it in less than half asecond: the highest voltage of the ramp on Pin 27is sampledon the sampling capacitorconnectedonPin 25 (VAGCCAP) at each clock pulse and atransconductance amplifier generates the chargecurrent of the capacitor. The ramp amplitude be-comes again constant.It is recommanded to usea AGC capacitor with lowleakage current. A value lower than 100nA is man-datory.
DC Control Adjustments
Then, a S correction shape can be added to thisramp. This frequency independent S correction isgenerated internally; its amplitude is DC adjustableon Pin 28 (VSAMP) and it can be centered to gener-ate C correction, according to the voltage appliedon Pin 29 (VSCENT).It is non effective for VSAMP lower than VREF/4 andmaximum for VSAMP = 3/4 ⋅ VREF.
Endly, the amplitude of this S corrected ramp canbe adjusted by the voltage applied on Pin 31(VAMP). The adjusted ramp is available on Pin 30(VOUT) to drive an external power stage. The gainof thisstage is typically±30% when voltage appliedon Pin 31 is in the range VREF/4 to 3/4 ⋅ VREF. TheDC value of this ramp is kept constant in thefrequency range , for any correction applied on it.Its typical value is :
VDCOUT = VMID = 7/16 ⋅ VREF.A DC voltage is available on Pin 32 (VDCOUT). It isdriven by the voltage applied on Pin 33 (VPOS). Fora voltage control range between VREF/4 and 3/4 ⋅VREF, the voltage available on Pin 32 is :
VDCOUT = 7/16 ⋅ VREF ± 300mV.So, the VDCOUT voltage is correlated with DC valueof VOUT. It increases the accuracy when tempera-ture varies.
Basic EquationsIn first approximation, the amplitude of the ramp onPin 30 (VOUT) is :
VOUT - VMID = (VCAP - VMID) [1 + 0.16 ⋅ (VAMP - VREF/2)]
with VMID = 7/16 ⋅ VREF ; typically 3.5VVMID is the middle value of the ramp on Pin 27VCAP = V27 , ramp with fixed amplitude.
On Pin 32 (VDCOUT), the voltage (in volts) is calcu-lated by :
VDCOUT =VMID + 0.16 ⋅ (VPOS - VREF/2).VPOS is the voltage applied on Pin 33.The center of the S correction can be approxima-tively calculated according to the voltage appliedon Pin 29 (VSCENT) :
VCENTER = VMID + 0.25 ⋅ (VSCENT - VREF/2)This is an internal voltage used to adjust the Ccorrection. The S correction can be adjusted alongthe ramp according to this parameter. It is ineffec-tive when VSAMP is lower than VREF/4.The current available on Pin 27(when VSAMP = VREF/4) is :IOSC = 3/8 ⋅ VREF ⋅ COSC ⋅ fCOSC : capacitor connected on Pin 27f synchronisation frequencyThe recommanded capacitor value on Pin 25(VAGC) is 470nF. Its assumes a good stability of theinternal closed loop.
TDA9103
18/27
INTERNAL SCHEMATICS
Q5
Q6Q6
Q1
VREF
VCC
D23
Q4 D22
PLL2C1
9103
-22.
AI
Figure 23
Q9
VCC
D25 Q8
M7
D24
HDUTY 2
9103
-23.
AI
Figure 24
Q13
VCC
D26
D27
HFLY 3
9103
-24.
AI
Figure 25
Q16
D29
Q15
VCC
VCC
D28
HREF5
9103
-25.
AI
Figure 26
VCC
D31
M20
D30
S4/S3/S2/S1Pins 6-7-8-9
9103
-26.
AI
Figure 27
VCC
D34
Q32
Q33
D35
C010
9103
-27.
AI
Figure 28
TDA9103
19/27
INTERNAL SCHEMATICS (continued)
Q69R0 11
Q46
9103
-28.
AI
Figure 29
VCC
D10
M5
Q7
Q8
M4 M6
D9
PLL1F 12
9103
-29.
AI
Figure 30
VCC
D14M11
D13
HLOCK-CAP13
9103
-30.
AI
Figure 31
VCC
D20
Q17
Q15
D19
FH-MIN14
9103
-31.
AI
Figure 32
VCC
D24
D25
Q23
Q22
Q21
H-POS15
9103
-32.
AI
Figure 33
VCC
D27
Q26
D28
XRAY-IN16
9103
-33.
AI
Figure 34
VCC
D2
D0
Q1 HSYNC17
9103
-34.
AI
Figure 35
Q4
VCC
D7
D6
Q3
VCC
D8
D9
H-OUTCOLL21
H-OUTEM20
9103
-35.
AI
Figure 36
TDA9103
20/27
INTERNAL SCHEMATICS (continued)
VCC
PMOS
PMOS
NMOS
NMOS
VAGCCAP 25
9103
-36.
AI
Figure 37
VCC
NPN
NPN
NPN
VREF26
9103
-37.
AI
Figure 38
VCC
PNP
PNP
NPN NPN
VREF
VS-AMP 28
9103
-39.
AI
Figure 40
VCC
VREF
PNP
PNP
NPN NPN
NPN
VS-CENT 29
9103
-40.
AI
Figure 41
VCC 12V
PNP
PNP PNP
NPN
VREF
NPN
NPN
VREF VCC
VCAP 27
NMOS
9103
-38.
AI
Figure 39
TDA9103
21/27
INTERNAL SCHEMATICS (continued)
PNP
NPN
VCC
VOUT30
9103
-41.
AI
Figure 42
NPN
NPN
VREF VCC
V-AMP31
9103
-42.
AI
Figure 43
PNP
VCC
NPN
NPN
PNP VDCOUT32
9103
-43.
AI
Figure 44
VCC
NPN
PNP
PNP
NPN
VREF
V-POS 33
9103
-44.
AI
Figure 45
VCC
PNP
PNP
VREF
VSYNC 34
9103
-45.
AI
Figure 46
VCC
NPN
NPN
NPN
VREF
E/WOUT36
9103
-46.
AI
Figure 47
TDA9103
22/27
INTERNAL SCHEMATICS (continued)
VCC
NPN
NPN
PNP
PNP
VREF
E/W-AMP 37
9103
-47.
AI
Figure 48
VCC
NPN
PNP
PNP
NPN
VREF
KEYST 38
9103
-48.
AI
Figure 49
VCCD28
Q26Q24
Q23
D27
B+-ADJ39
9103
-49.
AI
Figure 50
VCCD21
D22
Q20 Q19REGIN 40
9103
-50.
AI
Figure 51
VCC
D18Q16
Q15
Q14D17
COMP41
9103
-51.
AI
Figure 52
VCCD13
Q10
D12
ISENSE 42
9103
-52.
AI
Figure 53
TDA9103
23/27
+
PIN
CS
HV
SH
IFT
SC
OR
VS
IZE
KE
YS
TC
CO
RH
SIZ
E
J3b
HR
EF
VR
EF
HD
FH
SH
IFT
BP
LUS
FH
MIN
J2b
IC1
+
+
+ + +
+
+
VR
EF
+12
V
TP
8
TP
9of
fon
S1
++
HR
EF
+
J18
+
HF
LYJ1b
HF
LY
+12
V
+
1H
FLY
J17
CS
SW
ITC
H TP
2X
RA
YIN
J2
HS
YN
CT
P3
J5V
SY
NC
TP
7
TP
6B
LK
J19
1
TP
5T
P4
J3 1
+12
V
+
0/5V
to2/
6VIN
TE
RF
AC
E
HD
RIV
E
J22
T1
G55
76-0
1
+
VP
R44
10Ω
+12
V
HO
RIZ
ON
TA
LD
RIV
ER
ST
AG
E
1J23
CO
N2
VY
OK
E
1-1
2VJ2
1
R36
12kΩ
R70
12k Ω
-12V
+
R36
5.6k
Ω
+12
V
TP
11
+
17
26
3 54
VE
RT
ICA
LD
EF
LEC
TIO
NS
TA
GE
J24
E/W
VP
+12
V
+
R75
E/W
PO
WE
RS
TA
GE
1J25VP
1J11
EH
TF
EE
DB
AC
K
+B
+
D3
BY
T13
-800
++
12V
+
VM
T2
G54
46-0
01J2
0
1J12
R72
1kΩ
B+
CO
NV
ER
TE
R
+
1 2 3 4 5 6 7 8 9 10 16 17 18 19 20
26272829303637383940
11 12 13 14 15 2122232425313233343542 41
T D A 9 1 0 32 3 1 2 31 2 3
12
34
12
34
12
34
56
7
C24
220p
F40
0V
C25
22µF
250V
C33
100p
F
C46
C47
10nF
10nF
Q5
BC
557
Q7
BC
547
Q8
BC
547
Q3
Q4
BC
547
BC
547
Q9
TIP
122
C10
100n
F
C11
470p
F
C14
470 µ
FC
1147
0pF
C15
220n
F
C32
100n
F
C12
100µ
F35
VC13
470 µ
F
Q10
BC
547
Q1
BC
557
Q2
ST
D5N
20
C20
100 µ
F
C19
1nF
R35
1kΩ
R45
22k Ω
R46
560Ω
R47
a47
Ω3W
R47
b33
Ω3W
R37
5.6k
Ω
D1
1N40
04
R41
1.5Ω
R39
220
Ω1/
2W
R40
1Ω 1/2W
R49
1.5k
Ω
3.3k
Ω
R76
R52
10k Ω
10k Ω
R48
R77
R50
10k Ω
1kΩ
1kΩ
R51
10k Ω
R54
470 Ω
C21
10µF
C44
220p
F
R57
12k Ω
R58
47kΩ
1/2W
R59
2.2
Ω1W
R53
1kΩ
R55
10k
Ω
R56 2.7k
Ω
Q6
IR43
0F
R63
1kΩ
R62
1kΩ
C22
100µ
F
C23
220µ
F63
V
R64
3.3k
Ω
R66
1.5k
Ω
R65
33k Ω
R79
75k Ω
R61
33Ω
1W
R60
1kΩ
R78
22kΩ
C9
100n
FC
810
0µF
R33
10k Ω
C28
47µF
R69
3.9k
Ω
TP
1 C5
150n
F
470n
F
C48 1nF
R802.7kΩ
D4
1N41
48
C42
1 µF
C43
1µF
C27
100n
F
C4
C40
1 µF
C41
1 µF
C37
1µF
C38
1µF
R67
22kΩ
R68
1MΩ
C29
470p
F
C6
220n
F
C7
4.7
µFR
311.
8kΩ
R32
7.5k
Ω
680p
F5%
C2
C3
10nF
C45
220p
FC1
22nF
C39
1µF
C35
1µF
C34
1µF
C36
1 µF
C30
C29
100n
F47
µF
R71
10k Ω
1 2 3 4
R7410kΩ
R7310kΩ
R2120kΩ
R5120kΩ
R8120kΩ
R310kΩ
R610kΩ
R910kΩ
R1210kΩ
R1510kΩ
R1810kΩ
R2110kΩ
R2410kΩ
R2710kΩ
R3010kΩ
R11120kΩ
R14120kΩ
R17120kΩ
R20120kΩ
R23120kΩ
R26120kΩ
R29120kΩ
R223.9kΩ
R193.9kΩ
R253.9kΩ
R283.9kΩ
R163.9kΩ
R133.9kΩ
R103.9kΩ
R73.9kΩ
R43.9kΩ
R13.9kΩ
9103
-53.
EP
S
APPLICATION DIAGRAM
TDA9103
24/27
A demonstration board has been developped bySGS-THOMSON and is available through yourusual SGS-THOMSON office.This board has been designed in order to give firstthe possibility to evaluate the TDA9103 in STANDALONE, and then to be easily connected to anexisting monitor.In stand alone evaluation, for exemple, flybacksimulator is implemented in order to be able to
close the 2nd PLL loop, potentiometers are alsopresent to easily adjust all functions.Then for testing in a real application, the upper partof the board can be detached and the remainingpart can be connected to real application.In addition to this, the application board has beenvolontary designed separating clearly all theblocks. This led to quite large PCB but give muchmore space for measuring anything on the board.
9103
-60.
TIF
Figure 54
TDA9103
25/27
TD
A91
03
9103
-61.
EP
S
Figure 55
TDA9103
26/27
DimensionsMillimeters Inches
Min. Typ. Max. Min. Typ. Max.A 5.08 0.200
A1 0.51 0.020A2 3.05 3.81 4.57 0.120 0.150 0.180B 0.36 0.46 0.56 0.0142 0.0181 0.0220
B1 0.76 1.02 1.14 0.030 0.040 0.045c 0.23 0.25 0.38 0.0090 0.0098 0.0150
D 37.85 38.10 38.35 1.490 1.5 1.510E 15.24 16.00 0.60 0.629E1 12.70 13.72 14.48 0.50 0.540 0.570
e 1.778 0.070e1 15.24 0.60
e2 18.54 0.730e3 1.52 0.060L 2.54 3.30 3.56 0.10 0.130 0.140
SD
IP42
.TB
L
A1
B eB1
D
22
21
42
1
LA
e1
A2
c
E1
E
e2
Gage Plane
.015
0,38
e2
e3
E
SDIP42
PM
SD
IP42
.EP
S
PACKAGE MECHANICAL DATA42 PINS - PLASTIC PACKAGE
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibilityfor the consequences of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces allinformation previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lifesupport devices or systems without express written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the PhilipsI2C Patent. Rights to use these components in a I 2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco
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TDA9103
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