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The Control UnitLectures 31
Section 4.3, Appendix D
Robb T. Koether
Hampden-Sydney College
Mon, Nov 11, 2019
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 1 / 27
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 2 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 3 / 27
The Five Stages of the Data Path
The five stages.Instruction fetch (IF).Instruction decode (ID).Execution (EXE).Memory access (MEM).Write back (WB).
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 4 / 27
The Data Path
The Data Path
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
0
1
MUX
0
1
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
ALUSrc
ALUop MemWrite
MemtoReg
MemRead
RegWrite
PCSrc
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 5 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 6 / 27
Instruction Formats
MIPS uses three different formats for its instructions.R-format: 2 source registers, 1 destination registerI-format: 1 source register, 1 destination register, 1 immediate valueJ-format: 1 immediate value
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 7 / 27
Instruction Formats
Instruction Formatsle
31 2526 1621 11 5101520 06
Op code Src Reg 2Src Reg 1 Dst Reg Const Funct
R-format
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 8 / 27
Instruction Formats
Instruction Formatsle
31 2526 1621 1520
Op code Dst RegSrc Reg Const
0
I-format
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 8 / 27
Instruction Formats
Instruction Formatsle
31 2526 0
Op code Const
J-format
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 8 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 9 / 27
The Control Unit
Given the instruction, the control unit generates the control signalsneeded for the proper execution of the instruction.We will design a control unit for our sample instruction set.
lwswbeqaddiandornoraddsubslt
Our control unit will also produce the ALU control input for eachinstruction.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 10 / 27
The Control Unit
The control unit sends out the ALU operation and seven controlsignals.
RegDst - Whether rd is the destination register.Branch - Whether the operation is a branch.MemRead - Whether to read from memory.MemtoReg - Whether the result is from the ALU or from memory.MemWrite - Whether to write to memory.ALUSrc - Whether to use an immediate value.RegWrite - Whether to write to a register.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 11 / 27
The Control Unit
SignalName Effect When Asserted (1) Effect When Disasserted (0)RegDst The register destination The register destination
comes from the rd field comes from the rt fieldBranch PC is computed from PC← PC + 4
branch targetMemRead Put memory data in read Nothing
data outputMemtoReg The register write data The register write data
input comes from memory input comes from the ALUMemWrite Data memory replaced by Nothing
value from registerALUSrc Second operand comes from Second operand comes from
the immediate field the rt fieldRegWrite The write register is Nothing
is written with write data
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 12 / 27
The Control Unit
The Control Unit
RegWriteRegDest MemToReg MemRead MemWriteALUSrc Branch
Control Unit ALUOp ALUOp
Operation
RegWriteRegDest MemToReg MemRead MemWriteALUSrc Branch
Data Path
ALU
Instruction
32 6 6[31:26] [5:0]
2
4
The control unit sends outputs signals that control the data path.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 13 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 14 / 27
R-Type Instructions
Consider the R-type instructionadd rd, rs, rt
Reads the values from the registers rs and rt.Adds them together.Writes the result to the register rd.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 15 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
0
add rd, rs, rt
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Fetch
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Decode
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Execution
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Memory Access
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
R-Type Instructions
R-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Write Back
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 16 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 17 / 27
I-Type Instructions
Consider the I-type instructionaddi rt, rs, imm
Reads the value from the register rs.Adds imm to that value.Writes the result to the register rt.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 18 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
0
addi rt, rs, imm
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Fetch
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Decode
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Execution
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Memory Access
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Write Back
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 19 / 27
I-Type Instructions
Consider the I-type instructionlw rt, offset(rs)
Reads the value from the register rs.Sign-extends the offset.Adds the offset to the value from rs.Reads from that address of memory.Writes the result to the register rt.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 20 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
0
lw rt, offset(rs)
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Fetch
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Decode
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Execution
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Memory Access
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Write Back
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 21 / 27
I-Type Instructions
Consider the I-type instructionsw rt, offset(rs)
Reads the value from the register rs.Sign-extends the offset.Adds the offset to the value from rs.Reads from that address of memory.Writes the result to the register rt.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 22 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
0
sw rt, offset(rs)
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Fetch
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Decode
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Execution
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Memory Access
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Write Back
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 23 / 27
I-Type Instructions
Consider the I-type instructionbeq rs, rt, offset
Reads the values from the registers rs and rt.Subtracts one from the other.Produces 0 if they are equal.Shifts the offset by 2 positions.Adds the shifted offset to the PC register.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 24 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
0
beq rs, rt, offset
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Fetch
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Instruction Decode
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Execution
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Memory Access
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
I-Type Instructions
I-Type Instruction
16
ALUzero
ALUresult Address
Writedata
Datamemory
Readdata
MUX
1
0
MUX
0
1
ALUcontrol
Readdata 1
Readdata 2
Registers
Readregister 1
Readregister 2
Writeregister
Writedata
Sign-extend
32
Instruction [5-0]
Instruction [15-0]
MUX
0
1Instruction [15-11]
Instruction [20-16]
Instruction [25-21]
Instruction [31-26]
RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWrite
Control
ADDERADDER
Readaddress
Instruction [31-0]
Instructionmemory
PC
4
MUX
0
1
Shiftleft 2
Write Back
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 25 / 27
Outline
1 The Data Path
2 Instruction Formats
3 The Control Unit
4 R-Type Instructions
5 I-Type Instructions
6 Assignment
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 26 / 27
Assignment
AssignmentRead Section 4.3, Appendix D.
Robb T. Koether (Hampden-Sydney College) The Control Unit Mon, Nov 11, 2019 27 / 27