The Coming Silicon Convergence - SiliconAid Solutions SWDFT 0503… · © 2012 Altera Corporation—Public The Coming Silicon Convergence: Programmability is the Answer Ty Garibay

© 2012 Altera Corporation—Public

The Coming Silicon Convergence:Programmability is the Answer

Ty GaribayVP, Embedded Processing


Altera at a Glance

2

Founded in Silicon Valley, California in 1983

Industry’s first reprogrammable logic semiconductors

$2.06 billion in 2011 sales

Over 2,900 employees

Leading supplier of FPGAs, ASICs, and CPLDs


Altera’s Embedded Processing COE

Altera launched the Austin Technology Center in Q2, 2011 Focused on building a strong team

to develop processor-based systems and software

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Altera finds its Austin homeCalif. chipmaker to employ hundredsPremium content from Austin Business Journal - by Cody Lyon , ABJ Staff Date: Friday, June 10, 2011, 5:00am CDT - Last Modified: Thursday, June 9, 2011, 2:55pm CDT

California chipmaker Altera Corp. signed a major lease in Southwest Austin so it can establish a research and development center that will employ hundreds,

according to Transwestern.


The Dilemma: Flexibility vs. Efficiency

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Source: “High-performance Energy-Efficient Reconfigurable Accelerator Circuits for the Sub-45nm Era” July 2011by Ram K. Krishnamurthy, Circuits Research Labs, Intel Corp.

MO

PS/m

W

Programmable Processing


The Range of IC Options Today

5

Std-cell/Custom Multiple customers Buy & program SW

µP DSP

Std-cell/Custom Multiple customers Buy & program SW Optimized for DSP

C

Software ProgrammabilityµP: C-code DSP: C-code or Models

W W

µPC

DSP FPGA

Programmable Fabric Multiple customers Buy & program HW

Hardware ProgrammabilityRTL code (VHDL, Verilog)

FPGA

W

N

W Supports wide range of applications and unit volumes

Only for narrow /single applicationswith high unit volumes

SoftwareInstruction-based C-code programmingor behavioral modelingHigher abstraction, less silicon efficiency

RTL-based detailed design“Wired speed” efficiency

IP

ASIC

Std-cell One customer Provide design,

buy devices

ASSP

Std-Cell Multiple customers Buy complete

product

Limited or No Software ProgrammabilityEmbedded µP, Embedded DSP: C-code or Models

N N

DSP

May containMay containembeddedembedded

µµP,DSPP,DSPµP

IPIPIPIP

DSP µP

Hardware


Optimization Drives “Best Chip For The Job”

6

FPGA?DSP?ASSP?ASIC?

DSP?ASSP?

FPGA?µP?ASSP?

Intel®Atom™ processorE600C series

Intel®ATOMTM

E600 Processor

Series

AlteraFPGA

Internet Protocol Surveillance Camera

ImageSensor Image

Processing

IP Block 1 Analytics

VideoEncoding

IP Block 3

FPGA

DDR-SDRAM

EthernetPHY

IP Block 2

DDR-SDRAM

The UMTS Infrastructure

Chipset


Silicon Convergence

7


µP DSP


C


W W

µPC

DSP FPGA

Programmable Fabric Multiple customers Buy & program HW

Hardware ProgrammabilityRTL code (VHDL, Verilog)

FPGA

W

N

W Supports wide range of applications and unit volumes

Only for narrow /single applicationswith high unit volumes

SoftwareInstruction-based C-code programmingor behavioral modelingHigher abstraction, less silicon efficiency

RTL-based detailed design“Wired speed” efficiency

IP

ASIC


buy devices

ASSP


product


N N

DSP


µµP,DSPP,DSPµP

IPIPIPIP

DSP µPNeed for IP Speed& Efficiency

Need for Greater ROI

Hardware


ASIC


buy devices

ASSP


product


N N

DSP


µµP,DSPP,DSPµP

IPIPIPIP

DSP µP

Silicon Convergence

8


µP DSP


C


W W

µPC

DSP FPGA

µP, DSP, application-specific IP & programmable fabric Multiple customers Buy & program HW

and SW

Software & Hardware Programmability

C-code, Models, RTL code

W

Need for IP Speed& Efficiency

Need for Greater ROI

IP

µP DSP

“Mixed System Fabric”

µP + DSP + application-specific IP + programmable fabric

IP

FPGA


Augmenting Fine-Grained Fabric with Coarse-Grained Programmable Functions in FPGAs

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

IPI/ORAMLOGIC


Growth of Processors in FPGAs

10

0

20,000

40,000

60,000

80,000

100,000

120,000

Without CPU With CPU

Source: Gartner September 2010

50%Des

ign

Star

ts

© 2012 Altera Corporation—Public11

SoC FPGA

Glue Logic HeterogeneousCapabilities

Stratix I130nm process

High Integration/ Bandwidth

Stratix IV40nm process

Hardened Subsystems

Stratix V28nm process

Cortex-A9 MPCore

SoC FPGA28nm process

Flex 60003µ process

FPGA Architectural Progression

1990’s >50K LEs

Logic

2010 & beyond >1M LEs

RAM

2000’s >500K LEs

Logic RAM

LogicXCVR

DSP

PLL

ALM

RAMPPT

PLLExt Mem Int

FPGAs have evolved well beyond logic fabric!

XCVR

DSP

PLL PLLExt Mem Int

FPDSP

2 X8 CG V

R

HardµPMem Cntl

ALM

PPT

EHB

PCS


“More Moore” Projections

Sources: ITRS 2010, ITRS 2011, Altera projections beyond 2026

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Year 2012 2014 2017 2020 2023 2026 2029 2032

Node 20nm 14nm 10nm 7nm 5nm 3.5nm 2.5nm 1.8nm

# FETs per die (B) 8 14 28 56 113 222 453 887

M1 1/2 pitch (nm) 32 24 16.9 11.9 8.4 6 4.2 3

Lgate (nm) 22 18 14 10.6 8.1 5.9 4.2 3

* Normalized to 20nm


ADC / DAC

Optical

ASSP

3D Integration Technology Opportunities

13

Memory

ASIC

M-core CPU

XCVR + FPGA

3D In

tegr

atio

n Po

ssib

ilitie

s

XCVR + FPGA

XCVR + FPGA


Programmable Platforms in 2012

Moore’s law has enabled a range of high density programmable platforms

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Fine‐GrainedMassivelyParallel HeterogeneousArrays

FPGAsDSPsCPUs

Single Cores Coarse‐GrainedMassivelyParallelProcessorArrays

Multi‐CoresCoarse‐GrainedCPUs and DSPs

Multi-Cores Many-Core Arrays

CONVERGENCE


Mixed System Fabric

The Best of All Worlds

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Wide ApplicationScope

Wired SpeedWired Efficiency

•Support for legacy code•Familiar C-code

methodology

•Support for high volume applications

• Application-specific IP

• Off-the-shelf availability• Support for changing

standards / reconfigurable systems

DSP•Optimized for DSP

operations

µP ASIC /ASSP

Domain of FPGA Suppliers

IPIP

FPGA


It’s More Than the Silicon

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Embedded Initiative Qsys System Integration Tool

Software Programming Support

Video andImage

ProcessingOTN Memory

ControllersFloating

PointOpen standard for

cross-platform design (µP, DSP, GPU)

DSPdesign

Cortex-M1MP32 ColdFire V1

Atom E6XXC

Cortex A9


Providing the Best of Two Worlds

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SoC FPGA

Dual Core ARM Cortex-A9 MPCore Processor

Hard Memory

ControllerPeripherals

ARM Processor System28-nm FPGA

ARM + Altera = SoC FPGAs


SoC FPGA

Processor Dual ARM Cortex-A9

SDRAM Controller, Peripherals Other Hard IP

Serial protocols, memory interfaces

FPGA programmable fabric Multiple density options

Programming model: C/C++ for ARM Common operating systems APIs for hardware accelerators

developed in HDL (Verilog, VHDL, System Verilog), or C/C++ by using high-level-synthesis

OpenCL

* Integrated DMA logic

ARM Cortex-A9NEON / FPU

L1 Cache


L1 Cache

L2 CacheL2 Cache

USBOTG *USB

OTG *

WD(x2)WD(x2)

DMADMA

FPGAFPGA

Multiport DDR SDRAM Controller

Multiport DDR SDRAM Controller

Ethernet

(x2) *

Ethernet

(x2) *

JTAG Debug / Trace

JTAG Debug / Trace

QSPI & NANDFlash Controller *

QSPI & NANDFlash Controller *


L1 Cache


L1 Cache

SD / MMCSD / MMC

I2C(x2)I2C(x2)

CAN(x2)CAN(x2)

GPIOGPIO

UART(x2)

UART(x2)

SPISPI

PCIeHIP

PCIeHIP

Multi-port DDR SDRAM Controller (optional)

Multi-port DDR SDRAM Controller (optional)

Timer(x4)

Timer(x4)

SOC 2FPGASOC 2FPGA

FPGA2 SOCFPGA2 SOC

FPGAConfigFPGAConfig


System-Level Benefits of SoC FPGA

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Before

FPGAFPGA

Dev

ices

Dev

ices Memor

yMemor

y

CPUCPU

Dev

ices

Dev

ices Memor

yMemor

y

After

FPGA+ CPUFPGA+ CPUD

evic

esD

evic

es Memory

Memory

Increased system performance 4,000 DMIPS for under 1.8W Up to 1,600 GMACS, 300 GFLOPS DSP >125 Gbps processor to FPGA interconnect Cache coherent hardware accelerators

Reduced power consumption Up to 30% power savings vs. 2-chip solution

Reduced board size Up to 55% form factor reduction As few as two power rails

Reduced system costs Lower component cost Reduction in PCB complexity and cost

Less routing with fewer layers

HighLow


Summary: Enabling Convergence

Effective integration FPGA programmable fabric, standard cell ASIC /

ASSP, HardCopy ASIC, application-specific IP, DSP, µP cores, analog transceivers, memory

Flexibility Hardware and software programmability Supports wide range of applications

Mass innovation for developers Quartus II, Qsys – enable hardware engineering

productivity OpenCL , Advanced DSP Builder – enable

software engineering productivity

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Mixed System Fabric


What Does This All Mean for DFT?

More of the same, of course: Bigger chips More devices Same amount of test time (or less) Same number of pins (or less)

New challenges: 3D IC testing?

Who owns what, when? Higher level redundancy

FPGA Tiles Processing units

What is the boundary between DFT and DV for highly programmable products?

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© 2012 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the United States and are trademarks or registered trademarks in other countries.

Thank You

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Documents

The Coming Silicon Convergence - SiliconAid Solutions SWDFT 0503… · © 2012 Altera Corporation—Public The Coming Silicon Convergence: Programmability is the Answer Ty Garibay