The challenges of configurable hybrid Memristor-CMOS ... · 2010 Storage Developer Conference. Insert Your © Company Name. All Rights Reserved The challenges of configurable hybrid

2010 Storage Developer Conference. Insert Your © Company Name. All Rights Reserved

The challenges of configurable hybrid Memristor-CMOS Integrated circuits

fabrication: Physics and Materials Science

Gilberto Medeiros-RibeiroHP Labs


Outline

Context Memristor basics Memristor fabrication and incorporation in

reconfigurable logic CMOS Final thoughts

2


Data Storage

170%/year Compound Growth rate (2002-2009):16x Moore’s law density increase;56x increase in storage 5-280 exabytes of online

data1

Hard disks are cheap, but latency is the bottleneck Flash as a hard disk replacement is on course DRAM roadmap ends in 2015

3

Need for universal memory!Preferable Non-volatile

1 “Physics of data”, Marissa Myers, Google


Why DRAM and Flash are approaching scaling limits?

4

DRAMCapacitors can’t get smallTransistors leak through the gateShort channel effects – S-D leakage

FLASHTunnel oxide

can’t get thinnerFaster

degradation


Non-volatile storage options

5

MemoryElement Cell size CMOS

IntegrationSwitch

MechanismBipolar

/Unipolar Power ScalingUltimate Scaling

Limit

Set-reset Times

Maturity

Metal Oxide *≤0.5F2 Excellent E-field Bipolar Good GoodConducting

channel size (5nm)

Good Lab-to-fab

PCM *4F2 Demonstrated Temperature Unipolar Poor Fair

Stable nanocrystal

size (~10nm)

Good Prototype

Flash *4F2 Excellent E-field N/A Good Fair Capacitor size Fair Product

FeRAM *4F2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product

MRAM *4F2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty

product

F=technology node


Non-volatile storage options

6

MemoryElement Cell size CMOS

IntegrationSwitch

MechanismBipolar

/Unipolar Power ScalingUltimate Scaling

Limit

Set-reset Times

Maturity

Metal Oxide *≤0.5F2 Excellent E-field Bipolar Good GoodConducting

channel size (5nm)

Good Lab-to-fab

PCM *4F2 Demonstrated Temperature Unipolar Poor Fair

Stable nanocrystal

size (~10nm)

Good Prototype

Flash *4F2 Excellent E-field N/A Good Fair Capacitor size Fair Product

FeRAM *4F2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product

MRAM *4F2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty

product

F=technology node

2010 Storage Developer Conference. Insert Your © Company Name. All Rights Reserved© Copyright 2010 Hewlett-Packard Development Company, L.P.7

Memristor x PCRAM:pro’s and con’s

Parameter Memristor PCRAM

Operation Bipolar Unipolar

1T/1R Yes Yes

X-bar Yes Yes, if incorporates series diode

CMOS compatible Yes, for both FEOL and BEOL

Not FEOL compatible

Maturity Incipient Decades

bit size scalability Good (down to 5nm) Uncertain (ok down to 50nm)

Retention Good Worsens with decreasing size


The memristor as the fourth element

MEMRISTORdφ = M dq

CAPACITORdq = C dv

RESISTORv = R i

INDUCTORdφ = L di

L. O. Chua, IEEE Trans. Circuit Theory 18, 507 (1971)

)](,[)( tiwfdt

tdw=

)()](,[)( titiwRtv =

rigorousdefinition

Quasi-static conduction eq.-R depends on state variable w

Dynamical equation: Evolution of state in time


What makes the memristor ‘fundamental’?Current vs. Sinusoidal Voltage

Voltage Voltage

Resistor

Cur

rent

Capacitor

Inductor

Cur

rent

Memristor

dv = R di dq = C dv

dφ = L di dφ = M dq

Time

Volta

ge

Cur

rent


Simple Phenomenological Description

)()( tiD

Rdt

tdw ONVµ=

ROFF

RON

Undoped:

Doped:

RON w/D ROFF (1-w/D)

D

Undoped

w

Doped

A

V

)()(1)()( OFFON tiD

twRD

twRtv

−+=

−= )(1)( 2 tqR

DRqM ON

VOFF

µ

Ionic drift:

Electronic current:

Strukov, Stewart, Snider & Williams, Nature 453 80 (2008)

w1

w2

w3

w3>>w2>>w1

i = sin[wt]

v = M(q(t)) i(t)

0

t

i


4 properties of memristive systems in 3 sweeps:

a dynamical device

1

Memristive Properties• Continuous states• Zero-crossing• Frequency dependent• Bias dependent

34

2


How can one make such a device?

Different materials choices, like TiOx, NiOx, CuOx, etc.

Metal electrodes

12


TiOx: a switching material

3.0/3.2 eV semiconductor dielectric ε ~ 80, bi-

refringent pigment, photocatalyst,

O2 sensors TiO2 : 1x Ti4+ + 2x O2-

Relatively easy to reduce Vacancy diffusion ~1eV

13


MIM devicesMetal/oxide/metal junction

Pt bottom electrode

Pt top electrode

TiO2

SiOx

Si

TiO2-x

Ti adhesion layer

TEM cross-section

Metallic nanowire(top electrode)

Switching materials(e.g. TiO2)Metallic nanowire

(bottom electrode)

Typical device fabrication:• sputtered deposited films of oxides;• e-beam deposition of Pt

J. Yang et al., Adv. Mat, (2010)


How can one make a memory from this?

15


Cross bar concept

16


Cross bar concept

17

V

-+ 0 or 1threshold

Sense amps


Cross bar concept

18

V/2

-+ 0 or 1threshold

-V/2

Sense amps


Cross bar concept

19

V/2

-+ 0 or 1threshold

-V/2

Sense amps


Cross bar concept

20

V/2

-+ 0 or 1threshold

-V/2+=

Sense amps


A memristor X-bar implementation

Ability to scale to aggressive technology nodes

21

50 nm wire width


Nonlinear devices required!

Since the resistance of each device can be a very non linear function of the voltage, this non-linearity and asymmetry can be used in adjacent devices to isolate bits.

22

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Cu

rre

nt (A

)

43210-1-2-3Voltage (V)

#1-999 cycle# 1000 cycleON

OFF

10-11

10-9

10-7

Cu

rre

nt (A

)1-1

Voltage (V)


Putting devices onto a CMOS platform

Develop simple models for realistic circuit design Known and well tested CMOS circuitry Match very different technologies Flexible voltage adjustments

23


Simple Spice Model for Circuit Verification

2, 9.80739E-06

2, 1.38918E-06

-0.000015

-0.00001

-0.000005

0

0.000005

0.00001

0.000015

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

Cur

rent

(A)

Voltage (V)

Junction IV Characteristics

IonIoff

Bench Data provided by HPL

( )VkIk *sinh βα=State Alpha Beta Avg of RMS errorOFF 2.29E-08 2.4 1.8E-08ON 1.73E-08 3.5 5.3E-08

Simplified Model

State of the art model at time of design, a more detailed model exists now.

Actual device model used for CMOS verification

Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp 3640–3645


out

start

in

DQFF

half-adder

B

AS

C 00111 “7”

00001 “+1”

001000 “8”

in

out 00 0

0011 1

001

LSB MSBB

time

1

Time

1

Q

1

1

1

Hard Coded Die Configuration

In order to mitigate design risk, and speed up test development, CMOS pre-configured


SNIC Architecture


CMOS Integration Challenges

Challenges: Unstable process for nanowires Design needed to enable process development Driver circuitry for a dynamical load Different operating voltages

Implication: Design had to provide a flexible interface for fab and lab quality

imprint tooling Larger than necessary alignment tree

Risks Unknown Fab-Lab integration challenges

2010 Storage Developer Conference. Insert Your © Company Name. All Rights Reserved28

Quartz NIL Molds

Bottom Electrode Top Electrode “Holey” Pad Structure

Master mold patterned by EBL. Daughter molds duplicated on QZ using NIL. Nanowires:100 nm HP. Feature height: 60 nm. Pad size: 10 µm by 15 µm.


CMOS Substrate

3 metal layer CMOS circuits, [0, 3.3V] operation. Chip finished with TEOS and CMP. Fabricated with 0.5 µm technology at HP Corvallis fab in Oregon


Integrated Hybrid Circuits

100 nm100 nm(c)12 nm Pt36 nm TiO29 nm Pt2 nm Ti


Wiring of Logic Gates Using Memristors


OR gate

Logic Functions Successfully Implemented

NOT gate

AND gate

A C

C

A

B

1

A

B

1

C

Reading voltage: 1.7 V. CMOS: 3.3V


NAND gate

NOR gate

D Flip-flop

D

Clk Q

Q

C

A

B

1

C

A

B

1

Logic Functions Successfully Implemented


Reconfigurability Demonstrated

ON OFF

INPUT00001111

OUTPUT11110000

INPUT00001111

OUTPUT00000000Reading voltage: 0.5 V

Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp 3640–3645


Main points

Scalability: 4F2 feasible, stacking also feasible CMOS compatible process Low power (not discussed) Non-volatility Faster and more resilient than FLASH, with better

scaling perspectives

35


Acknowledgements: Julien Borghetti John Paul Strachan Dmitri Strukov Feng Miao Wei Yi Matthew Pickett Douglas Ohlberg Qiangfei Xia Hans Cho Xuema Li Tan Ha Cuong Le Fred Perner Tsung-Wen Lee Mike Cumbie Phil Kuekes Warren Robinett Alexandre Bratkovski Dick Carter Rick Amerson Pascal Vontobel Erik Ordentlich Gadiel Seroussi Wei Wu Max Zhang Hisham Abdahla Shakeel Quresh Greg Snider Janice Nickel Stan Williams

Information and quantum Systems Lab:Photonics, CeNSE & Nanoelectronics groupsLab Director: Stan Williams


The Questions People Ask

Switching voltages/currents (volts/nA-100µA) Write/Erase/Read speed and energy (<10ns, pJ) ON/OFF ratio (>1000:1) Retention time (years – even millennia) Scaling limits (5nm? - >4 terabits/sq cm) Endurance and failure mechanisms (heating) Nature of ON and OFF states (metal/insulator) Devices are evolving rapidly with understanding

Documents

The challenges of configurable hybrid Memristor-CMOS ... · 2010 Storage Developer Conference. Insert Your © Company Name. All Rights Reserved The challenges of configurable hybrid