The APV Emulator (APVE)

System Meeting: Greg Iles27 Feb 2002 1

The APV Emulator (APVE)The APV Emulator (APVE)

Task 1.Task 1.– The APV25 has a 10 event buffer in de-convolution mode.

– Readout of an event = 7us

– Triggers arrive in a Poisson distribution with mean period = 10us.

– Finite buffer + Random triggers => Possibility of buffer overflow

– OVERFLOW => DEAD TRACKER (APV reset required)

Task 2.Task 2.– FED detects a small portion of APVs within the Tracker losing sync

APVEAPVE protects against buffer overflowprotects against buffer overflow

APVEAPVE detects a detects a groupgroup of APVs losing sync of APVs losing sync

What does the APVE do & why ?What does the APVE do & why ?


Tracker

APV in

deconvolution

mode

What does APVE do & why ?What does APVE do & why ?

Primary task: Preventing buffer Primary task: Preventing buffer overflow in APVsoverflow in APVs

– Its takes too long to send a ‘buffers full’ signal from APVs in the tracker to Trigger Control System (TCS).

– Therefore require an APV close to the TCS.

Secondary task: Secondary task: Synchronisation checkSynchronisation check

– All APV data frames include the memory cell (pipeline) address used to store the L1A data in the APV.

– The pipeline address is sent to all FEDs to ensure that all APVs are in-sync.

APAPVEVE 1: Full

2: Full

3: Empty

10: Empty

Data frame

TCS: Inhibit L1A?

Reset and L1A

Busy

FED: Data OK?

Pipeline

address

(min period = 75ns)

(period = 7000ns)


How does APVE work ?How does APVE work ?

L1A ThrottleL1A Throttle– A counter keeps track of the number

of filled APV buffers.

• L1A => INCREMENTS counter.

• Output frame => DECREMENTS the counter.

• Reset => CLEARS the counter.

• APVE must receive the same L1As and Resets as APVs within the Tracker or System fails

– When the counter reaches preset values it asserts Warn followed by Busy.

Synchronisation checkSynchronisation check– Header on APV data frame provides

pipeline address

Real APV25

Buffer counter

L1A

APV data frame

Pipeline addressBusy

UP

DOWN

Reset

CLEAR

Frame output signal

Assert busy?

Header recognition

APVEAPVE


Task 1: L1A ThrottleTask 1: L1A ThrottleTiming criticalTiming critical

– Set by control loop from L1A inhibit gate within Global or Local TCS to APVE and back again.

– Ideally need to assert busy < 75ns) – Alternatively we lose an event buffer

location in the APV for every 75ns delay.

• Loss of buffers increases dead time.

• Require fast access to GTCS/LTCS to receive L1A/RESET and send Fast Control signals.

– TCS prefers a single set of Fast Control signals from the Tracker.

• Fast Merge Module (FMM) signals to go via APVE

L1A &

RESET

Inhibit gate

(inside TCS)

APVE

Buffers Full ?

L1A & RESET

BUSY


DeadtimeDeadtime

0.01

2

4

68

0.1

2

4

68

1

Dea

dtim

e (%

)

4003002001000Maximum control loop time (ns)

11 10 9 8 7 6 5Buffers filled when BUSY asserted

Nancy Marinelli and Bill Cameron Triggers rejected @ 100kHz

Simulation uses the internal APV pipeline logic.


Control structureControl structure

WARNING.................WARNING.................– Timing structure of L1As and

Resets received by the APVE and the APVs within the Tracker must be identical.

– How are resets issued by the TCS transformed into ‘101’ resets for the APV. Also relevant for ‘11’ calibrates.

– The APVE will NOT operate if the TTCvi is used as a source of Resets & L1As.

APVE TTCvi

Fast control

APV

GTCS LTCS

TTCex

TTCtx

FEC

CCU Ring

FED

FMM

Fast

Merge

Module

Pipeline address

Reset

& L1As

?

Applying timing constraints to control structureApplying timing constraints to control structure– At present envisage that APVE receives L1A and

Reset from both Global and Local TCS.


Current progressCurrent progress

Development system built and Development system built and tested.tested.

– Fast Control functions (i.e. busy, warn and out-of-sync).

– Programmable (i.e busy asserted when ‘X’ many APV buffers remain empty.

– History of signals recorded

• busy, warn, out-of-sync (i.e. when asserted, when negated) for ‘X’ many occasions.

• Total time asserted for busy, warn, and out-of-sync.

– Interfaces such VME, Wishbone and I2C interface

– TCS system implemented for testing.

APV

Trig & ResetClk

FPGA

ResetReset

Pre TCS, T1

Post TCS, T1

APV Output

Busy

Warn

Pre TCS, Reset

Pre TCS, Trigger

Time penalty incurred in the FPGA to distinguish triggers, '1' from resets, '101‘ and calibrates, '11‘, unless we receive trigger and reset signals separately.

1009590858075706560Clock

‘101’ reset ‘1’ trigger

inhibit blocks trigger

first tick after APV reset

busy asserted

warn asserted

End of reset periodEnd of reset period

Busy asserted after 8 triggers. Warn asserted after 5 triggers.

Pre TCS, T1

Post TCS, T1

APV Output

Busy

Warn

240235230225220215210205200Clock

Pre TCS, Reset

Pre TCS, Trigger

APV ready to receive trigger

‘1’ trigger

Buffer emptiesBuffer empties

Pre TCS, T1

Post TCS, T1

APV Output

Busy

Warn

Pre TCS, Reset

Pre TCS, Trigger

480475470465460455450445440Clock

Busy negated when an APV buffer empties, providing space for another event to be stored. It is asserted once more after a further trigger is sent to the APV.

‘1’ trigger

APV frame digital header


Future.... Simulate APV in real timeFuture.... Simulate APV in real time

VHDL code to simulate the APV in real time written and tested on ModelSim VHDL code to simulate the APV in real time written and tested on ModelSim (VHDL logic simulation package), but not downloaded into an FPGA.(VHDL logic simulation package), but not downloaded into an FPGA.

An FPGA is sufficiently fastAn FPGA is sufficiently fast

The APV pipeline logic , a possible obstacle to FPGA implementation, has been tested in a Xilinx Spartan-2.

....... and sufficiently large....... and sufficiently large

At a size of 200k gates the design is too big for our Spartan-2 (100k gates), but will fit in a Virtex-2.


Task 2: Sync (global)Task 2: Sync (global)

Task 2.Task 2.– FED detects individual APVs losing sync

– If more than 65 (?) APVs out of sync........

• FED can generate the wrong pipeline address

• Incorrect data to the DAQ.

– Should happen very rarely.......

• How important is getting pipeline address to the FED?

APVEAPVE detects a detects a groupgroup of APVs losing sync of APVs losing sync


Pipeline address via Pipeline address via networknetwork

At present........At present........– Check data after it has been sent to DAQ at a

frequency of every few seconds and in software.

Cons ...Cons ...– Requires lots of software and the pipeline

address travels a complex route to FED.

APVE Crate

CPU

APVE

APVE

APVE

APVE

FED Crate

CPU

FED

FED

FED

FED Crate

CPU

FED

FED

FED

x10 (ish)

x20x20


Pipeline address via Pipeline address via serial linkserial link

Possibly.....Possibly.....– Direct serial link (optical) to each FED crate. – Pipeline address distributed to FEDs via single

trace on VME back-plane.

Cons ...Cons ...– Additional hardware which needs to be

designed built and tested.– Reliability & maintenance for duration of LHC.

APVE Crate

APVE

APVE

APVE

APVE

FED Crate

APVP

FED

FED

FED Crate

CPU

FED

FED

FED

x10 (ish)

CPU

CPU

APVP


Outstanding issuesOutstanding issues

Where do we get L1A and Reset from, if not LTCS and GTCS ?Where do we get L1A and Reset from, if not LTCS and GTCS ?– If not LTCS & GTCS what is the time penalty of obtaining these signals further down

the command chain?

Where does merge of fast feedback signals take place, if at all ?Where does merge of fast feedback signals take place, if at all ?– APVE needs to be the last stage in this process, or very near it because timing critical.

– What is the time penalty imposed by going through FMM?

– At present APVE design assumes it is after FMM module and has 4 inputs (Ready/Error/Busy, Warn and Out-Of-Sync) that are OR’ed with APVE fast feedback signals.

How do we get pipeline address to the FEDs ?How do we get pipeline address to the FEDs ?– At present intend to check data after it has been sent to DAQ at a frequency of every

few seconds and in software.

– Serial link to each FED crate VME bus is possibly a simpler, more robust option, but more awkward to implement.


ConclusionsConclusions

Need to finalise location of APVE in command (RESET/L1A) and fast Need to finalise location of APVE in command (RESET/L1A) and fast feedback (BUSY/WARN etc.) control structure.feedback (BUSY/WARN etc.) control structure.

Many aspects, such as obtaining fast access to TCS already discussed Many aspects, such as obtaining fast access to TCS already discussed with those responsible. with those responsible.

When details finalised we will be able to finish board schematics, When details finalised we will be able to finish board schematics, manufacture and test APVE.manufacture and test APVE.

At the beginning we envisage 4 VME boards, one for each partition At the beginning we envisage 4 VME boards, one for each partition located in the Global Trigger rack.located in the Global Trigger rack.


APVE IOAPVE IO

FPGA

Global TCS, Reset/L1A

Global TCS Fast Control

FMM, Fast Control

Local TCS, Reset/L1A

Local TCS Fast Control

LHC Clock

VME, A24/D16

Perhaps also...... Perhaps also...... A fibre optic serial links to each FED crate to deliver the pipeline address (approx 10 per APVE)


Pipeline address

Alternative control structuresAlternative control structures

Fast control

Reset

& L1As

APVE

TTCvi

APV

GTCS

LTCS 0

FEC

FED

FMM

L1A/Fast Control Source Sel

LTCS 1

APVE

TTCvi

APV

GTCS

LTCS 0

FEC

FED

FMM

Key

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The APV Emulator (APVE)