Abstract– The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 half staves each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8,192 active cells, so that the total number of pixel cells in the SPD is ≈ 107. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget detector module dimensions are very demanding.

I. SPD LAYOUT

The ALICE silicon pixel detector (SPD) consists of two-barrel layers at radii of 3.9 cm and 7.6 cm, respectively. The basic detector module is the half-stave, in which the active elements are two sensor ladders glued to a flexible multi-layer aluminium/polyimide laminate carrying power and signal lines and one multi-chip read-out module. Each sensor ladder consists of 5 pixel chips bump bonded to one silicon pixel sensor. Each pixel chip contains a matrix of 8192 cells. The SPD contains 9.83 x 106 pixel cells in total.

The half-staves are mounted on 10 lightweight carbon

fiber sectors, each sector supporting 4 half-staves on the inner layer and 8 half-staves on the outer layer. Figure 1 shows a CAD drawing of the main functional elements of the SPD. Fig. 2 shows an image of one sector. The pseudorapidity coverage of the inner layer is |η| < 1.95.

II. SPD ELECTRONICS

A. Electronics system architecture Due to expected total ionizing dose in the inner layer

of 2.5 kGy (10 years), the neutron fluence (1 Mev equivalent) of 3 x 1012 cm-2 (10 years) and the limited geometrical space available, commercial electronics cannot be used on the detector. As a result radiation hard application specific integrated circuits (ASIC) were designed and were integrated to satisfy the requirements. To keep the design effort a minimum the electronics architecture [1] was designed in such a way that hardware intensive processing as data buffering and zero suppression are performed in the off-detector electronics. A custom

The ALICE Silicon Pixel Detector: Electronics System Integration

A. Kluge a, G. Anelli a, F. Antinori b, A. Badala c, A. Boccardi a, G. E. Bruno d, M. Burns a, I.A. Cali a,d, M. Campbell a,

M. Caselle d, S. Ceresa a, P. Chochula a,e, M. Cinausero f, J. Conrad a, R. Dima b, D. Elia d, D. Fabris b, R. A. Fini d, E. Fioretto f , F. Formenti a, S. Kapusta e, M. Krivda g, V. Lenti d, F. Librizzi c, M. Lunardon b,

V. Manzari d, M. Morel a, S. Moretto b, F. Osmic a, G.S. Pappalardo c, V. Paticchio d, A. Pepato b, G. Prete f, A. Pulvirenti c, P. Riedler a, F. Riggi c, L. Sandor g, R. Santoro d, F. Scarlassara b, G. Segato b, F. Soramel h,

G. Stefanini a, C. Torcato Matos a, R. Turrisi b, L. Vannucci f, G. Viesti b, T. Virgili i a CERN

b Dipartimento di Fisica dell’Universita’ and Sezione INFN di Padova, Italy c Dipartimento di Fisica dell’Universita’ and Sezione INFN di Catania, Italy

d Dipartimento di Fisica dell’Universita’ and Sezione INFN di Bari, Italy e Comenius University, Bratislava, Slovakia

f Laboratori Nazionali di Legnaro, Italy g Slovak Academy of Sciences, Kosice, Slovakia

h Dipartimento di Fisica dell’Universita’ and INFN Gruppo Collegato di Udine, Italy i Universita’ di Salerno and Sezione INFN, I-84081 Baronissi, Italy

Figure 2. Image of one SPD sector; power supply connections (extenders) on the left and right; the eight outer layer half-staves visible in the middle.

Figure 1. Artistic view of one half stave, of one sector and a CAD drawing of the SPD.

design radiation hard link has been developed to transfer the pixel raw data off the detector [2].

In each half-stave, a multi-chip module (MCM) initiates the read-out and performs the configuration process of the pixel chips [3]. The connection to the control room is established via three optical fibers. The MCM contains four ASICs and the custom developed 800 Mbit/s optical link for the data transfer between the detector and the control room. All on-detector ASICs have been implemented using a commercial 0.25 µm CMOS process; radiation hardness is obtained by appropriate gate design rules and by redundancy in the critical nodes. In the control room FPGA-based electronics performs zero suppression, data formatting and sends the data to the ALICE data acquisition system [1].

B. Half stave electronics integration The compactness of the design sets severe constraints

on the material budget and dimensions of the detector

elements and the interconnects. The very small clearance between the SPD inner layer

and the wall of the beam pipe requires that the overall radial thickness of the half-staves is less than 3 mm. The width of the half-staves is determined by the pixel chip dimensions; the clearance between the edges of adjacent half-staves is down to ≈ 0.2 mm and the width of the MCM substrate is limited to 11 mm in order to avoid interference with the other structural elements. In order to keep the material budget within 1% X0 (each layer), the read-out chip and the sensors are 200 µm thick and the pixel chips are thinned down to 150 µm.

Fig. 3 shows an exploded view of the half stave. Fig. 4 shows photographs of the actual components. A carbon fiber structure is the support for four half staves of the SPD inner layer and eight half staves of the SPD outer layer, see fig. 1 and 2. The half stave is attached to the the carbon fiber structure by drops of UV curable adhesive and mechanical clips (for reworkability) and electrically isolated from the carbon fiber structure via a polyimide foil. The sensor ladders are located closest to the carbon fiber support with the read-out chips facing the support. A read-out multi-chip-module (MCM) is mounted at the end of the carbon fiber structure. It is mechanically protected via a lid glued on top of the MCM. The interconnection between the pixel chips on the sensor ladder and the read-out MCM is established via a multi-layer flexible aluminium/polyimide laminate (pixel bus), in which aluminium layers are used as conductor to even further reduce the material budget. Copper/polyimide flexible laminates, are used to provide the pixel chips (bus extender) and the MCM (MCM extenders) with power. The half stave is less than 3 mm thick, 240 mm in long and 12 mm wide.

1) Grounding foil The polyimide grounding foil is 50 µm thick and coated

Figure 3. Exploded view of one half stave.

Figure 4. Exploded view of one half stave.

with a 10 µm thick aluminum layer, which is connected by wire bond to the ground of the read-out electronics in order to present an electromagnetic shield from the carbon fiber support.

2) Pixel read-out chip In the ALICE pixel read-out chip 8192 pixel cells are

arranged in a matrix of 256 rows times 32 columns. The pixel chips wafers are mechanically thinned to a thickness of 150 µm. Each pixel cell contains one amplifier-shaper, one discriminator, one delay line and 4 multi event buffers. The read-out of the chip is fully binary. The ALICE pixel read-out chip is designed in a 0.25 µm CMOS process. Due to the applied layout technique it is radiation hard, tested up to 20 Mrad. The chip has an active area of 12.8 mm x 13.6 mm. The delay lines allow to store each pixel hit for a duration of up to 51 µs at an operation frequency of 10 MHz before a trigger signal decides whether to store the hit in one of the four multi-event buffers or to discard it. In the multi-event buffer the hit data wait for the level 2 trigger signal, which decides to either dismiss the data, or to read-out the data via a 32 bit 10 MHz parallel bus [1].

3) Sensor The sensor is a matrix of 40,960 p-in-n diodes of

dimensions 50 µm x 425 µm on a tile of dimensions 13.92 mm x 72.72 mm and 200 µm thickness [4]. Each diode is connected to the read-out electronics via a 25 µm large Pb-Sn bump bond [4]. The sensor thickness is 200 µm.

4) Detector ladder and Sn-Pb Bump bonding A detector ladder is formed by five read-out chips, which

are connected to one sensor using the bump bonding technique. The 5 pixel chips with 8192 pixel cells each are connected to one sensor ladder containing 40,960 diodes. In the bump bonding process Sn-Pb solder joints of the size of 25 µm connect the sensor to the pixel chip. Fig. 5 shows a magnified bump bond on a pixel chip [5] and a detector ladder.

5) Read-out Multi-chip-module (MCM) The read-out and control electronics of the pixel chips is

located on a multi chip module (MCM). The MCM is 110 mm long and 11 mm wide (see fig. 8).

The ASICs are mounted on the MCM as bare die for space constraints. A custom developed optical transceiver module is used for data communication. The optical module contains two PIN diodes and one laser diode, housed in a silicon package. The module is extremely

Figure 8. Multi-chip-module – MCM.

Figure 5. top: Magnified bump bond on a pixel chip. Bottom: Sensor ladder.

Figure 6. Artistic view of the bus with a ladder and magnified picture of the bonding pads on the bus.

Figure 7. Image of the wire bonds between the bus and the pixel chips (on the left) and the bus and the MCM (on the right).

compact with a floorprint of 16 mm x 6 mm and a thickness of 1.2 mm. The module has bond pads for electrical connections. Space constraints limit the implementation of stress relief on the fibre pigtails, which therefore require very careful handling [6].

6) Aluminium/polyimide laminate – pixel bus The aluminium/polyimide laminate, the so called bus,

connects the 10 pixel chips to the read-out MCM and to the power supply. To keep material budget at a minimum the conductive material used is aluminium. The connections from the pixel chips to the bus and from the MCM to the bus is done via wire bonds.

The bus has a thickness of 250 μm and has 5 layers. Two layers for the power supply (50 μm thick) and 3 layers for signal routing (10 μm thick). In order to suppress vias for the power supply connection each layer of the bus is accessible for wire bonding because each subsequent layer is 500 μm shorter than the layer below, see fig. 6 and 7. In total more than 1000 wire bonds are used in the half stave.

7) Copper/polyimide laminates – Extenders Two-layer copper/polyimide laminates are connected to

the multi chip module (MCM extender) and to the bus (bus extenders) to provide power to the read-out electronics and the sensors. Each half stave is supplied with 1.8 V/5 A for the pixel chips and 2.5 V/0.2 A for the multi chip module.

8) Carbon fiber support and cooling A carbon fiber support with 200 µm thickness made of

10 sectors was developed [7] to form the two barrel layers of the SPD, see fig. 1. Cooling lines are embedded in each sector. The tubes are made of PHYNOX (Co-Cr-Ni alloy) with 1 mm diameter and a wall thickness of 40 µm. The

two-phase evaporative cooling system is based on C4F10. In total 1.5 kW are dissipated in the SPD. The operating temperature is set at 22 ± 5 C.

C. Material budget The ALICE detector design relies on the low material

budget of the Silicon Pixel Detector. As a result the materials used are as thin as possible using wherever possible light weight material. Table 1 shows the type, the thickness and the radiation length of the material along the particle trajectory in the active area. The overall radiation length X0 is estimated to smaller than 1 % per layer.

D. Full system and production tests Full system tests in the laboratory and in beam setups of

the entire electronics chain for two half staves including the MCM, the optical links, the off detector electronics, the ALICE trigger system and the ALICE data acquisition system have been performed [8].

Automated production setups have been developed for all components. After each production process of the half stave and the sector the tests are repeated to ensure quality control [9].

E. Summary The tight material budget and the limitation in physical

dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. The basic on detector building block of the SPD, the half stave, has successfully been tested and mechanically integrated in the SPD sector.

REFERENCES [1] A. Kluge et al., The Read-Out system of the ALICE pixel detector,

Proceedings of the International Workshop on Semiconductor Pixel Detectors for Particles and X-Rays (PIXEL2002), Monterey, CA, 2002, eConf C020909 (2003).

[2] A. Kluge et al., The ALICE Silicon Pixel Detector Front-end and Read-out Electronics, Proceedings of the Vertex 2004, Como, submitted to NIM A.

[3] K. Wyllie et al., A pixel readout chip for tracking at ALICE and particle identification at LHCb, Fifth workshop on electronics for LHC Experiment, CERN/LHCC/99-33, 29 October 1999, 93.

[4] P. Riedler et al., The ALICE Silicon Pixel Detector: System, Components and Test Procedures, Proceedings of the 10th symposium on semiconductor detectors, Wildbad Kreuth, Gemany, June 2005, to be published as special issue of NIMA.

[5] P. Riedler et al., ALICE Pixel Detector, Proceedings of the VERTEX 2003, Cumbria, United Kingdom.

[6] Boccardi, A. et al., Integration and test of the ALICE SPD readout chain, 10th Workshop on Electronics for LHC and Future Experiments LECC 2004 , Boston, MA, USA , 13 - 17 Sep 2004 - pages 47-50.

[7] A. Pepato et al., ”The mechanics and cooling system for the silicon pixel detector (SPD) of ALICE”, submitted to Pixel 2005 Conference.

[8] I. Cali et al., Test, Qualification and Electronics Integration of the ALICE Silicon Pixel Detector Modules, Proceedings of the 10th ICATPP, Como, Sept. 2005.

TABLE 1. MATERIAL BUDGET OF ONE SPD LAYER SPD Element Thickness µm % X0

Al Bus

Kapton 60 0.021

Al power 100 0.112

Al signals [50% of total surface] 17.5 0.020

Glue Epoxy 70 0.016

SMD components 16.4 0.173

Total bus 0.341

Other Components

Pixel chip 150 0.160

Sensor 200 0.214

Bump bonds Sn 60%+Pb 40% 0.18+0.12 0.004

Grounding Foil-Kapton/Al 50+10 0.029

Glue Epoxy/thermal grease 200 0.049

Carbon fiber 200 0.106

Total components 0.561

Total bus and components 0.903