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Text Book: Silicon VLSI Technology
Fundamentals, Practice and ModelingAuthors: J. D. Plummer, M. D. Deal,
and P. B. Griffin
Class: ECE 6466 “IC Engineering”Instructor: Dr. W. Zagozdzon-Wosik
INTRODUCTION - Chapter 1 in the Text
• This course is basically about silicon chip fabrication, the technologies used to manufacture ICs.• We will place a special emphasis on computer simulation tools to help understand these processes and as design tools. • These simulation tools are more sophisticated in some technology areas than in others, but in all areas they have made tremendous progress in recent years.
• 1960 and 1990 integrated circuits. • Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).
Increasing chip size - ≈ 16% per year. “Creativity” in implementing functions.
Evolution of the Silicon Integrated Circuits since 1960s
Increasing: circuit complexity, packing density, chip size, speed, and reliability
Decreasing: feature size, price per bit, power (delay) product
1960s1990s
G. Marcyk
http://www.extremetech.com/computing/116561-the-death-of-cpu-scaling-from-one-core-to-many-and-why-were-still-stuck
Dennard Scaling Expanded Moore’Law
•How to scale other parameters (oxide thickness, length, doping) •To get Moore’s Law
~ 2005 collapse of scaling
Use innovations: •Materials •Designs (FinFET, FD-SOI etc.)•Architecture (multi-core) for parallelized programs end product still too slow and too high power•Multi-core is power limited
http://www.extremetech.com/computing/116561-the-death-of-cpu-scaling-from-one-core-to-many-and-why-were-still-stuck
Chip Architecture May not Solve the Problem with Scaling and Performance
Physics/chemistry/biology
come to the rescue
for transistor designs
• The era of “easy” scaling is over. We are now in a period where technology and device innovations are required. Beyond 2020, new currently unknown inventions will be required.
Cell dimensions
Atomic dimensions
Device Scaling Over Time
Era of Simple Scaling
Scaling + Innovation(ITRS)
Invention
~16% increase in complexity each year (now:6.3% for µP, 12% for DRAM)
~13% decrease in feature size each year (now: ~10%)
0.25µm in 1997
G. Marcyk, Intel
1997 1999 2001 2004 2007 2010 2013 2016
2 nodes
High K gates
Trends in ScalingSi Microeletronics and MEMS
• 1990 IBM demo of Å scale “lithography”. • Technology appears to be capable of making structures much smaller than currently known device limits.
ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.
• Assumes CMOS technology dominates over entire roadmap.• 2 year cycle moving to 3 years (scaling + innovation now required).
Trends in Increasing Integration Scale of CircuitsPast, Present, and Future ICs
Historical Perspective
• Invention of the bipolar transistor - 1947, Bell Labs.
• Shockley’s “creative failure” methodology
• Grown junction transistor technology of the 1950s
Building Blocks of Integrated Circuits
Bipolar Transistors(BJT) and Metal Oxide Semiconductor Field Effect Transistors (MOSFET) with n- and p-type channels.
Fabrication of Bipolar Transistors in the 1950s
Ge used as a crystal, III and V group atoms used as dopants
Al wires
Exposed junctions had degraded surface properties and no possibility of connecting multiple devices
• Alloy junction technology of the 1950s.
p-n-p transistor
3rd group
Evolution of the Fabrication Process
The Mesa Design of Bipolar Transistors
Bell Lab, 1957, Double Diffused Process
Solid state B diffusion
Solid state P diffusion
Contacts alloyed
Mesa etched
Advantage: Connection of multiple devices but no ICs
Disadvantage: Degradation by exposed junctions at the surface
Evolution of the Fabrication Process: The Planar Design of Bipolar Transistors
Implementation of a masking oxide to protect junctions at the Si surface
Boron diffusionSiO2
Mask
Oxidation possible for Si not good for Ge
Oxidation and outdiffusion
Lithography to open window in SiO2
Phosphorus diffusion through the oxide mask
Beginning of the Silicon Technology and the End of Ge devices
The planar process of Hoerni and Fairchild (1950s)
Photolithography used for Pattern Formation
Beginning of Integrated Circuits in 1959Kilby (TI) and Noyce (Fairchild Semiconductors)
• Basic lithography process which is central to today’s chip fabrication.
• Sensitive to light• Durable in etching
Alignment of Layers to Fabricate IC Elements
Emitter
Collector
Resistor
BaseResistor
• Lithographic process allows integration of multiple devices side by side on a wafer.
• Bipolar Transistor and resistors made in the base region
•Accuracy of placement ~1/4 to 1/3 of the linewidth being printed
Vcc
C
B
E
BJT
0V
Contact to collector
R=L/W•Rs
Schematic Cross-Section of Modern CMOS Integrated Circuit with Two Metal Levels
IC is located at the surface of a Si wafer (~500µm thick)
PMOS NMOS
Via
Interconnect
Silicide
Oxide Isolation
M1
M2
OXIDE
TiN
Modern IC with a Five Level Metallization Scheme.
Planarization
• Actual cross-section of a modern microprocessor chip. Note the multiple levels of metal and planarization. (Intel website).
Computer Simulation Tools (TCAD)
•Most of the basic technologies in silicon chip manufacturing can now be simulated.Simulation is now used for:
• Designing new processes and devices.• Exploring the limits of semiconductor devices and
technology (R&D).• “Centering” manufacturing processes.• Solving manufacturing problems (what-if?)
• Simulation of an advanced local oxidation process.
• Simulation of photoresist exposure.
Semiconductors: Si, Ge, and Compound (III-V, II-VI)
Four valence electrons
Covalent bonding: no free electrons at 0K
P-type dopants
N-type dopants
Review: materials and devices(after Streetman & Kano)
Dopants have• to be compatible with processing (ex. slow diffusion through oxide)• to have high solubility in Si
Intrinsic Semiconductor
Electron and hole generation occur at elevated temperature (above 0K). n=p
Energy Band Gap determines the intrinsic carrier concentration. ni EgGe< EgSi< EgGaAs
For devices we need concentrations: n and p>>ni
N- and p-type semiconductor
n≈ND
p≈NA
Ingot crystal
Possible dopant deactivation & defect formation
Resistivity as a Function of Dopant Concentration
=1/(qµnn+qµpp)
µ carrier mobility depends on scattering e.i. dopants, lattice imperfections (defects) andvibration (temperature)
µn>µp
Electrical Properties of Semicondutors Explained by a Band Model and Bond Model
n=pn=p=ni
Intrinsic (Undoped) Silicon
Energy Gap T>0K
Electrical Properties of Semicondutors Explained by a Band Model and Bond Model
n-type Silicon doped with As
Very small ionization energies ED and EA
n=NAs
moves
Dopant Ionization
nn>>pn ni≈pi
n-type semiconductor
intrinsic semiconductor
ni=1.45x1010cm-3 at RT (300K)
Distribution of Free Carries (electrons and holes) Obeys Pauli Exclusion Principle
Intrinsic Semiconductor n-type Semiconductor p=type Semiconductor
Conduction Band
Valence Band
Fermi level is the energy at which the probability of finding an electron F(E) is 0.5
below Ei
above Ei
p=Na
n=Nd
Fermi Dirac probability function:
Majority carriers
EF ≈Eg/2
Majority carriers
Density of states
Energy
Probability function Density of electrons and holes
Carriers’ Statistics
Effective density of states NC and NVF-D statistics becomes Boltzmann if E-EF>>kT (low doped)
n=niexp(EF-Ei/kT)
p=niexp(Ei-EF/kT)
np=ni2
Pauli exclusion principle important here
Parabolicdensity of states
Carrier Concentrations
n= Ncexp[-(EC-EF)/kT]=niexp(EF-Ei/kT)
p= Ncexp[-(EF-EV)/kT]= niexp(Ei-EF/kT)
np=ni2 =NCNVexp(-EG/kT)=KT3exp(- EG/kT)
EG=
EC
EV
EC-EV Band gap
EF
For small dopant concentrations or close to the intrinsic conditions (ex. at processing temperatures) charge neutrality should be used:
ND++p=NA
-+n then
n=1/2[N+D- N-
A)+√(N+D - N-
A)2+4ni2]
p=1/2[N-A -N+
D)+√(N-A - N+
D)2+4ni2]
Heavy doping moves EF to EC
Energy Band Dependence on Temperature
Larger temperature weakens the bonding between atoms causing the band gap energy EG (energy needed to free e-h pairs) to decrease
EG(eV)=1.17-4 -4. 73x10-4T2/(T+636)≈1.16 - (3x10-4)T
EG shrinks with T
EF
Example: doping by As and B results in p-type Si at RT
Energy levels for shallow dopants are close to the majority carrier bands
and in intrinsic Si at 1000°C
RT 1000°C
n≈p≈ni at 1000°C
p>>n
Recombination of Carriers
Si is an indirect semiconductor so indirect recombination (Shockley-Read-Hall) occurs through traps located in the mid-gap
intrinsic Si n-type Si; a trap (below EF) is always filled with electron=majority carrier and waits for a minority hole.
R=1/vthNt
lifetime capture cross sectionthermal velocity, and traps
Carier Recombination and Generation
Traps (defects,metal impurities) present in silicon act either to annihilate carriers (recombination) or produce (generation) them.
SRH recombination/generation rate
lifetime r≠g
Umax for ET=Ei
np>ni2 U>0 recombination
np<ni2 U<0 generation
s=vthNit
Surface of Si with traps lead to the surface recombination velocity, which affects carrier lifetime
Semiconductor Devices
Reverse biased diode Forward biased diode
p-n Diodes
after Kano, Sem. Dev.
n+ for low resistance
p-n Diodes at Thermal Equilibrium
Dopants’ positions are fixed
Carriers move and create depletion layers
after Kano, Sem. Dev.
Majority holes
Minority holes
Majority electronsMinority
electrons
p-n Diodes at Thermal Equilibrium
Uncompensated acceptors and donors
At thermal equilibrium charge neutrality qN+
dxn=qN-Axp leads to asymmetrical depletion layers
Electric field only in the depletion layer
p-n Diodes at Thermal Equilibrium
Build-in voltage determined by doping on both sides of the p-n junction
No current flows at thermal equilibrium
after Kano, Sem. Dev.
n0n≈ND
p0n≈ni2/ND
p-n Diodes Under Bias
Reverse biased diode
Forward biased diode
Majority electrons (and holes) diffuse, become minority carriers and produce large current
holes
(- +)
(+ -)
Minority electrons and holes drift (small current)
after Kano, Sem. Dev.
I~exp(qV/kT)I
V
I
V
p-n Diodes Under Forward Bias
Depletion layer shrinks
Electric field decreases
Junction potential decreases by Va
Energy barrier decreases by qVa
after Kano, Sem. Dev.
J
J~exp(qVa/kT)
p-n Diodes Under Reverse Bias
Depletion layer spreads mainly to the low doped side
Electric field increases
Junction potential increases by Va
Energy barrier increases by qVa
after Kano, Sem. Dev.
J0A
p-n Diodes Under Bias
Carrier Injection and Extraction
Current distribution in a p-n diodeFor the forward biasing condition
after Neudeck
No recombination assumed in the SCR
Breakdown of a p-n Diode
Zener effect Avalanche effect
after Kano and Streetman
Breakdown Voltage of a p-n Diode
after Kano and Streetman
Eg
5-7V
• Ebr field increases with ND but not very much• Wdepl~1/√ND
Vbr=Ebr•Wdepl so Vbr decreases with ND
Transistors for digital and analg applications
MOSFET and Bipolar Junction Transistors
Bipolar Transistors
E-B junction is forward biased=injects minority carriers to the baseBase (electrically neutral) is responsible for electron transport via diffusion (or drift also if the build in electric field exist) to collectorC-B diode is reverse biased and collects transported carries
VBE>0 VBC<0
IE=IEn+IEp IC=IE<1
IB=IEp+Irec
IE IC
IB
Bipolar Junction Transistors
n-p-nIntegrated circuit BJT
p-n-p Individual device
Bipolar Junction Transistors
minority carriers
Injectedelectrons
Extracted electronsholes
Forwards bias Reverse bias
Bipolar Junction Transistors
Currents’ Components
small
Bipolar Junction Transistors
Forward Operation Mode
Early Effect
Early Voltage
Bipolar Junction Transistors
Breakdown Voltages
Common BaseCommon Emitter
Collector-Base junction
Bipolar Junction Transistors
Current Gain =
Gummel Plot
Kirk Effect
Recombination in the E-B SCR
IC/IB
Bipolar Junction Transistors and a Switch
SchottkyDiode used in n-p-n BJTs forfaster speed
MOS Field Effect Transistors (MOSFET)
NMOS and PMOS (used in CMOS circuits)
VG>VT to create strong inversion
depletion
Oxide
Operation of NMOS-FET
Linear Region, Low VD
Saturation Region, Channel Starts to Pinch-Off
Saturation Region, channel shortens beyond pinch-off, L’<L
Operation of MOS-FET
ID(VD)
Channel-Length-Modulation(Shorten by L)
ID=kp[(VG-VT)VD-VD2/2
Device transconductancekp=µnCoxW/L larger for NMOS than PMOSIn CMOS for compensation use Wp>Wn
Scaled Down NMOS
DIBL
Proximity of the drain depletion layer charge sharing DIBL
Modern MOS Transistors Gate
LDDLDD used to reduce the electric field in the drain depletion region and hot carrier effects
Self aligned contacts decrease the resistance
isolation
DrainSource
Semiconductor Technology Families
First circuits were based on BJT as a switch because MOS circuits limitations related to large oxide charges
isolation
BL
n-p-n
NMOS and CMOS Technologies
Enhancement NMOS Depletion NMOS
1970s
NMOS PMOS1980s and beyond
Smaller power consumption
Challenges For The Future• Having a “roadmap” suggests that the future is well defined and there are few challenges to making it happen.
• The truth is that there are enormous technical hurdles to actually achieving the forecasts of the roadmap. Scaling is no longer enough.
• 3 stages for future development:
Materials/process innovationsNOW
Device innovationsIN 5-15 YEARS
Beyond Si CMOSIN 15 YEARS??
“Technology Performance Boosters” Invention
???
Gate
Source Drain• Spin-based devices • Molecular devices• Rapid single flux quantum• Quantum cellular automata• Resonant tunneling devices• Single electron devices
Plummer et al.
Broader Impact of Silicon Technology
Tip on Stage Individual Actuator Part of 12 x 12 arrayCornell University
-0.75V
-2.5V
-2.25V
-2V
-1.75V
-1.5V
-1.25V
-1V
-0.5V
Stanford, Cornell
• Many other applications e.g. MEMs and many new device structures e.g. carbon nanotube devices, all use basic silicon technology for fabrication.
Source
Gate
Drain
SiO2
Plummer et al.
Summary of Key Ideas• ICs are widely regarded as one of the key components of the information age.
• Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry.
• For more than 40 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true.
• CMOS has become the dominant circuit technology because of its low DC power consumption, high performance and flexible design options. Future projections suggest these trends will continue at least 15 more years.
• Silicon technology has become a basic “toolset” for many areas of science and engineering.
• Computer simulation tools have been widely used for device, circuit and system design for many years. CAD tools are now being used for technology design.
• Chapter 1 also contains some review information on semiconductor materials semiconductor devices. These topics will be useful in later chapters of the text.
Plummer et al.