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VDSM Testing 1999-2003 1999-2003 Testing Solutions for Very Deep Sub-Micron CMOS Technologies University of Ioannina University of Ioannina Dept. of Computer Science Dept. of Computer Science Ioannina - Greece Ioannina - Greece University of Athens University of Athens Dept. of Informatics & Telecommunications Dept. of Informatics & Telecommunications Athens - Greece Athens - Greece University of Patras University of Patras Dept. of Computer Engineering & Informatics Dept. of Computer Engineering & Informatics Rio - Patras - Greece Rio - Patras - Greece Southern Illinois University Southern Illinois University Dept. of Electrical & Computer Engineering Dept. of Electrical & Computer Engineering Carbondale - USA Carbondale - USA

Testing Solutions for Very Deep Sub-Micron CMOS Technologies

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Testing Solutions for Very Deep Sub-Micron CMOS Technologies. University of Ioannina Dept. of Computer Science Ioannina - Greece. University of Athens Dept. of Informatics & Telecommunications Athens - Greece. Southern Illinois University Dept. of Electrical & Computer Engineering - PowerPoint PPT Presentation

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Page 1: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

VDSM TestingVDSM Testing1999-20031999-2003

Testing Solutions for Very Deep Sub-Micron CMOS TechnologiesTesting Solutions for Very Deep Sub-Micron CMOS Technologies

University of IoanninaUniversity of IoanninaDept. of Computer ScienceDept. of Computer Science

Ioannina - GreeceIoannina - Greece

University of AthensUniversity of AthensDept. of Informatics & TelecommunicationsDept. of Informatics & Telecommunications

Athens - GreeceAthens - Greece

University of PatrasUniversity of PatrasDept. of Computer Engineering & InformaticsDept. of Computer Engineering & Informatics

Rio - Patras - GreeceRio - Patras - Greece

Southern Illinois UniversitySouthern Illinois UniversityDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering

Carbondale - USACarbondale - USA

Page 2: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

22VDSM TestingVDSM Testing1999-20031999-2003

Delay Testing“On-Line and Off-Line DFT Techniques”

Delay Testing“On-Line and Off-Line DFT Techniques”

• A Zero Aliasing Built-In Self TesA Zero Aliasing Built-In Self Test Tet Technique for Delay Fault chnique for Delay Fault TestingTesting – DFT 1999

• A Zero Aliasing Built-In Self TesA Zero Aliasing Built-In Self Test Tet Technique for Delay Fault chnique for Delay Fault TestingTesting – DFT 1999

• A Versatile Built-In Self Test Scheme for Delay Fault Testing – DATE 2000

• A Versatile Built-In Self Test Scheme for Delay Fault Testing – DATE 2000

Page 3: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

33VDSM TestingVDSM Testing1999-20031999-2003

CLEAR

Error Indication Output

Dflip-flop

ENB

CL

CKD

VDD

TPG

PIPO Register

CUT

Primary Outputs

Primary Inputs

R-CLK

N/T

G-CLK

n

nn

m

m

m

MUX

Transition DetectionCircuitry

E

DFT for Delay Fault TestingDFT for Delay Fault TestingDFT for Delay Fault TestingDFT for Delay Fault Testing

DFT-99

Page 4: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

44VDSM TestingVDSM Testing1999-20031999-2003

Start of CurrentTest Phase

Application of Vi

End of ValidData Output

Responses

Capture of Vi

Response

Start of ValidData Output

Responses

End of CurrentTest Phase

Application of Vi+1

Τ1 Τ2 Τ3 Τ4Valid ResponseErroneousResponse

ErroneousResponse

R-CLK

G-CLK

Test Phase

ENB

dmax

Off-Line Delay TestingOff-Line Delay TestingOff-Line Delay TestingOff-Line Delay Testing

DFT-99

Page 5: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

55VDSM TestingVDSM Testing1999-20031999-2003

Τ1 Τ2 Τ3 Τ4

Valid Responses

Erroneous Response

R-CLK

NormalSystemClock

Test Phase

ENB dmax

PrimaryOutputs

Stable States

On-Line Delay TestingOn-Line Delay TestingOn-Line Delay TestingOn-Line Delay Testing

DFT-99

Page 6: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

66VDSM TestingVDSM Testing1999-20031999-2003

TPGTPGTPGTPG

CUTCUT

Primary Outputs

Primary Inputs

ENB

N/T

G-CLK

n

n n

m

MUXMUX

ERR

TDUTDUTDUTDU

A Current Mode Technique for Delay TestingA Current Mode Technique for Delay TestingA Current Mode Technique for Delay TestingA Current Mode Technique for Delay Testing

. . .

CUTCUT

BICSBICS

TDUTDU

Primary Outputs

ENB

ERR

m

m

Dummy Buffers Virtual Ground

DATE - 00

Page 7: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

77VDSM TestingVDSM Testing1999-20031999-2003

DATE - 00

Test Phase

Valid Response

Erroneous Response

Erroneous Response

Τ1 Τ2 Τ3 Τ4

G-CLK

ENB

Start of Current Test PhaseApplication of Vj

Enable TDU

End of Valid Data Output Responses

Enable TDU Start of Valid Data Output Responses

Disable TDU

End of Current Test PhaseStart of Next Test Phase

Application of Vj+1

dmax

Off-Line Delay TestingOff-Line Delay TestingOff-Line Delay TestingOff-Line Delay Testing

Page 8: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

88VDSM TestingVDSM Testing1999-20031999-2003

On-Line Delay TestingOn-Line Delay TestingOn-Line Delay TestingOn-Line Delay Testing

Τ1 Τ2 Τ3 Τ4Valid

ResponseErroneous Response

Erroneous Response

Detection Phase jDetection Phase j+1

CLK

ENB

Start of Detection PhaseInput Ij

Enable TDU

End of Valid Data Output Responses

Start of Detection PhaseInput Ij+1

Enable TDU Start of Valid Data Output Responses

Disable TDU

Start of Valid Data Output Responses

Disable TDU

Detection Phase j-1

DATE - 00

Page 9: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

99VDSM TestingVDSM Testing1999-20031999-2003

Concurrent Testing“Soft and Timing Error Detection

Circuits and Techniques”

Concurrent Testing“Soft and Timing Error Detection

Circuits and Techniques”

• A Hierarchical Architecture for Concurrent Soft Error Detection

Based on Current Sensing – IOLTW 2002

• A Hierarchical Architecture for Concurrent Soft Error Detection

Based on Current Sensing – IOLTW 2002

• A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs – IOLTS 2003

• A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs – IOLTS 2003

Page 10: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1010VDSM TestingVDSM Testing1999-20031999-2003

Output FFCombinational

LogicERR

OUT

CLK

FFO

Functional Circuit

IN

Monitoring Circuit

Output FFCombinational

LogicERR

OUT

CLK

FFO

Functional Circuit

IN

Monitoring Circuit

The Time Redundancy TechniqueThe Time Redundancy TechniqueThe Time Redundancy TechniqueThe Time Redundancy Technique

Page 11: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1111VDSM TestingVDSM Testing1999-20031999-2003

Current Mode Comparator

ERR

ENB

VDD

OUT FFO

Activation Circuit (AC)

BICSBICSSN

DTCT

ENBPreset

ErrorFF DTCT

Current Mode ComparatorCurrent Mode ComparatorCurrent Mode ComparatorCurrent Mode Comparator

OUT

CLK

ENB

FFO

ERR

Preset ActionSensing Mode

Transient Pulse

IOLTW - 02

Page 12: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1212VDSM TestingVDSM Testing1999-20031999-2003

The Hierarchical Error Detection ArchitectureThe Hierarchical Error Detection ArchitectureThe Hierarchical Error Detection ArchitectureThe Hierarchical Error Detection Architecture

AC11 AC1m ACnm

BICS

. . .

SN

EIFERRMultiple Lines

Current Sensing Comparator(ML-CSC)

OUT & FFOPair

ACn1

. . . . . .m m

Functional Circuit

n

CM1 CMn

1st LevelActivation

2nd LevelPre-Sense

3rd LevelFinal Sense

CL1 CLn

N1 Nn

CSC_out

Cluster ofPairs

OUT11 OUTnmFFO11 FFOnmOUT1m FFO1m OUTn1 FFOn1

IOLTW - 02

Page 13: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1313VDSM TestingVDSM Testing1999-20031999-2003

ERR

ENB

VDD

OUT FFO

Activation Circuit (AC)

NCSC_out

ENB Preset

Multiple Lines Current Sensing Comparator

ML-CSC

EIFSN BICSBICS

Current Mirror (CM)

From the rest ACs of the cluster

From the rest CMs

Multiple Lines Current Sensing ComparatorMultiple Lines Current Sensing ComparatorMultiple Lines Current Sensing ComparatorMultiple Lines Current Sensing Comparator

IOLTW - 02

Page 14: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1414VDSM TestingVDSM Testing1999-20031999-2003

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .EN

EN

INL

INR

EN

EN

SenseAmplifier

(SA)

ERR

FFOk

OUTk

FFOk

OUTk

MFL

MFR

MCL

MCR

SBL

SBR

RESET

SCLK

EIFFSAO

EN

VDD

VDD

Gnd

Gnd

PSB

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .EN

EN

INL

INR

EN

EN

SenseAmplifier

(SA)

ERR

FFOk

OUTk

FFOk

OUTk

MFL

MFR

MCL

MCR

SBL

SBR

RESET

SCLK

EIFFSAO

EN

VDD

VDD

Gnd

Gnd

PSB

Sense Amplifier Based DetectorSense Amplifier Based DetectorSense Amplifier Based DetectorSense Amplifier Based Detector

IOLTS - 03

Page 15: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1515VDSM TestingVDSM Testing1999-20031999-2003

OUT

FFO

CLK

EN

ERR

Unknown Data Valid Data Erroneous Data

Set-Up

Hold

MonitoringPhase

Set-Up

Hold

MonitoringPhase

Error Free Error Present

FFO = OUT FFO OUT

δmax

dmax

Normal Phase Normal PhaseNormal Phase

OUT

FFO

CLK

EN

ERR

Unknown Data Valid Data Erroneous Data

Set-Up

Hold

MonitoringPhase

Set-Up

Hold

MonitoringPhase

Error Free Error Present

FFO = OUT FFO OUT

δmax

dmax

Normal Phase Normal PhaseNormal Phase

Timing WaveformsTiming WaveformsTiming WaveformsTiming Waveforms

IOLTS - 03

Page 16: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1616VDSM TestingVDSM Testing1999-20031999-2003

100

150

200

250

300

350

400

450

500

0 100 200 300 400 500 600

Monitored Pairs

De

tect

ion

Tim

e

Detection Time vs Monitored PairsDetection Time vs Monitored PairsDetection Time vs Monitored PairsDetection Time vs Monitored Pairs

IOLTS - 03

Page 17: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1717VDSM TestingVDSM Testing1999-20031999-2003

IDDQ Testing“The Challenge of VDSM Technologies”

IDDQ Testing“The Challenge of VDSM Technologies”

• Extending the Viability of IExtending the Viability of IDDQDDQ Testing in the Deep Submicron Era Testing in the Deep Submicron Era – ISQED 2002

• Extending the Viability of IExtending the Viability of IDDQDDQ Testing in the Deep Submicron Era Testing in the Deep Submicron Era – ISQED 2002

• An Embedded IDDQ Testing Architecture and Technique – ISQED

2003

• An Embedded IDDQ Testing Architecture and Technique – ISQED

2003

Page 18: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1818VDSM TestingVDSM Testing1999-20031999-2003

Background Current CompensationBackground Current CompensationBackground Current CompensationBackground Current Compensation

T_EN

Vdd

Fault IndicationOutput

Gnd

EN

Gnd

Vdd

LeakageCompensator

IB IDEF

BCCBCC

Higher Current ResolutionITH as low as BICS and/or BCC permit

Higher Current ResolutionITH as low as BICS and/or BCC permit

BICSBICS

CUTCUT ITH

ISQED - 02

Page 19: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

1919VDSM TestingVDSM Testing1999-20031999-2003

The BCC Based IThe BCC Based IDDQDDQ Testing Technique Testing TechniqueThe BCC Based IThe BCC Based IDDQDDQ Testing Technique Testing Technique

Vdd

Fault IndicationOutput R

BICSR

Gnd

ENRT_EN

IBR

BCCBCC

Vdd

BICSL

Gnd

ENL T_EN

Fault IndicationOutput L

Vdd

CurrentMirror

AmplifierL to R

MIR_L_to_R

Gnd

CurrentMirror

AmplifierR to L

MIR_R_to_L

Gnd

Vdd

IBL =R IBR

IBL IBR =L IBL

sub-CUTL sub-CUTR

ISQED - 02

Page 20: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2020VDSM TestingVDSM Testing1999-20031999-2003

BCC & BICSs

Gnd

V_GndRV_GndLCUTCUT

T_EN

sub-CUTL sub-CUTR

T_EN

Power Supply DistributionPower Supply DistributionPower Supply DistributionPower Supply Distribution

ISQED - 02

Page 21: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2121VDSM TestingVDSM Testing1999-20031999-2003

0 1 0

Scan RegisterScan Register

SEL1 SEL2 SELn

1

Multiple Current Sink BCC ImplementationMultiple Current Sink BCC ImplementationMultiple Current Sink BCC ImplementationMultiple Current Sink BCC Implementation

Gnd

SEL1 SEL2IBL

T_EN

MIR_L_to_R

Background Current

from sub-CUTL

Background Current

from sub-CUTR

Current Current MirrorMirror

AmplifierAmplifier

To the BICSRSELn

W1/L Wn/LW2/L

IBRL2 IBLIDEF

• IEEE 1149.1IEEE 1149.1• IEEE P1500IEEE P1500• VSIA TST 2 1.0VSIA TST 2 1.0

ISQED - 02

Page 22: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2222VDSM TestingVDSM Testing1999-20031999-2003

SCUT 1SCUT 1 SCUT 2SCUT 2 SCUT nSCUT n. . .

VDD

CUT

Pass / Fail

IDDQ RegisterScan In

BICSBICS

SDFFSDFF

T/N1 T/N1

VSS

DD

Decoder

ENB

T/Nn T/Nn

VSS

T/N2 T/N2

VSS

T/N1 T/N2 T/Nn

VSS

SL

MSL

MN1 MT1 MN2 MNnMT2 MTn

. . .

SelectCircuitry

Virtual Grounds

REF

ISQED - 03

Embedded IEmbedded IDDQDDQ Testing TestingEmbedded IEmbedded IDDQDDQ Testing Testing

Page 23: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2323VDSM TestingVDSM Testing1999-20031999-2003

CUT

IR Register

Decode LogicTDI

Dev. ID Register

BICSBICS SDFFSDFF

DD

BypassBypass

IDDQ Register

Decoder

TAPController

FFFF

ENB

Shift_IRClock_IRUpdate_IRReset

Shift_DRClock_DRUpdate_DRRun_Test

TDO

TCK

TMS

TRST

MUX-1

MUX-2

PI PO

.

.

..B

SR

BSR

ISQED - 03

IEEE 1149.1 Based IIEEE 1149.1 Based IDDQDDQ Testing Architecture Testing ArchitectureIEEE 1149.1 Based IIEEE 1149.1 Based IDDQDDQ Testing Architecture Testing Architecture

Page 24: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2424VDSM TestingVDSM Testing1999-20031999-2003

START

Scan-InTest Vector

Scan-InIDDQ Register

IDDQSensing

Another SCUT?

Another TestVector?

END

Yes

Yes

No

No

Scan-OutSDFF

IIDDQDDQ Testing Flow Diagram Testing Flow DiagramIIDDQDDQ Testing Flow Diagram Testing Flow Diagram

ISQED - 03

Page 25: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2525VDSM TestingVDSM Testing1999-20031999-2003

ISQED - 03

VSS

CUTCUT

<T/Ni

BICS IEEE 1149.1

. . .

SCUT1

SCUT2

SCUTn

VDD

SL

REF

PASS/FAIL

ENB

SelectCircuitry

TDI TCK TMS TDO

TRST

T/Ni>

MSL

MT2 MN2

MT1 MN1

MTn MNn

Power Supply DistributionPower Supply DistributionPower Supply DistributionPower Supply Distribution

Page 26: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2626VDSM TestingVDSM Testing1999-20031999-2003

Memory Testing“The Neighborhood Pattern Sensitive Fault Model”

Memory Testing“The Neighborhood Pattern Sensitive Fault Model”

• A Test Pattern Generation Unit for Memory NPSF Built-In Self Test – ICECS 2000

• A Test Pattern Generation Unit for Memory NPSF Built-In Self Test – ICECS 2000

Page 27: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2727VDSM TestingVDSM Testing1999-20031999-2003

ControlCircuitry

Gray Counter

Rotate

Submit

ParallelLoad

R_Rot

MSB LSB

P_LoadRot

Update

5

5

EndClk

Reset

TPG

A Deterministic TPG UnitA Deterministic TPG UnitA Deterministic TPG UnitA Deterministic TPG Unit

ICECS - 00

Page 28: Testing  Solutions  for Very Deep  Sub-Micron CMOS Technologies

2828VDSM TestingVDSM Testing1999-20031999-2003

ICECS - 00

FPGA ImplementationFPGA ImplementationFPGA ImplementationFPGA Implementation