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TESTING OF COMBINATIONAL LOGIC CIRCUITS. DIGITAL LOGIC CIRCUIT TESTING DEFINITIONS TYPICAL DIGITAL CIRCUIT TEST SETUP FAULT MODELS COMBINATIONAL LOGIC CIRCUITS TEST GENERATION EXCLUSIVE-OR METHOD PATH-SENSITIZING METHOD PATH-SESITIZING IN POPULAR GATES PATH-SESITIZING IN A NETWORK - PowerPoint PPT Presentation
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUIT TESTING DEFINITIONS TYPICAL DIGITAL CIRCUIT TEST SETUP
FAULT MODELS COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION EXCLUSIVE-OR METHOD PATH-SENSITIZING METHOD
PATH-SESITIZING IN POPULAR GATES PATH-SESITIZING IN A NETWORK A NETWORK WITH FAN-OUT COUNTER-EXAMPLE TO SINGLE-PATH SENSITIZING
UNTESTABLE FAULTS MULTIPLE OUTPUT NETWORKS FAULT DETECTION TEST SETS (FDTS)
FAULT TABLE REDUCTION – CHECK POINTS MINIMUM FDTS
____________________________________________________________________ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.Adapted from Digital Logic Circuit Analysis & Design, by Nelson, Nagle, Carroll, Irwin, Prentice-Hall,1995, Chapter 12, pages 739 to 757
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUIT TESTING TYPICAL DIGITAL CIRCUIT TEST SETUP
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
DIGITAL LOGIC CIRCUIT TESTING TYPICAL DIGITAL CIRCUIT TEST SETUP
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT MODELS (CONTINUES) Example: Consider the following circuit which has a
stuck-at-zero at wire 3 ,
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS: TEST GENERATION: DEFINITIONS
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS: TEST GENERATION: DEFINITIONS
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
Example : Find the fault table for all stuck-at faults of the following circuit (circuit 1)STEP 1 1
2
3
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f = x1 x2 + x3
X1X2
x3
Testx1x2x3
f f1/0 f1/1 f2/0 f2/1 f3/0 f3/1 f4/0 f4/1 f5/0 f5/1
0 0 0 0 0 0 0 0 0 1 0 1 0 1
0 0 1 1 1 0 1 1 0 1 1 1 0 1
0 1 0 0 0 1 0 0 0 1 0 1 0 1
0 1 1 1 1 1 1 1 0 1 1 1 0 1
1 0 0 0 0 0 0 1 0 1 0 1 0 1
1 0 1 1 1 1 1 1 0 1 1 1 0 1
1 1 0 1 0 1 0 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1
x3 x2+x3 x3 x1+x3 x1x2 1 x3 1 0 1
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD Example continues (STEP 2)
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: EXCLUSIVE-OR METHOD
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD
PATH-SESITIZING IN POPULAR GATES
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS TEST GENERATION: PATH-SENSITIZING METHOD
PATH-SESITIZING IN POPULAR GATES
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD PATH-SESITIZING IN A NETWORK
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT: ANOTHER EXAMPLE
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION - PATH-SENSITIZING METHOD: A NETWORK WITH FAN-OUT: ANOTHER EXAMPLE
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD COUNTER-EXAMPLE TO SINGLE-PATH
SENSITIZING
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
TEST GENERATION: PATH-SENSITIZING METHOD COUNTER-EXAMPLE TO SINGLE-PATH
SENSITIZING
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION – CHECK POINTS
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION – CHECK POINTS
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION – CHECK POINTS CHECK POINTS ARE:
ALL INPUT WIRES THAT ARE NOT FAN-OUT STEMS
ALL WIRES THAT ARE FAN-OUT BRANCHES OUTPUTS TO XOR GATES
FAN-OUT STEM REFERS TO THE WIRE PRECEDING THE FAN-OUT POINT.
FAN-OUT BRANCHES REFERS TO THE WIRES BEYOND THE FAN-OUT POINT.
EXAMPLE FOLLOWS
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT DETECTION TEST SETS (FDTS) FAULT TABLE REDUCTION – CHECK
POINTS EXAMPLE: FOR THE FOLLOWING CIRCUIT,
THE CHECK POINTS ARE 1, 3, 4 AND 5
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TESTING OF COMBINATIONAL LOGIC CIRCUITS
FAULT DETECTION TEST SETS (FDTS): MINIMUM FDTS: APPLYING THE PROCEDURE TO THE TABLE ON SLIDE 37
YIEDLS {010,011,101,110} AS A MINIMUM TEST SET. THE PETRICK FUNCTION, P, CAN BE USED TO REDUCE
THE TABLE: LABELLING THE TESTS ON THE TABLE P0,P1,P2,P3,P4,P5,P6,P7
P = (P6)(P2)(P3)(P2)(P6)(P4+P5)(P3)(P1+P5)P = P6 P2 P3 (P4+P5)(P1+P5) = P6 P2 P3 (P4 P1+P5)P = P6P2P3P4P1 + P6P2P3P5.
THE MINIMAL FDTS IS {P6,P2,P3,P5} = {110,010,011,101}
FOR LARGE FAULT TABLES, THE USE OF PROCEDURES FORSELECTING A NEAR MINIMAL IS MORE PRACTICAL.